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1. 发明公开

US20230291842A1 INFORMATION PROCESSING APPARATUS, ABNORMALITY DETECTION METHOD, STORAGE MEDIUM, AND INFORMATION PROCESSING SYSTEM 审中-公开
公开(公告)号：US20230291842A1
公开(公告)日：2023-09-14
申请号：US18177886
申请日：2023-03-03
申请人： Hideyuki KIHARA , Yusuke TANEDA , Yuta NAGATA
发明人： Hideyuki KIHARA , Yusuke TANEDA , Yuta NAGATA
IPC分类号： H04N1/00 , H04N1/60
CPC分类号： H04N1/00037 , H04N1/00013 , H04N1/6044
摘要： An information processing apparatus includes processing circuitry. The processing circuitry detects an abnormality in an image reading apparatus from a first spectral reflectance and a second spectral reflectance, the first spectral reflectance being generated based on data read from a reference white plate installed in the image reading apparatus, the second spectral reflectance being generated before generation of the first spectral reflectance, and identifies a cause of an abnormality in the image reading apparatus in a case where the processing circuitry detects the abnormality.

2. 发明公开

US20240291931A1 METHOD OF CREATING COLOR CHART DATA, INFORMATION PROCESSING APPARATUS FOR CREATING COLOR CHART DATA, COLOR CHART, IMAGE FORMING SYSTEM, AND NON-TRANSITORY RECORDING MEDIUM 审中-公开
公开(公告)号：US20240291931A1
公开(公告)日：2024-08-29
申请号：US18583896
申请日：2024-02-22
申请人： Hideyuki KIHARA , Yusuke TANEDA , Yuta NAGATA
发明人： Hideyuki KIHARA , Yusuke TANEDA , Yuta NAGATA
IPC分类号： H04N1/60
CPC分类号： H04N1/6044
摘要： A computer-implemented method of creating color chart data to be used for executing color adjustment on an image forming apparatus includes obtaining, from a color chart printed out by the image forming apparatus, color chart data including a color adjustment patch group in which a plurality of color patches used for executing the color adjustment are arranged adjacent to each other, determining, for one or more of the plurality of color patches included in the color adjustment patch group, whether color of the color patch and color of an adjacent color patch adjacent to the color patch are similar, and based on a determination that the color of the color patch and the color of the adjacent color patch are similar, creating color chart data in which the color patch and the adjacent color patch that are similar in color are arranged not to be adjacent to each other.

3. 发明申请

US20220141356A1 COLOR CHART, INFORMATION PROCESSING APPARATUS, AND INFORMATION PROCESSING SYSTEM 有权
公开(公告)号：US20220141356A1
公开(公告)日：2022-05-05
申请号：US17512960
申请日：2021-10-28
申请人： Hideyuki KIHARA , Yuta NAGATA , Yusuke TANEDA
发明人： Hideyuki KIHARA , Yuta NAGATA , Yusuke TANEDA
IPC分类号： H04N1/60
摘要： A color chart is for performing color adjustment on an image forming apparatus. The color chart includes identification information and a color adjustment patch. The identification information is on an image forming apparatus to which color adjustment is to be applied. The color adjustment patch includes a plurality of color patches for performing color adjustment on the image forming apparatus indicated by the identification information.

4. 发明申请

US20090198841A1 INTERFACE DETECTING CIRCUIT AND INTERFACE DETECTING METHOD 失效
标题翻译：接口检测电路和接口检测方法
公开(公告)号：US20090198841A1
公开(公告)日：2009-08-06
申请号：US12026730
申请日：2008-02-06
申请人： Masato YOSHIDA , Yoshihito KAWAKAMI , Shigenori ARAI , Hideyuki KIHARA
发明人： Masato YOSHIDA , Yoshihito KAWAKAMI , Shigenori ARAI , Hideyuki KIHARA
IPC分类号： G06F13/10
CPC分类号： G06F13/4295
摘要： An interface detecting circuit and interface detecting method are provided, whereby operations can be carried out depending on peripheral devices connected to USB terminals, and whereby the system can be simplified and software load can be reduced. A pull-down resistor is connected to an ID terminal of a Mini-A receptacle of a peripheral device, the voltage generated by the pull-down resistor, which is pulled down by the ID terminal of the Mini-A receptacle of the peripheral device, and a pull-up resistor, which is pulled up by the ID terminal of a Mini-B receptacle of a device, is detected in an analog fashion, using a detecting section comprised of comparators, and, via a logic section, a logic output is subjected to noise cancellation in a filter section and is memorized in a register section. The operations of other devices are determined according to the states memorized in the register section.
摘要翻译：提供了一种接口检测电路和接口检测方法，由此可以根据连接到USB端子的外围设备进行操作，从而可以简化系统并且可以减少软件负载。下拉电阻连接到外围设备的Mini-A插座的ID端子，由下拉电阻器产生的电压由外围设备的Mini-A插座的ID端子拉下并且使用由比较器组成的检测部分以模拟方式检测由设备的Mini-B插座的ID端子上拉的上拉电阻器，并且经由逻辑部分逻辑输出在滤波器部分进行噪声消除，并被存储在寄存器部分中。其他设备的操作根据存储在寄存器部分中的状态来确定。

5. 发明申请

US20100219878A1 SEMICONDUCTOR SWITCH CIRCUIT 有权
标题翻译：半导体开关电路
公开(公告)号：US20100219878A1
公开(公告)日：2010-09-02
申请号：US12776459
申请日：2010-05-10
申请人： Hideyuki KIHARA , Tomohiro UKAI , Kiyotaka INAGAKI
发明人： Hideyuki KIHARA , Tomohiro UKAI , Kiyotaka INAGAKI
IPC分类号： H03K17/687
CPC分类号： H03K17/6874 , H03K2217/0018 , H03K2217/0036 , Y10T307/747
摘要： A semiconductor switch circuit is provided that enables current consumption to be reduced even in a conduction state. A semiconductor switch circuit 100 has P-type MOS transistors Q101 and Q102 for conduction that share a source and are connected in series between an input/output terminal 101 and input/output terminal 102, a P-type MOS transistor Q103 and N-type MOS transistor Q105 having drains connected to the gate of Q101, a P-type MOS transistor Q104 and N-type MOS transistor Q106 having drains connected to the gate of Q102, and a control terminal 103 connected to the gates of the transistors. Further semiconductor switch circuit 100 is configured with the sources and back gates of Q103 and Q104 connected to the sources of Q101 and Q102. Therefore, it is possible to switch the path between input/output terminal 101 and input/output terminal 102 between a conduction state and non-conduction state by means of voltage control by voltage value Vcont of a control signal applied to control terminal 103.
摘要翻译：提供一种半导体开关电路，即使在导通状态下也能够降低电流消耗。半导体开关电路100具有用于导通的P型MOS晶体管Q101和Q102，其共享源极并串联连接在输入/输出端子101和输入/输出端子102之间，P型MOS晶体管Q103和N型具有连接到Q101的栅极的漏极的MOS晶体管Q105，具有连接到Q102的栅极的漏极的P型MOS晶体管Q104和N型MOS晶体管Q106以及连接到晶体管的栅极的控制端子103。进一步的半导体开关电路100被配置有与Q101和Q102的源极连接的Q103和Q104的源极和后门。因此，可以通过施加到控制端子103的控制信号的电压值Vcont通过电压控制来将输入/输出端子101和输入/输出端子102之间的路径切换到导通状态和非导通状态之间。

6. 发明申请

US20080116751A1 SEMICONDUCTOR SWITCH CIRCUIT 有权
标题翻译：半导体开关电路
公开(公告)号：US20080116751A1
公开(公告)日：2008-05-22
申请号：US11941365
申请日：2007-11-16
申请人： Hideyuki KIHARA , Tomohiro UKAI , Kiyotaka INAGAKI
发明人： Hideyuki KIHARA , Tomohiro UKAI , Kiyotaka INAGAKI
IPC分类号： H02B1/24
CPC分类号： H03K17/6874 , H03K2217/0018 , H03K2217/0036 , Y10T307/747
摘要： A semiconductor switch circuit is provided that enables current consumption to be reduced even in a conduction state. A semiconductor switch circuit 100 has P-type MOS transistors Q101 and Q102 for conduction that share a source and are connected in series between an input/output terminal 101 and input/output terminal 102, a P-type MOS transistor Q103 and N-type MOS transistor Q105 having drains connected to the gate of Q101, a P-type MOS transistor Q104 and N-type MOS transistor Q106 having drains connected to the gate of Q102, and a control terminal 103 connected to the gates of the transistors. Further semiconductor switch circuit 100 is configured with the sources and back gates of Q103 and Q104 connected to the sources of Q101 and Q102. Therefore, it is possible to switch the path between input/output terminal 101 and input/output terminal 102 between a conduction state and non-conduction state by means of voltage control by voltage value Vcont of a control signal applied to control terminal 103.
摘要翻译：提供一种半导体开关电路，即使在导通状态下也能够降低电流消耗。半导体开关电路100具有用于导通的P型MOS晶体管Q 101和Q 102，其共享源极并串联连接在输入/输出端子101和输入/输出端子102之间，P型MOS晶体管Q 103和具有连接到Q 101的栅极的漏极的N型MOS晶体管Q 105，具有连接到Q 102的栅极的漏极的P型MOS晶体管Q 104和N型MOS晶体管Q 106，以及连接到晶体管的栅极。另外的半导体开关电路100配置有连接到Q 101和Q 102的源极的Q 103和Q 104的源极和反向栅极。因此，可以通过施加到控制端子103的控制信号的电压值Vcont通过电压控制来将输入/输出端子101和输入/输出端子102之间的路径切换到导通状态和非导通状态之间。

7. 发明申请

US20100134147A1 TOLERANT BUFFER CIRCUIT AND INTERFACE 有权
标题翻译：容错缓冲电路和接口
公开(公告)号：US20100134147A1
公开(公告)日：2010-06-03
申请号：US12621776
申请日：2009-11-19
申请人： Kazuyo OHTA , Hideyuki KIHARA
发明人： Kazuyo OHTA , Hideyuki KIHARA
IPC分类号： H03K19/0948
CPC分类号： H03K17/08142 , H03K19/00315
摘要： A tolerant buffer circuit and interface are provided in which reverse inflow of current to a power supply voltage from an output terminal does not occur even if the output terminal is at a higher potential than an output circuit power supply voltage during open-drain operation in an output circuit of a semiconductor integrated circuit, or if the output circuit power supply voltage becomes 0 V. Tolerant buffer circuit 100 is provided with PMOS transistors Q111 and Q112 that are connected in series and that share a source between power supply terminal VDD1 and output terminal 102, NMOS transistor Q113 connected between output terminal 102 and ground terminal 101, inverter 121 output-connected to the gate of PMOS transistor Q111, inverter 122 output-connected to the gate of PMOS transistor Q112, and control circuit 130 that outputs first, second, and third control signals to PMOS transistor Q111, PMOS transistor Q112, and NMOS transistor Q113 respectively, and controls the on/off state of these MOS transistors.
摘要翻译：提供了一种容限缓冲电路和接口，其中即使输出端子在漏极开路操作期间的输出端子处于比输出电路电源电压高的电压的情况下，也不会发生电流与输出端子的电源电压的反向流入半导体集成电路的输出电路，或者输出电路电源电压为0V。容限缓冲电路100具有串联连接的PMOS晶体管Q111，Q112，并共用电源端子VDD1和输出端子如图102所示，连接在输出端子102和接地端子101之间的NMOS晶体管Q113，输出连接到PMOS晶体管Q111的栅极的反相器121，输出连接到PMOS晶体管Q112的栅极的反相器122，以及控制电路130，其输出第一，，第三控制信号分别连接到PMOS晶体管Q111，PMOS晶体管Q112和NMOS晶体管Q113，并控制开关状态这些MOS晶体管。

8. 发明申请

US20070201104A1 DATA RECEIVING APPARATUS 有权
标题翻译：数据接收装置
公开(公告)号：US20070201104A1
公开(公告)日：2007-08-30
申请号：US11676747
申请日：2007-02-20
申请人： Hideyuki KIHARA
发明人： Hideyuki KIHARA
IPC分类号： H04N1/00
CPC分类号： H04L25/40
摘要： A data receiving apparatus which makes it possible to obtain reliable received data during EOP period and a preceding period, and which makes it possible to receive serial data in a reliable manner. Data receiving apparatus 100 is provided with receiving comparator 102 which has first signal line 101a and second signal line 101b for differential input; NOR circuit 105 that outputs a logical output, as a trigger signal, at the time the first signal and the second signal have changed from out-of-phase to in-phase; and D-FF circuit 107 that retrieves, by means of a trigger signal from NOR circuit 105, and holds an output RCV of receiving comparator 102; wherein selection circuit 108 selects the output of receiving comparator 102, when the first signal of first signal line 101a and the second signal of second signal line 101b are out-of-phase with each other, and outputs, as received data, a value held in D-FF circuit, when the first signal and the second signal have changed from out-of-phase to in-phase.
摘要翻译：一种数据接收装置，其可以在EOP周期和前一时段期间获得可靠的接收数据，并且使得可以以可靠的方式接收串行数据。数据接收装置100设置有接收比较器102，其具有用于差分输入的第一信号线101a和第二信号线101b; NOR电路105，其在第一信号和第二信号从异相变为同相时输出作为触发信号的逻辑输出; 和D-FF电路107，其通过来自或非电路105的触发信号检索并保持接收比较器102的输出RCV; 其中当第一信号线101a的第一信号和第二信号线101b的第二信号彼此不同相时，选择电路108选择接收比较器102的输出，并将其作为接收数据输出当第一信号和第二信号从异相变为同相时，保持在D-FF电路中的值。

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