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1. 发明授权

US6167493A Semiconductor apparatus and read access method 失效
标题翻译：半导体装置及读取方式
公开(公告)号：US6167493A
公开(公告)日：2000-12-26
申请号：US863025
申请日：1997-05-23
申请人： Hidetaka Ebeshu , Hirotoshi Okada , Hideaki Tomatsuri
发明人： Hidetaka Ebeshu , Hirotoshi Okada , Hideaki Tomatsuri
IPC分类号： G06F12/06 , G06F13/16 , G06F13/18 , G06F15/78
CPC分类号： G06F13/18 , Y02D10/14
摘要： A CPU performs read access to a plurality of resources. A plurality of buffers connect the plurality of resources to the CPU, respectively. The CPU causes one of the plurality of buffers connected to one of the plurality of resources to be in an active state so that the CPU can perform read access to the one of the plurality of resources via the one of the plurality of buffers, the one of the plurality of resources being given priority.
摘要翻译： CPU执行对多个资源的读取访问。多个缓冲器分别将多个资源连接到CPU。 CPU使得与多个资源之一连接的多个缓冲器中的一个处于活动状态，使得CPU可以经由多个缓冲器中的一个来执行对多个资源之一的读取访问，多个资源的优先权。

2. 发明授权

US06775741B2 Cache system with limited number of tag memory accesses 有权
标题翻译：具有有限数量的标签存储器访问的缓存系统
公开(公告)号：US06775741B2
公开(公告)日：2004-08-10
申请号：US09768348
申请日：2001-01-25
申请人： Hidetaka Ebeshu , Hideaki Tomatsuri
发明人： Hidetaka Ebeshu , Hideaki Tomatsuri
IPC分类号： G06F1200
CPC分类号： G06F12/0882 , G06F2212/1028 , Y02D10/13
摘要： The present invention is a cache system comprising a data memory for storing data in an external memory, and a tag memory for storing address information for data held in the data memory and a valid data bit indicating whether data controlled by the address information is valid; wherein the address information in the tag memory commonly controls a plurality of data items with consecutive addresses; wherein reading from tag memory is prohibited in a case where an address to be accessed corresponds to data controlled by address information in tag memory that matches a preceding address to be accessed; and wherein tag memory is read and a cache hit determination is performed in a case where the address to be accessed corresponds to data controlled by address information in tag memory that does not match the preceding address to be accessed.
摘要翻译：本发明是一种缓存系统，包括用于在外部存储器中存储数据的数据存储器和用于存储数据存储器中保存的数据的地址信息的标签存储器和指示由地址信息控制的数据是否有效的有效数据位; 其中，所述标签存储器中的地址信息共同地控制具有连续地址的多个数据项; 在要访问的地址对应于标签存储器中与要访问的先前地址匹配的地址信息控制的数据的情况下，禁止从标签存储器读取; 并且其中标签存储器被读取，并且在要访问的地址对应于标签存储器中与要访问的前一个地址不匹配的地址信息控制的数据的情况下执行高速缓存命中确定。

3. 发明授权

US08027352B2 Gateway apparatus and data managing method 有权
标题翻译：网关设备和数据管理方法
公开(公告)号：US08027352B2
公开(公告)日：2011-09-27
申请号：US11976546
申请日：2007-10-25
申请人： Kaoru Noumi , Susumu Nishihashi , Tomoyuki Katou , Yukio Ishikawa , Yasuyuki Umezaki , Hidetaka Ebeshu , Shigeo Koide , Yukio Fujisawa , Hiroaki Shimauchi
发明人： Kaoru Noumi , Susumu Nishihashi , Tomoyuki Katou , Yukio Ishikawa , Yasuyuki Umezaki , Hidetaka Ebeshu , Shigeo Koide , Yukio Fujisawa , Hiroaki Shimauchi
IPC分类号： H04L12/66
CPC分类号： H04L47/10 , H04L12/40026 , H04L12/4625 , H04L43/106 , H04L47/283 , H04L47/31 , H04L47/32 , H04L49/206 , H04L49/30 , H04L49/351 , H04L2012/40215 , H04L2012/40273
摘要： A gateway apparatus for performing transfer control of frame data between a plurality of different communication channels is provided with a time stamp unit for adding time stamp information to received frame data and a data discarding unit for determining processing delay of the frame data or abnormality of the apparatus by referring to the time stamp information and for deleting the time stamp information added to the frame data at the time of sending the frame data.
摘要翻译：用于在多个不同的通信信道之间执行帧数据的传送控制的网关装置设置有用于将时间戳信息添加到接收到的帧数据的时间戳单元和用于确定帧数据的处理延迟或异常的数据丢弃单元通过参考时间戳信息和删除在发送帧数据时添加到帧数据的时间戳信息的装置。

4. 发明授权

US08122316B2 Error detector and error detection method 有权
标题翻译：误差检测器和误差检测方法
公开(公告)号：US08122316B2
公开(公告)日：2012-02-21
申请号：US11976544
申请日：2007-10-25
申请人： Kaoru Noumi , Susumu Nishihashi , Tomoyuki Katou , Yukio Ishikawa , Yasuyuki Umezaki , Hidetaka Ebeshu , Shigeo Koide , Yukio Fujisawa , Hiroaki Shimauchi
发明人： Kaoru Noumi , Susumu Nishihashi , Tomoyuki Katou , Yukio Ishikawa , Yasuyuki Umezaki , Hidetaka Ebeshu , Shigeo Koide , Yukio Fujisawa , Hiroaki Shimauchi
IPC分类号： H03M13/00 , G06F11/00 , G06F11/30 , G08C25/00 , H04L1/00
CPC分类号： H04L1/0045 , G06F11/10 , H04L1/0063 , H04L1/243 , H04L1/244
摘要： An error detector has a parity bit generator which generates error detection data for data strings sent from a CPU I/F to a memory, a parity checker which detects an error in the data strings output from the memory based on the error detection data, and a selector circuit which switchingly outputs the data from the parity bit generator and the data from a CPU which sends diagnostic data. While the selector circuit is switched to output the data from the CPU, based on the error detection data output from the selector circuit, the error detector conducts a failure diagnosis of error detection functions including at least one of the parity bit generator and the parity checker.
摘要翻译：错误检测器具有产生从CPU I / F向存储器发送的数据串的错误检测数据的奇偶校验位产生器，基于检错数据检测从存储器输出的数据串中的错误的奇偶检验器，以及选择器电路，其切换地输出来自奇偶位产生器的数据和来自发送诊断数据的CPU的数据。当选择器电路被切换以从CPU输出数据时，基于从选择器电路输出的错误检测数据，误差检测器进行包括奇偶位产生器和奇偶校验器中的至少一个的错误检测功能的故障诊断。

5. 发明申请

US20080101393A1 Gateway apparatus and data managing method 有权
标题翻译：网关设备和数据管理方法
公开(公告)号：US20080101393A1
公开(公告)日：2008-05-01
申请号：US11976546
申请日：2007-10-25
申请人： Kaoru Noumi , Susumu Nishihashi , Tomoyuki Katou , Yukio Ishikawa , Yasuyuki Umezaki , Hidetaka Ebeshu , Shigeo Koide , Yukio Fujisawa , Hiroaki Shimauchi
发明人： Kaoru Noumi , Susumu Nishihashi , Tomoyuki Katou , Yukio Ishikawa , Yasuyuki Umezaki , Hidetaka Ebeshu , Shigeo Koide , Yukio Fujisawa , Hiroaki Shimauchi
IPC分类号： H04L12/66
CPC分类号： H04L47/10 , H04L12/40026 , H04L12/4625 , H04L43/106 , H04L47/283 , H04L47/31 , H04L47/32 , H04L49/206 , H04L49/30 , H04L49/351 , H04L2012/40215 , H04L2012/40273
摘要： A gateway apparatus for performing transfer control of frame data between a plurality of different communication channels is provided with a time stamp unit for adding time stamp information to received frame data and a data discarding unit for determining processing delay of the frame data or abnormality of the apparatus by referring to the time stamp information and for deleting the time stamp information added to the frame data at the time of sending the frame data.
摘要翻译：用于在多个不同的通信信道之间执行帧数据的传送控制的网关装置设置有用于将时间戳信息添加到接收的帧数据的时间戳单元和用于确定帧数据的处理延迟或异常的数据丢弃单元通过参考时间戳信息和删除在发送帧数据时添加到帧数据的时间戳信息的装置。

6. 发明申请

US20080141074A1 Error detector and error detection method 有权
标题翻译：误差检测器和误差检测方法
公开(公告)号：US20080141074A1
公开(公告)日：2008-06-12
申请号：US11976544
申请日：2007-10-25
申请人： Kaoru Noumi , Susumu Nishihashi , Tomoyuki Katou , Yukio Ishikawa , Yasuyuki Umezaki , Hidetaka Ebeshu , Shigeo Koide , Yukio Fujisawa , Hiroaki Shimauchi
发明人： Kaoru Noumi , Susumu Nishihashi , Tomoyuki Katou , Yukio Ishikawa , Yasuyuki Umezaki , Hidetaka Ebeshu , Shigeo Koide , Yukio Fujisawa , Hiroaki Shimauchi
IPC分类号： G06F11/00
CPC分类号： H04L1/0045 , G06F11/10 , H04L1/0063 , H04L1/243 , H04L1/244
摘要： An error detector has a parity bit generator which generates error detection data for data strings sent from a CPU I/F to a memory, a parity checker which detects an error in the data strings output from the memory based on the error detection data, and a selector circuit which switchingly outputs the data from the parity bit generator and the data from a CPU which sends diagnostic data. While the selector circuit is switched to output the data from the CPU, based on the error detection data output from the selector circuit, the error detector conducts a failure diagnosis of error detection functions including at least one of the parity bit generator and the parity checker.
摘要翻译：错误检测器具有产生从CPU I / F向存储器发送的数据串的错误检测数据的奇偶校验位产生器，基于检错数据检测从存储器输出的数据串中的错误的奇偶检验器，以及选择器电路，其切换地输出来自奇偶位产生器的数据和来自发送诊断数据的CPU的数据。当选择器电路被切换以从CPU输出数据时，基于从选择器电路输出的错误检测数据，误差检测器进行包括奇偶位产生器和奇偶校验器中的至少一个的错误检测功能的故障诊断。

7. 发明授权

US08265087B2 Gateway apparatus and data transfer control method 有权
标题翻译：网关设备和数据传输控制方法
公开(公告)号：US08265087B2
公开(公告)日：2012-09-11
申请号：US11976687
申请日：2007-10-26
申请人： Kaoru Noumi , Susumu Nishihashi , Tomoyuki Katou , Yukio Ishikawa , Yasuyuki Umezaki , Hidetaka Ebeshu , Shigeo Koide , Yukio Fujisawa , Hiroaki Shimauchi
发明人： Kaoru Noumi , Susumu Nishihashi , Tomoyuki Katou , Yukio Ishikawa , Yasuyuki Umezaki , Hidetaka Ebeshu , Shigeo Koide , Yukio Fujisawa , Hiroaki Shimauchi
IPC分类号： H04L12/28
CPC分类号： H04L12/66 , H04L12/4135 , H04L12/4625 , H04L2012/40215 , H04L2012/40273
摘要： A gateway apparatus for performing transfer control of frame data between communication channels includes a routing map that stores ID information about the frame data and information about a communication channel that uses the ID information, and a search engine unit that routes the frame data to a transfer destination on the basis of the ID information of the frame data received and the routing map. The search engine unit does not transfer the frame data to the transfer destination when the ID information about the frame data received is ID information that is not used in the communication channel through which the frame data is received.
摘要翻译：用于在通信信道之间执行帧数据的传输控制的网关装置包括存储关于帧数据的ID信息和关于使用该ID信息的通信信道的信息的路由图，以及将帧数据路由到传送的搜索引擎单元基于接收的帧数据的ID信息和路由图。当接收到的帧数据的ID信息是在接收帧数据的通信信道中未使用的ID信息时，搜索引擎单元不将帧数据传送到传送目的地。

8. 发明申请

US20080101394A1 Gateway apparatus and data transfer control method 有权
标题翻译：网关设备和数据传输控制方法
公开(公告)号：US20080101394A1
公开(公告)日：2008-05-01
申请号：US11976687
申请日：2007-10-26
申请人： Kaoru Noumi , Susumu Nishihashi , Tomoyuki Katou , Yukio Ishikawa , Yasuyuki Umezaki , Hidetaka Ebeshu , Shigeo Koide , Yukio Fujisawa , Hiroaki Shimauchi
发明人： Kaoru Noumi , Susumu Nishihashi , Tomoyuki Katou , Yukio Ishikawa , Yasuyuki Umezaki , Hidetaka Ebeshu , Shigeo Koide , Yukio Fujisawa , Hiroaki Shimauchi
IPC分类号： H04L12/28
CPC分类号： H04L12/66 , H04L12/4135 , H04L12/4625 , H04L2012/40215 , H04L2012/40273
摘要： A gateway apparatus for performing transfer control of frame data between communication channels includes a routing map that stores ID information about the frame data and information about a communication channel that uses the ID information, and a search engine unit that routes the frame data to a transfer destination on the basis of the ID information of the frame data received and the routing map. The search engine unit does not transfer the frame data to the transfer destination when the ID information about the frame data received is ID information that is not used in the communication channel through which the frame data is received.
摘要翻译：用于在通信信道之间执行帧数据的传输控制的网关装置包括存储关于帧数据的ID信息和关于使用该ID信息的通信信道的信息的路由图，以及将帧数据路由到传送的搜索引擎单元基于接收的帧数据的ID信息和路由图。当接收到的帧数据的ID信息是在接收帧数据的通信信道中未使用的ID信息时，搜索引擎单元不将帧数据传送到传送目的地。

9. 发明申请

US20060069817A1 Data transferring device 失效
标题翻译：数据传输设备
公开(公告)号：US20060069817A1
公开(公告)日：2006-03-30
申请号：US11047744
申请日：2005-02-02
申请人： Hidetaka Ebeshu
发明人： Hidetaka Ebeshu
IPC分类号： G06F3/00
CPC分类号： G06F13/4022
摘要： A data transferring device comprises means for storing data to be transferred and means for, upon reception of data via one communication device such as a first communication device, connecting the communication device with the storing means, and for, after the completion of data reception, switching connections of the storing means to a communication device such as a second communication device for transmitting the stored data.
摘要翻译：数据传送装置包括用于存储要传送的数据的装置，以及用于在经由诸如第一通信装置的一个通信装置接收数据时连接通信装置与存储装置的装置，并且在数据接收完成之后，将存储装置的连接切换到诸如用于发送所存储的数据的第二通信装置的通信装置。

10. 发明授权

US07707333B2 Data transferring device for transferring data sent from one communication device to another communication device 失效
标题翻译：用于将从一个通信设备发送的数据传送到另一个通信设备的数据传送设备
公开(公告)号：US07707333B2
公开(公告)日：2010-04-27
申请号：US11047744
申请日：2005-02-02
申请人： Hidetaka Ebeshu
发明人： Hidetaka Ebeshu
IPC分类号： G06F3/00 , G06F5/00
CPC分类号： G06F13/4022
摘要： Upon reception of data via a first communication device, a unit connects the first communication device with a storage unit to store the data to be transferred and, after completion of data reception, the unit switches connections of the storage unit to a second communication device and transmits the stored data to the second communication device.
摘要翻译：在通过第一通信设备接收数据时，单元将第一通信设备与存储单元连接以存储要传送的数据，并且在完成数据接收之后，单元将存储单元的连接切换到第二通信设备，以及将存储的数据发送到第二通信设备。

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