专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20140191248A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20140191248A1
公开(公告)日：2014-07-10
申请号：US14147048
申请日：2014-01-03
申请人： Hidefumi Takaya , Masaru Nagao , Narumasa Soejima
发明人： Hidefumi Takaya , Masaru Nagao , Narumasa Soejima
IPC分类号： H01L23/62 , H01L29/78
CPC分类号： H01L29/7827 , H01L27/0251 , H01L29/4236 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes: a semiconductor substrate that has an element region and a peripheral region that surrounds the element region; and a gate pad that is disposed in an area that is on a surface side of the semiconductor substrate. The element region is formed with an insulated gate semiconductor element that has a gate electrode. The peripheral region is formed with a first withstand voltage retaining structure that surrounds the element region and a second withstand voltage retaining structure that is located in a position on the first withstand voltage retaining structure side from an outer edge of the element region and on the element region side from a boundary of the first withstand voltage retaining structure on the element region side. The gate pad is electrically connected to the gate electrode and is disposed in an area in which the second withstand voltage retaining structure is formed.
摘要翻译：半导体器件包括：半导体衬底，其具有围绕元件区域的元件区域和周边区域; 以及设置在所述半导体基板的表面侧的区域中的栅极焊盘。元件区域由具有栅电极的绝缘栅半导体元件形成。周边区域形成有围绕元件区域的第一耐压保持结构和位于第一耐压保持结构侧的位于元件区域的外边缘上的位置的第二耐压保持结构，并且元件区域侧从元件区域侧的第一耐压保持结构的边界。栅极焊盘与栅电极电连接，并且设置在形成第二耐压保持结构的区域中。

2. 发明授权

US09257501B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09257501B2
公开(公告)日：2016-02-09
申请号：US14138270
申请日：2013-12-23
申请人： Hidefumi Takaya , Masaru Nagao , Narumasa Soejima
发明人： Hidefumi Takaya , Masaru Nagao , Narumasa Soejima
IPC分类号： H01L29/06 , H01L29/78 , H01L29/16 , H01L29/423 , H01L29/739
CPC分类号： H01L29/0623 , H01L29/0649 , H01L29/0661 , H01L29/1608 , H01L29/42368 , H01L29/42372 , H01L29/4238 , H01L29/7397 , H01L29/7811 , H01L29/7813 , H01L29/8611
摘要： A semiconductor substrate of a semiconductor device includes a first conductive body region that is formed in the element region; a second conductive drift region that is formed in the element region; a gate electrode that is formed in the element region, that is arranged in a gate trench, and that faces the body region; an insulating body that is formed in the element region and is arranged between the gate electrode and an inside wall of the gate trench; a first conductive floating region that is formed in the element region and that is surrounded by the drift region; a first voltage-resistance retaining structure that is formed in the peripheral region and that surrounds the element region; and a gate pad that is formed in the peripheral region, and is electrically connected to the gate electrode in a position on the element region-side of the first voltage-resistance retaining structure.
摘要翻译：半导体器件的半导体衬底包括形成在元件区域中的第一导电体区域; 形成在所述元件区域中的第二导电漂移区; 栅电极，其形成在元件区域中，其布置在栅沟槽中并且面向所述主体区域; 绝缘体，其形成在所述元件区域中并且布置在所述栅电极和所述栅沟槽的内壁之间; 第一导电浮动区域，其形成在所述元件区域中并且被所述漂移区域包围; 第一耐电压保持结构，其形成在所述周边区域中并且围绕所述元件区域; 以及形成在周边区域中的栅极焊盘，并且在第一耐压保持结构的元件区域侧的位置与电极电连接。

3. 发明申请

US20140183620A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20140183620A1
公开(公告)日：2014-07-03
申请号：US14138270
申请日：2013-12-23
申请人： Hidefumi Takaya , Masaru Nagao , Narumasa Soejima
发明人： Hidefumi Takaya , Masaru Nagao , Narumasa Soejima
IPC分类号： H01L29/78 , H01L29/16
CPC分类号： H01L29/0623 , H01L29/0649 , H01L29/0661 , H01L29/1608 , H01L29/42368 , H01L29/42372 , H01L29/4238 , H01L29/7397 , H01L29/7811 , H01L29/7813 , H01L29/8611
摘要： A semiconductor substrate of a semiconductor device includes a first conductive body region that is formed in the element region; a second conductive drift region that is formed in the element region; a gate electrode that is formed in the element region, that is arranged in a gate trench, and that faces the body region; an insulating body that is formed in the element region and is arranged between the gate electrode and an inside wall of the gate trench; a first conductive floating region that is formed in the element region and that is surrounded by the drift region; a first voltage-resistance retaining structure that is formed in the peripheral region and that surrounds the element region; and a gate pad that is formed in the peripheral region, and is electrically connected to the gate electrode in a position on the element region-side of the first voltage-resistance retaining structure.
摘要翻译：半导体器件的半导体衬底包括形成在元件区域中的第一导电体区域; 形成在所述元件区域中的第二导电漂移区; 栅电极，其形成在元件区域中，其布置在栅沟槽中并且面向所述主体区域; 绝缘体，其形成在所述元件区域中并且布置在所述栅电极和所述栅沟槽的内壁之间; 第一导电浮动区域，其形成在所述元件区域中并且被所述漂移区域包围; 第一耐电压保持结构，其形成在所述周边区域中并且围绕所述元件区域; 以及形成在周边区域中的栅极焊盘，并且在第一耐压保持结构的元件区域侧的位置与电极电连接。

4. 发明授权

US09136372B2 Silicon carbide semiconductor device 有权
标题翻译：碳化硅半导体器件
公开(公告)号：US09136372B2
公开(公告)日：2015-09-15
申请号：US13531793
申请日：2012-06-25
申请人： Shinichiro Miyahara , Masahiro Sugimoto , Hidefumi Takaya , Yukihiko Watanabe , Narumasa Soejima , Tsuyoshi Ishikawa
发明人： Shinichiro Miyahara , Masahiro Sugimoto , Hidefumi Takaya , Yukihiko Watanabe , Narumasa Soejima , Tsuyoshi Ishikawa
IPC分类号： H01L29/66 , H01L29/78 , H01L29/423 , H01L29/04 , H01L29/08 , H01L29/10 , H01L29/16
CPC分类号： H01L29/7813 , H01L29/045 , H01L29/0865 , H01L29/1095 , H01L29/1608 , H01L29/4236 , H01L29/66068 , H01L29/7825 , H01L29/7827
摘要： In a silicon carbide semiconductor device, a plurality of trenches has a longitudinal direction in one direction and is arranged in a stripe pattern. Each of the trenches has first and second sidewalls extending in the longitudinal direction. The first sidewall is at a first acute angle to one of a (11-20) plane and a (1-100) plane, the second sidewall is at a second acute angle to the one of the (11-20) plane and the (1-100) plane, and the first acute angle is smaller than the second acute angle. A first conductivity type region is in contact with only the first sidewall in the first and second sidewalls of each of the trenches, and a current path is formed on only the first sidewall in the first and second sidewalls.
摘要翻译：在碳化硅半导体器件中，多个沟槽在一个方向上具有纵向方向并且被布置成条纹图案。每个沟槽具有在纵向方向上延伸的第一和第二侧壁。第一侧壁与（11-20）面和（1-100）面中的一个成锐角，第二侧壁与（11-20）面和（1-100）平面，第一锐角小于第二锐角。第一导电类型区域仅与每个沟槽的第一和第二侧壁中的第一侧壁接触，并且仅在第一和第二侧壁中的第一侧壁上形成电流路径。

5. 发明申请

US20140252465A1 SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20140252465A1
公开(公告)日：2014-09-11
申请号：US14352142
申请日：2012-10-17
申请人： Hidefumi Takaya , Hideo Matsuki , Naohiro Suzuki , Tsuyoshi Ishikawa , Narumasa Soejima , Yukihiko Watanabe
发明人： Hidefumi Takaya , Hideo Matsuki , Naohiro Suzuki , Tsuyoshi Ishikawa , Narumasa Soejima , Yukihiko Watanabe
IPC分类号： H01L29/423 , H01L29/66 , H01L21/28 , H01L29/78
CPC分类号： H01L29/4236 , H01L21/047 , H01L21/28008 , H01L21/823487 , H01L29/0619 , H01L29/0623 , H01L29/1608 , H01L29/41741 , H01L29/42368 , H01L29/66068 , H01L29/66666 , H01L29/7806 , H01L29/7813 , H01L29/7827
摘要： A semiconductor device has a semiconductor substrate including a body region, a drift region, a trench that extends from a surface of the semiconductor substrate into the drift region through the body region, and a source region located adjacent to the trench in a range exposed to the surface of the semiconductor substrate, the source region being isolated from the drift region by the body region. A specific layer is disposed on a bottom of the trench, and it has a characteristic of forming a depletion layer at a junction between the specific layer and the drift region. An insulating layer covers an upper surface of the specific layer and a sidewall of the trench. A conductive portion is formed on a part of the side wall of the trench. The conductive portion is joined to the specific layer, and reaches the surface of the semiconductor substrate.
摘要翻译：半导体器件具有半导体衬底，其包括体区，漂移区，从半导体衬底的表面延伸通过体区的漂移区的沟槽，以及与暴露于半导体衬底的表面，源区域通过身体区域与漂移区隔离。特定层设置在沟槽的底部，并且具有在特定层和漂移区之间的结处形成耗尽层的特征。绝缘层覆盖特定层的上表面和沟槽的侧壁。导电部分形成在沟槽的侧壁的一部分上。导电部分连接到特定层，并到达半导体衬底的表面。

6. 发明申请

US20140175459A1 SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：硅碳化硅半导体器件及其制造方法
公开(公告)号：US20140175459A1
公开(公告)日：2014-06-26
申请号：US13994855
申请日：2012-02-06
申请人： Kensaku Yamamoto , Masato Noborio , Hideo Matsuki , Hidefumi Takaya , Masahiro Sugimoto , Narumasa Soejima , Tsuyoshi Ishikawa , Yukihiko Watanabe
发明人： Kensaku Yamamoto , Masato Noborio , Hideo Matsuki , Hidefumi Takaya , Masahiro Sugimoto , Narumasa Soejima , Tsuyoshi Ishikawa , Yukihiko Watanabe
IPC分类号： H01L29/78 , H01L29/16 , H01L29/66
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/66068 , H01L29/66348 , H01L29/7397
摘要： A SiC semiconductor device includes: a semiconductor switching element having: a substrate, a drift layer and a base region stacked in this order; a source region and a contact region in the base region; a trench extending from a surface of the source region to penetrate the base region; a gate electrode on a gate insulating film in the trench; a source electrode electrically coupled with the source region and the base region; a drain electrode on a back side of the substrate; and multiple deep layers in an upper portion of the drift layer deeper than the trench. Each deep layer has upper and lower portions. A width of the upper portion is smaller than the lower portion.
摘要翻译： SiC半导体器件包括：半导体开关元件，其具有：依次层叠的基板，漂移层和基极区域; 源极区域和基极区域中的接触区域; 从源极区域的表面延伸以穿透基部区域的沟槽; 沟槽中的栅极绝缘膜上的栅电极; 源极，与源极区域和基极区域电耦合; 位于所述基板的背面的漏电极; 以及在漂移层的上部比沟槽更深的多个深层。每个深层具有上部和下部。上部的宽度小于下部。

7. 发明授权

US08878290B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08878290B2
公开(公告)日：2014-11-04
申请号：US14046361
申请日：2013-10-04
申请人： Hidefumi Takaya , Narumasa Soejima
发明人： Hidefumi Takaya , Narumasa Soejima
IPC分类号： H01L29/78
CPC分类号： H01L29/7831 , H01L29/0623 , H01L29/4236 , H01L29/42364 , H01L29/42368 , H01L29/66734 , H01L29/7813
摘要： A semiconductor substrate of a semiconductor device includes a body region of a first conductivity type, a drift region of a second conductivity type coming into contact with a lower surface of the body region, a gate electrode that is provided in a gate trench passing through the body region and extending to the drift region and faces the body region, and a gate insulator that is provided between the gate electrode and a wall surface of the gate trench. An inverted U-shaped section is formed in a lower surface of the gate insulator, and a floating region of the first conductivity type is formed in the inverted U-shaped section. The floating region protrudes under a portion that is located at a lowermost portion in the lower surface of the gate insulator.
摘要翻译：半导体器件的半导体衬底包括第一导电类型的主体区域，与主体区域的下表面接触的第二导电类型的漂移区域，设置在通过所述主体区域的栅极沟槽中的栅电极并且延伸到漂移区并面向身体区域，以及设置在栅极电极和栅极沟槽的壁表面之间的栅极绝缘体。在栅极绝缘体的下表面形成倒U字状的截面，在倒U字状的截面形成有第一导电型的浮动区域。浮动区域在位于栅极绝缘体的下表面中的最下部的部分下方突出。

8. 发明授权

US08710586B2 SIC semiconductor device and method for manufacturing the same 有权
标题翻译： SIC半导体器件及其制造方法
公开(公告)号：US08710586B2
公开(公告)日：2014-04-29
申请号：US13229892
申请日：2011-09-12
申请人： Toshimasa Yamamoto , Masahiro Sugimoto , Hidefumi Takaya , Jun Morimoto , Narumasa Soejima , Tsuyoshi Ishikawa , Yukihiko Watanabe
发明人： Toshimasa Yamamoto , Masahiro Sugimoto , Hidefumi Takaya , Jun Morimoto , Narumasa Soejima , Tsuyoshi Ishikawa , Yukihiko Watanabe
IPC分类号： H01L29/66 , H01L29/15
CPC分类号： H01L29/7813 , H01L29/086 , H01L29/1608 , H01L29/41766 , H01L29/45 , H01L29/66068
摘要： A SiC semiconductor device includes: a substrate, a drift layer, and a base region stacked in this order; first and second source regions and a contact layer in the base region; a trench penetrating the source and base regions; a gate electrode in the trench; an interlayer insulation film with a contact hole covering the gate electrode; a source electrode coupling with the source region and the contact layer via the contact hole; a drain electrode on the substrate; and a metal silicide film. The high concentration second source region is shallower than the low concentration first source region, and has a part covered with the interlayer insulation film, which includes a low concentration first portion near a surface and a high concentration second portion deeper than the first portion. The metal silicide film on the second part has a thickness larger than the first portion.
摘要翻译： SiC半导体器件包括：依次堆叠的衬底，漂移层和基极区域; 第一和第二源极区域和基极区域中的接触层; 穿透源区和基区的沟槽; 沟槽中的栅电极; 具有覆盖所述栅电极的接触孔的层间绝缘膜; 源极通过接触孔与源极区域和接触层耦合; 衬底上的漏电极; 和金属硅化物膜。高浓度第二源区比低浓度第一源区浅，并且具有被层间绝缘膜覆盖的部分，其包括表面附近的低浓度第一部分和比第一部分更深的高浓度第二部分。第二部分上的金属硅化物膜的厚度大于第一部分。

9. 发明授权

US08518809B2 Manufacturing method of silicon carbide single crystal 有权
标题翻译：碳化硅单晶的制造方法
公开(公告)号：US08518809B2
公开(公告)日：2013-08-27
申请号：US13308721
申请日：2011-12-01
申请人： Hiroki Watanabe , Yasuo Kitou , Yasushi Furukawa , Kensaku Yamamoto , Hidefumi Takaya , Masahiro Sugimoto , Yukihiko Watanabe , Narumasa Soejima , Tsuyoshi Ishikawa
发明人： Hiroki Watanabe , Yasuo Kitou , Yasushi Furukawa , Kensaku Yamamoto , Hidefumi Takaya , Masahiro Sugimoto , Yukihiko Watanabe , Narumasa Soejima , Tsuyoshi Ishikawa
IPC分类号： H01L21/20
CPC分类号： H01L21/0262 , C30B25/186 , C30B29/36 , H01L21/02378 , H01L21/0243 , H01L21/02529 , H01L21/02658 , H01L21/046 , H01L21/0475 , H01L29/04
摘要： A manufacturing method of an SiC single crystal includes preparing an SiC substrate, implanting ions into a surface portion of the SiC substrate to form an ion implantation layer, activating the ions implanted into the surface portion of the SiC substrate by annealing, chemically etching the surface portion of the SiC substrate to form an etch pit that is caused by a threading screw dislocation included in the SiC substrate and performing an epitaxial growth of SiC to form an SiC growth layer on a surface of the SiC substrate including an inner wall of the etch pit in such a manner that portions of the SiC growth layer grown on the inner wall of the etch pit join with each other.
摘要翻译： SiC单晶的制造方法包括制备SiC衬底，将离子注入到SiC衬底的表面部分中以形成离子注入层，通过退火激活注入到SiC衬底的表面部分中的离子，化学蚀刻表面以形成由SiC衬底中的螺纹位错引起的蚀刻坑，并且在SiC衬底的表面上进行SiC的外延生长以形成SiC生长层，所述SiC生长层包括蚀刻的内壁以使得在蚀刻坑的内壁上生长的SiC生长层的部分彼此连接的方式形成凹坑。

10. 发明申请

US20130001592A1 SILICON CARBIDE SEMICONDUCTOR DEVICE 有权
标题翻译：硅碳化硅半导体器件
公开(公告)号：US20130001592A1
公开(公告)日：2013-01-03
申请号：US13531793
申请日：2012-06-25
申请人： Shinichiro Miyahara , Masahiro Sugimoto , Hidefumi Takaya , Yukihiko Watanabe , Narumasa Soejima , Tsuyoshi Ishikawa
发明人： Shinichiro Miyahara , Masahiro Sugimoto , Hidefumi Takaya , Yukihiko Watanabe , Narumasa Soejima , Tsuyoshi Ishikawa
IPC分类号： H01L29/161
CPC分类号： H01L29/7813 , H01L29/045 , H01L29/0865 , H01L29/1095 , H01L29/1608 , H01L29/4236 , H01L29/66068 , H01L29/7825 , H01L29/7827
摘要： In a silicon carbide semiconductor device, a plurality of trenches has a longitudinal direction in one direction and is arranged in a stripe pattern. Each of the trenches has first and second sidewalls extending in the longitudinal direction. The first sidewall is at a first acute angle to one of a (11-20) plane and a (1-100) plane, the second sidewall is at a second acute angle to the one of the (11-20) plane and the (1-100) plane, and the first acute angle is smaller than the second acute angle. A first conductivity type region is in contact with only the first sidewall in the first and second sidewalls of each of the trenches, and a current path is formed on only the first sidewall in the first and second sidewalls.
摘要翻译：在碳化硅半导体器件中，多个沟槽在一个方向上具有纵向方向并且被布置成条纹图案。每个沟槽具有在纵向方向上延伸的第一和第二侧壁。第一侧壁与（11-20）面和（1-100）面中的一个成锐角，第二侧壁与（11-20）面和（1-100）平面，第一锐角小于第二锐角。第一导电类型区域仅与每个沟槽的第一和第二侧壁中的第一侧壁接触，并且仅在第一和第二侧壁中的第一侧壁上形成电流通路。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式