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1. 发明授权

US09543428B2 Silicon carbide semiconductor device and method for producing the same 有权
标题翻译：碳化硅半导体器件及其制造方法
公开(公告)号：US09543428B2
公开(公告)日：2017-01-10
申请号：US14400365
申请日：2013-06-06
申请人： DENSO CORPORATION , TOYOTA JIDOSHA KABUSHIKI KAISHA , Masahiro Sugimoto , Hidefumi Takaya , Akitaka Soeno , Jun Morimoto
发明人： Yuichi Takeuchi , Naohiro Suzuki , Masahiro Sugimoto , Hidefumi Takaya , Akitaka Soeno , Jun Morimoto , Narumasa Soejima , Yukihiko Watanabe
IPC分类号： H01L29/78 , H01L29/16 , H01L21/82 , H01L29/66 , H01L29/10 , H01L29/872 , H01L21/04 , H01L21/306 , H01L21/308 , H01L29/423 , H01L29/417 , H01L29/06 , H01L29/08 , H01L29/861
CPC分类号： H01L29/7811 , H01L21/046 , H01L21/0475 , H01L21/30604 , H01L21/308 , H01L21/761 , H01L21/8213 , H01L29/0615 , H01L29/063 , H01L29/0634 , H01L29/0661 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/157 , H01L29/158 , H01L29/1608 , H01L29/41766 , H01L29/4236 , H01L29/66068 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7813 , H01L29/861 , H01L29/872
摘要： An SiC semiconductor device has a p type region including a low concentration region and a high concentration region filled in a trench formed in a cell region. A p type column is provided by the low concentration region, and a p+ type deep layer is provided by the high concentration region. Thus, since a SJ structure can be made by the p type column and the n type column provided by the n type drift layer, an on-state resistance can be reduced. As a drain potential can be blocked by the p+ type deep layer, at turnoff, an electric field applied to the gate insulation film can be alleviated and thus breakage of the gate insulation film can be restricted. Therefore, the SiC semiconductor device can realize the reduction of the on-state resistance and the restriction of breakage of the gate insulation film.
摘要翻译： SiC半导体器件具有包含低浓度区域和填充在形成于单元区域的沟槽中的高浓度区域的p型区域。由低浓度区域提供p型列，并且由高浓度区域提供p +型深层。因此，由于可以通过由n型漂移层提供的p型列和n型列来形成SJ结构，所以可以降低导通电阻。由于漏极电位可以被p +型深层阻挡，所以在关断时，施加到栅极绝缘膜的电场可以减轻，从而可以限制栅极绝缘膜的破裂。因此，SiC半导体器件可以实现导通电阻的降低和栅极绝缘膜的破损的限制。

2. 发明授权

US08525223B2 Silicon carbide semiconductor device 有权
标题翻译：碳化硅半导体器件
公开(公告)号：US08525223B2
公开(公告)日：2013-09-03
申请号：US13450639
申请日：2012-04-19
申请人： Hiroki Watanabe , Shinichiro Miyahara , Masahiro Sugimoto , Hidefumi Takaya , Yukihiko Watanabe , Narumasa Soejima , Tsuyoshi Ishikawa
发明人： Hiroki Watanabe , Shinichiro Miyahara , Masahiro Sugimoto , Hidefumi Takaya , Yukihiko Watanabe , Narumasa Soejima , Tsuyoshi Ishikawa
IPC分类号： H01L21/02
CPC分类号： H01L29/7813 , H01L29/045 , H01L29/0634 , H01L29/1095 , H01L29/1608 , H01L29/66068 , H01L29/7397
摘要： A SiC semiconductor device includes: a SiC substrate including a first or second conductive type layer and a first conductive type drift layer and including a principal surface having an offset direction; a trench disposed on the drift layer and having a longitudinal direction; and a gate electrode disposed in the trench via a gate insulation film. A sidewall of the trench provides a channel formation surface. The vertical semiconductor device flows current along with the channel formation surface of the trench according to a gate voltage applied to the gate electrode. The offset direction of the SiC substrate is perpendicular to the longitudinal direction of the trench.
摘要翻译： SiC半导体器件包括：SiC衬底，包括第一或第二导电类型层和第一导电类型漂移层，并且包括具有偏移方向的主表面; 设置在所述漂移层上并具有纵向方向的沟槽; 以及通过栅极绝缘膜设置在沟槽中的栅电极。沟槽的侧壁提供通道形成表面。垂直半导体器件根据施加到栅电极的栅极电压与沟道形成表面一起流动电流。 SiC衬底的偏移方向垂直于沟槽的纵向方向。

3. 发明授权

US08334541B2 SiC semiconductor device 有权
标题翻译： SiC半导体器件
公开(公告)号：US08334541B2
公开(公告)日：2012-12-18
申请号：US13177747
申请日：2011-07-07
申请人： Shinichiro Miyahara , Hidefumi Takaya , Masahiro Sugimoto , Jun Morimoto , Yukihiko Watanabe
发明人： Shinichiro Miyahara , Hidefumi Takaya , Masahiro Sugimoto , Jun Morimoto , Yukihiko Watanabe
IPC分类号： H01L27/088
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/66068 , H01L29/7397 , H01L29/7828
摘要： A SiC semiconductor device includes a reverse type MOSFET having: a substrate; a drift layer and a base region on the substrate; a base contact layer and a source region on the base region; multiple trenches having a longitudinal direction in a first direction penetrating the source region and the base region; a gate electrode in each trench via a gate insulation film; an interlayer insulation film covering the gate electrode and having a contact hole, through which the source region and the base contact layer are exposed; a source electrode coupling with the source region and the base region through the contact hole; a drain electrode on the substrate. The source region and the base contact layer extend along with a second direction perpendicular to the first direction, and are alternately arranged along with the first direction. The contact hole has a longitudinal direction in the first direction.
摘要翻译： SiC半导体器件包括：反向型MOSFET，具有：衬底; 衬底上的漂移层和基极区域; 基极接触层和基极区上的源极区; 多个沟槽具有沿着第一方向的纵向方向穿过源极区域和基极区域; 通过栅极绝缘膜在每个沟槽中的栅电极; 覆盖所述栅电极且具有接触孔的层间绝缘膜，所述源极区域和所述基极接触层暴露在所述接触孔中; 源极通过接触孔与源极区域和基极区域耦合; 衬底上的漏电极。源区域和基底接触层与垂直于第一方向的第二方向一起延伸，并且与第一方向交替布置。接触孔沿第一方向具有纵向方向。

4. 发明申请

US20120187478A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120187478A1
公开(公告)日：2012-07-26
申请号：US13499599
申请日：2009-10-01
申请人： Hidefumi Takaya
发明人： Hidefumi Takaya
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0623 , H01L29/0626 , H01L29/0878 , H01L29/4236 , H01L29/42368 , H01L29/66734 , H01L29/7808
摘要： Provided is a semiconductor device capable of suppressing deterioration in characteristics even when an Avalanche phenomenon occurs in the semiconductor device. The semiconductor device includes a first conductive type drift region; a second conductive type body region disposed on a front surface side of the drift region; a gate trench penetrating the body region and extending to the drift region; a gate electrode disposed within the gate trench; an insulator disposed between the gate electrode and a wall surface of the gate trench; and a second conductive type diffusion region surrounding a bottom portion of the gate trench. An impurity concentration and dimension of the diffusion region are adjusted such that a breakdown is to occur at a p-n junction between the diffusion region and the drift region when an Avalanche phenomenon is occurring.
摘要翻译：即使在半导体装置中发生雪崩现象的情况下，也能够抑制特性劣化的半导体装置。半导体器件包括第一导电型漂移区; 设置在所述漂移区域的前表面侧的第二导电型体区域; 穿过身体区域并延伸到漂移区域的栅极沟槽; 设置在所述栅极沟槽内的栅电极; 设置在所述栅极电极和所述栅极沟槽的壁表面之间的绝缘体; 以及围绕所述栅极沟槽的底部的第二导电型扩散区域。调整扩散区域的杂质浓度和尺寸，使得当发生雪崩现象时，在扩散区域和漂移区域之间的p-n结处发生击穿。

5. 发明申请

US20110203513A1 METHOD OF MANUFACTURING SILICON CARBIDE SUBSTRATE 审中-公开
标题翻译：制造碳化硅基板的方法
公开(公告)号：US20110203513A1
公开(公告)日：2011-08-25
申请号：US13029791
申请日：2011-02-17
申请人： Hiroki WATANABE , Yasuo Kitou , Kensaku Yamamoto , Hidefumi Takaya , Masahiro Sugimoto , Jun Morimoto , Yukihiko Watanabe , Narumasa Soejima , Tsuyoshi Ishikawa
发明人： Hiroki WATANABE , Yasuo Kitou , Kensaku Yamamoto , Hidefumi Takaya , Masahiro Sugimoto , Jun Morimoto , Yukihiko Watanabe , Narumasa Soejima , Tsuyoshi Ishikawa
IPC分类号： C30B19/12
CPC分类号： H01L21/02529 , C30B29/36 , C30B33/02 , H01L21/02378 , H01L21/02658 , H01L21/02667 , H01L29/66068
摘要： In a method of manufacturing a silicon carbide substrate, a defect-containing substrate made of silicon carbide is prepared. The defect-containing substrate has a front surface, a rear surface being opposite to the front surface, and a surface portion adjacent to the front surface. The detect-containing substrate includes a screw dislocation in the surface portion. The front surface of the defect-containing substrate is applied with an external force so that a crystallinity of the surface portion is reduced. After being applied with the external force, the defect-containing substrate is thermally treated so that the crystallinity of the surface portion is recovered.
摘要翻译：在制造碳化硅衬底的方法中，制备由碳化硅制成的含缺陷衬底。含缺陷的基板具有前表面，与前表面相对的后表面和与前表面相邻的表面部分。含检测基板包括在表面部分中的螺旋位错。使含有缺陷的基板的前表面被施加外力，使得表面部分的结晶度降低。在施加外力之后，对含缺陷的基板进行热处理，以恢复表面部分的结晶度。

6. 发明授权

US09276075B2 Semiconductor device having vertical MOSFET structure that utilizes a trench-type gate electrode and method of producing the same 有权
标题翻译：具有利用沟槽型栅电极的垂直MOSFET结构的半导体器件及其制造方法
公开(公告)号：US09276075B2
公开(公告)日：2016-03-01
申请号：US14352142
申请日：2012-10-17
申请人： Hidefumi Takaya , Hideo Matsuki , Naohiro Suzuki , Tsuyoshi Ishikawa , Narumasa Soejima , Yukihiko Watanabe
发明人： Hidefumi Takaya , Hideo Matsuki , Naohiro Suzuki , Tsuyoshi Ishikawa , Narumasa Soejima , Yukihiko Watanabe
IPC分类号： H01L29/78 , H01L21/8234 , H01L29/423 , H01L29/417 , H01L29/66 , H01L29/06 , H01L21/28 , H01L21/04 , H01L29/16
CPC分类号： H01L29/4236 , H01L21/047 , H01L21/28008 , H01L21/823487 , H01L29/0619 , H01L29/0623 , H01L29/1608 , H01L29/41741 , H01L29/42368 , H01L29/66068 , H01L29/66666 , H01L29/7806 , H01L29/7813 , H01L29/7827
摘要： A semiconductor device has a semiconductor substrate including a body region, a drift region, a trench that extends from a surface of the semiconductor substrate into the drift region through the body region, and a source region located adjacent to the trench in a range exposed to the surface of the semiconductor substrate, the source region being isolated from the drift region by the body region. A specific layer is disposed on a bottom of the trench, and it has a characteristic of forming a depletion layer at a junction between the specific layer and the drift region. An insulating layer covers an upper surface of the specific layer and a sidewall of the trench. A conductive portion is formed on a part of the side wall of the trench. The conductive portion is joined to the specific layer, and reaches the surface of the semiconductor substrate.
摘要翻译：半导体器件具有半导体衬底，其包括体区，漂移区，从半导体衬底的表面延伸通过体区的漂移区的沟槽，以及与暴露于半导体衬底的表面，源区域通过身体区域与漂移区隔离。特定层设置在沟槽的底部，并且具有在特定层和漂移区之间的结处形成耗尽层的特征。绝缘层覆盖特定层的上表面和沟槽的侧壁。导电部分形成在沟槽的侧壁的一部分上。导电部分连接到特定层，并到达半导体衬底的表面。

7. 发明授权

US09257501B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09257501B2
公开(公告)日：2016-02-09
申请号：US14138270
申请日：2013-12-23
申请人： Hidefumi Takaya , Masaru Nagao , Narumasa Soejima
发明人： Hidefumi Takaya , Masaru Nagao , Narumasa Soejima
IPC分类号： H01L29/06 , H01L29/78 , H01L29/16 , H01L29/423 , H01L29/739
CPC分类号： H01L29/0623 , H01L29/0649 , H01L29/0661 , H01L29/1608 , H01L29/42368 , H01L29/42372 , H01L29/4238 , H01L29/7397 , H01L29/7811 , H01L29/7813 , H01L29/8611
摘要： A semiconductor substrate of a semiconductor device includes a first conductive body region that is formed in the element region; a second conductive drift region that is formed in the element region; a gate electrode that is formed in the element region, that is arranged in a gate trench, and that faces the body region; an insulating body that is formed in the element region and is arranged between the gate electrode and an inside wall of the gate trench; a first conductive floating region that is formed in the element region and that is surrounded by the drift region; a first voltage-resistance retaining structure that is formed in the peripheral region and that surrounds the element region; and a gate pad that is formed in the peripheral region, and is electrically connected to the gate electrode in a position on the element region-side of the first voltage-resistance retaining structure.
摘要翻译：半导体器件的半导体衬底包括形成在元件区域中的第一导电体区域; 形成在所述元件区域中的第二导电漂移区; 栅电极，其形成在元件区域中，其布置在栅沟槽中并且面向所述主体区域; 绝缘体，其形成在所述元件区域中并且布置在所述栅电极和所述栅沟槽的内壁之间; 第一导电浮动区域，其形成在所述元件区域中并且被所述漂移区域包围; 第一耐电压保持结构，其形成在所述周边区域中并且围绕所述元件区域; 以及形成在周边区域中的栅极焊盘，并且在第一耐压保持结构的元件区域侧的位置与电极电连接。

8. 发明授权

US08975139B2 Manufacturing method of silicon carbide semiconductor device 有权
标题翻译：碳化硅半导体器件的制造方法
公开(公告)号：US08975139B2
公开(公告)日：2015-03-10
申请号：US14000901
申请日：2012-09-04
申请人： Shinichiro Miyahara , Toshimasa Yamamoto , Hidefumi Takaya , Masahiro Sugimoto , Yukihiko Watanabe , Narumasa Soejima , Tsuyoshi Ishikawa
发明人： Shinichiro Miyahara , Toshimasa Yamamoto , Hidefumi Takaya , Masahiro Sugimoto , Yukihiko Watanabe , Narumasa Soejima , Tsuyoshi Ishikawa
IPC分类号： H01L21/336 , H01L29/66 , H01L29/78 , H01L21/3065 , H01L29/34 , H01L29/423 , H01L29/16
CPC分类号： H01L29/66666 , H01L21/3065 , H01L29/1608 , H01L29/34 , H01L29/4236 , H01L29/66068 , H01L29/7813
摘要： A manufacturing method of a silicon carbide semiconductor device includes: forming a drift layer on a silicon carbide substrate; forming a base layer on or in a surface portion of the drift layer; forming a source region in a surface portion of the base layer; forming a trench to penetrate the base layer and to reach the drift layer; forming a gate electrode on a gate insulation film in the trench; forming a source electrode electrically connected to the source region and the base layer; and forming a drain electrode on a back surface of the substrate. The forming of the trench includes: flattening a substrate surface; and etching to form the trench after flattening.
摘要翻译：碳化硅半导体器件的制造方法包括：在碳化硅衬底上形成漂移层; 在漂移层的表面部分上或其中形成基底层; 在所述基底层的表面部分中形成源区; 形成沟槽以穿透基层并到达漂移层; 在沟槽中的栅极绝缘膜上形成栅电极; 形成与源极区域和基极层电连接的源电极; 以及在所述基板的背面上形成漏电极。沟槽的形成包括：使基底表面变平; 并进行蚀刻以在平坦化之后形成沟槽。

9. 发明授权

US08933483B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08933483B2
公开(公告)日：2015-01-13
申请号：US14074212
申请日：2013-11-07
申请人： Hidefumi Takaya , Kimimori Hamada , Yuji Nishibe
发明人： Hidefumi Takaya , Kimimori Hamada , Yuji Nishibe
IPC分类号： H01L29/78 , H01L29/08 , H01L29/10 , H01L29/06
CPC分类号： H01L29/7815 , H01L29/0653 , H01L29/0873 , H01L29/0878 , H01L29/0886 , H01L29/1095
摘要： Provided is a semiconductor device capable of reducing a temperature-dependent variation of a current sense ratio and accurately detecting current In the semiconductor device, at least one of an impurity concentration and a thickness of each semiconductor layer is adjusted such that a value calculated by a following equation is less than a predetermined value: [ ∑ i = 1 n ⁢ ( R Mi × k Mi ) - ∑ i = 1 n ⁢ ( R Si × k Si ) ] / ∑ i = 1 n ⁢ ( R Mi × k Mi ) where a temperature-dependent resistance changing rate of an i-th semiconductor layer (i=1 to n) of the main element domain is RMi; a resistance ratio of the i-th semiconductor layer of the main element domain relative to the entire main element domain is kMi; a temperature-dependent resistance changing rate of the i-th semiconductor layer of the sense element domain is RSi; and a resistance ratio of the i-th semiconductor layer of the sense element domain to the entire sense element domain is kSi.
摘要翻译：提供了能够降低电流感测比的温度变化并精确检测电流的半导体器件。在半导体器件中，调整每个半导体层的杂质浓度和厚度中的至少一个，使得通过a 以下等式小于预定值：[Σi = 1 n（R Mi×k Mi） - Σi = 1 n（R Si×k Si）] /Σi = 1 n（R Mi×k Mi）其中主要元素域的第i个半导体层（i = 1至n）的温度依赖性电阻变化率为RMi; 主元件区域的第i个半导体层相对于整个主要元件区域的电阻比为kMi; 感测元件畴的第i个半导体层的温度依赖性电阻变化率为RSi; 并且感测元件畴的第i个半导体层与整个感测元件畴的电阻比为kSi。

10. 发明申请

US20140183620A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20140183620A1
公开(公告)日：2014-07-03
申请号：US14138270
申请日：2013-12-23
申请人： Hidefumi Takaya , Masaru Nagao , Narumasa Soejima
发明人： Hidefumi Takaya , Masaru Nagao , Narumasa Soejima
IPC分类号： H01L29/78 , H01L29/16
CPC分类号： H01L29/0623 , H01L29/0649 , H01L29/0661 , H01L29/1608 , H01L29/42368 , H01L29/42372 , H01L29/4238 , H01L29/7397 , H01L29/7811 , H01L29/7813 , H01L29/8611
摘要： A semiconductor substrate of a semiconductor device includes a first conductive body region that is formed in the element region; a second conductive drift region that is formed in the element region; a gate electrode that is formed in the element region, that is arranged in a gate trench, and that faces the body region; an insulating body that is formed in the element region and is arranged between the gate electrode and an inside wall of the gate trench; a first conductive floating region that is formed in the element region and that is surrounded by the drift region; a first voltage-resistance retaining structure that is formed in the peripheral region and that surrounds the element region; and a gate pad that is formed in the peripheral region, and is electrically connected to the gate electrode in a position on the element region-side of the first voltage-resistance retaining structure.
摘要翻译：半导体器件的半导体衬底包括形成在元件区域中的第一导电体区域; 形成在所述元件区域中的第二导电漂移区; 栅电极，其形成在元件区域中，其布置在栅沟槽中并且面向所述主体区域; 绝缘体，其形成在所述元件区域中并且布置在所述栅电极和所述栅沟槽的内壁之间; 第一导电浮动区域，其形成在所述元件区域中并且被所述漂移区域包围; 第一耐电压保持结构，其形成在所述周边区域中并且围绕所述元件区域; 以及形成在周边区域中的栅极焊盘，并且在第一耐压保持结构的元件区域侧的位置与电极电连接。

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