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1. 发明授权

US07764564B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07764564B2
公开(公告)日：2010-07-27
申请号：US11987501
申请日：2007-11-30
申请人： Hideaki Saito , Hiroaki Ikeda
发明人： Hideaki Saito , Hiroaki Ikeda
IPC分类号： G11C8/00
CPC分类号： G06F13/1647 , G06F13/1684 , G11C7/10 , G11C7/1075 , G11C8/04
摘要： A semiconductor device, which allows a bank interleaving operation by issuing a write command and a read command to different banks while switching them without a waiting time to thereby prevent a drop in data transfer efficiency, is provided. The semiconductor device includes: a memory chip with banks each including at least one memory cell; a logic chip; and data buses, provided corresponding to the banks, for transmitting/receiving write data and read data between the banks and the logic chip. The logic chip includes: a writing data bus for transmitting write data to the memory chip via a data bus; a reading data bus for receiving read data from the memory chip via a data bus; and a switch for, corresponding to a write command or a read command to a bank, connecting the writing data bus or the reading data bus to a data bus connected to the bank.
摘要翻译：提供一种半导体器件，其通过在不间断的时间切换它们的同时向不同的库发出写入命令和读取命令来允许存储体交错操作，从而防止数据传送效率的下降。半导体器件包括：存储器芯片，每个存储器芯片包括至少一个存储单元; 一个逻辑芯片; 以及与银行对应的用于发送/接收写入数据和在存储体和逻辑芯片之间读取数据的数据总线。逻辑芯片包括：写入数据总线，用于经由数据总线将写入数据发送到存储器芯片; 读取数据总线，用于经由数据总线从存储器芯片接收读取数据; 以及用于对应于写入命令或对存储体的读取命令的开关，将写入数据总线或读取数据总线连接到连接到存储体的数据总线。

2. 发明授权

US07209376B2 Stacked semiconductor memory device 有权
标题翻译：堆叠半导体存储器件
公开(公告)号：US07209376B2
公开(公告)日：2007-04-24
申请号：US11151213
申请日：2005-06-14
申请人： Hideaki Saito , Yasuhiko Hagihara , Muneo Fukaishi , Masayuki Mizuno , Hiroaki Ikeda , Kayoko Shibata
发明人： Hideaki Saito , Yasuhiko Hagihara , Muneo Fukaishi , Masayuki Mizuno , Hiroaki Ikeda , Kayoko Shibata
IPC分类号： G11C5/06
CPC分类号： G11C5/04 , G11C5/063 , H01L25/0657 , H01L2224/16145 , H01L2225/06527 , H01L2225/06555 , H01L2924/01019 , H01L2924/10253 , H01L2924/00
摘要： A three-dimensional semiconductor memory device having the object of decreasing the interconnection capacitance that necessitates electrical charge and discharge during data transfer and thus decreasing power consumption is provided with: a plurality of memory cell array chips, in which sub-banks that are the divisions of bank memory are organized and arranged to correspond to input/output bits, are stacked on a first semiconductor chip; and interchip interconnections for connecting the memory cell arrays such that corresponding input/output bits of the sub-banks are the same, these interchip interconnections being provided in a number corresponding to the number of input/output bits and passing through the memory cell array chips in the direction of stacking.
摘要翻译：具有减少在数据传送期间需要充电和放电并因此降低功耗的互连电容的目的的三维半导体存储器件具有：多个存储单元阵列芯片，其中作为分区的子行组合存储器并且被布置为对应于输入/输出位，堆叠在第一半导体芯片上; 以及用于连接存储单元阵列的芯片间互连，使得子组的相应输入/输出位相同，这些芯片间互连以与输入/输出位数相对应的数量提供并通过存储单元阵列芯片在堆叠的方向。

3. 发明申请

US20050286286A1 Three-dimensional semiconductor device provided with interchip interconnection selection means for electrically isolating interconnections other than selected interchip interconnections 有权
标题翻译：设置有芯片间互连选择装置的三维半导体装置，用于电绝缘除了选定的芯片间互连之外的互连
公开(公告)号：US20050286286A1
公开(公告)日：2005-12-29
申请号：US11148363
申请日：2005-06-09
申请人： Hideaki Saito , Yasuhiko Hagihara , Muneo Fukaishi , Masayuki Mizuno , Hiroaki Ikeda , Kayoko Shibata
发明人： Hideaki Saito , Yasuhiko Hagihara , Muneo Fukaishi , Masayuki Mizuno , Hiroaki Ikeda , Kayoko Shibata
IPC分类号： G11C5/06 , G11C7/18 , H01L25/065 , H01L27/108
CPC分类号： G11C5/063 , G11C5/02 , G11C7/18 , H01L25/0657 , H01L27/10897 , H01L2225/06527 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： In a three-dimensional semiconductor device in which a plurality of semiconductor circuit chips are stacked and that is provided with a plurality of interchip interconnections for signal transmission between these semiconductor circuit chips, when transmitting signals, only one interchip interconnection that serves for signal transmission is selected and other interchip interconnections are electrically isolated by means of switches that are provided between the interchip interconnections and signal lines. Interchip interconnection capacitance relating to the charge and discharge of interconnections is thus minimized.
摘要翻译：在堆叠多个半导体电路芯片并且在这些半导体电路芯片之间设置有用于信号传输的多个芯片间互连的三维半导体器件中，当传输信号时，仅用于信号传输的一个芯片间互连是所选择的和其它芯片间互连通过设置在芯片间互连和信号线之间的开关电隔离。因此，与互连的充电和放电相关的芯片间互连电容最小化。

4. 发明授权

US08315331B2 Transmission method, transmission circuit and transmission system 有权
标题翻译：传输方式，传输电路和传输系统
公开(公告)号：US08315331B2
公开(公告)日：2012-11-20
申请号：US12379167
申请日：2009-02-13
申请人： Hideaki Saito , Hiroaki Ikeda
发明人： Hideaki Saito , Hiroaki Ikeda
IPC分类号： H04L27/04
CPC分类号： H04L25/4906
摘要： A transmission method for transmitting transmission data via a single line, includes: transmitting, as the transmission data, data that has one rising or falling transition of the amplitude of the data in each clock cycle of a clock and that carries a 2- or greater-bit value, making use of the phase from the edge of the clock to the transition in amplitude of the data.
摘要翻译：一种用于通过单行发送传输数据的传输方法包括：作为发送数据发送在时钟的每个时钟周期中具有数据幅度的一个上升或下降转换的数据，并且携带2-或更大的数据使用从时钟边沿到数据幅度转换的相位。

5. 发明申请

US20080133809A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20080133809A1
公开(公告)日：2008-06-05
申请号：US11987501
申请日：2007-11-30
申请人： Hideaki Saito , Hiroaki Ikeda
发明人： Hideaki Saito , Hiroaki Ikeda
IPC分类号： G06F13/42
CPC分类号： G06F13/1647 , G06F13/1684 , G11C7/10 , G11C7/1075 , G11C8/04
摘要： A semiconductor device, which allows a bank interleaving operation by issuing a write command and a read command to different banks while switching them without a waiting time to thereby prevent a drop in data transfer efficiency, is provided. The semiconductor device includes: a memory chip with banks each including at least one memory cell; a logic chip; and data buses, provided corresponding to the banks, for transmitting/receiving write data and read data between the banks and the logic chip. The logic chip includes: a writing data bus for transmitting write data to the memory chip via a data bus; a reading data bus for receiving read data from the memory chip via a data bus; and a switch for, corresponding to a write command or a read command to a bank, connecting the writing data bus or the reading data bus to a data bus connected to the bank.
摘要翻译：提供一种半导体器件，其通过在不间断的时间切换它们的同时向不同的库发出写入命令和读取命令来允许存储体交错操作，从而防止数据传送效率的下降。半导体器件包括：存储器芯片，每个存储器芯片包括至少一个存储单元; 一个逻辑芯片; 以及与银行对应的用于发送/接收写入数据和在存储体和逻辑芯片之间读取数据的数据总线。逻辑芯片包括：写入数据总线，用于经由数据总线将写入数据发送到存储器芯片; 读取数据总线，用于经由数据总线从存储器芯片接收读取数据; 以及用于对应于写入命令或对存储体的读取命令的开关，将写入数据总线或读取数据总线连接到连接到存储体的数据总线。

6. 发明申请

US20060145301A1 Semiconductor chip and semiconductor device 审中-公开
标题翻译：半导体芯片和半导体器件
公开(公告)号：US20060145301A1
公开(公告)日：2006-07-06
申请号：US11326170
申请日：2006-01-05
申请人： Hideaki Saito , Yasuhiko Hagihara , Hiroaki Ikeda
发明人： Hideaki Saito , Yasuhiko Hagihara , Hiroaki Ikeda
IPC分类号： H01L29/93
CPC分类号： H01L29/945 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A wire embedded in a semiconductor substrate is covered with an insulating film, and a bias voltage is applied to the semiconductor substrate or to the wire to form a depletion layer extending from an edge of the insulating film. Alternatively, a semiconductor layer having a different conductivity type from the semiconductor substrate is formed within the semiconductor substrate to surround the insulating film.
摘要翻译：嵌入在半导体衬底中的导线被绝缘膜覆盖，并且偏置电压被施加到半导体衬底或线，以形成从绝缘膜的边缘延伸的耗尽层。或者，在半导体衬底内形成具有与半导体衬底不同的导电类型的半导体层以包围绝缘膜。

7. 发明申请

US20090315147A1 SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体芯片和半导体器件
公开(公告)号：US20090315147A1
公开(公告)日：2009-12-24
申请号：US12548095
申请日：2009-08-26
申请人： Hideaki Saito , Yasuhiko Hagihara , Hiroaki Ikeda
发明人： Hideaki Saito , Yasuhiko Hagihara , Hiroaki Ikeda
IPC分类号： H01L29/93
CPC分类号： H01L29/945 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A wire embedded in a semiconductor substrate is covered with an insulating film, and a bias voltage is applied to the semiconductor substrate or to the wire to form a depletion layer extending from an edge of the insulating film. Alternatively, a semiconductor layer having a different conductivity type from the semiconductor substrate is formed within the semiconductor substrate to surround the insulating film.
摘要翻译：嵌入在半导体衬底中的导线被绝缘膜覆盖，并且偏置电压被施加到半导体衬底或线，以形成从绝缘膜的边缘延伸的耗尽层。或者，在半导体衬底内形成具有与半导体衬底不同的导电类型的半导体层以包围绝缘膜。

8. 发明申请

US20090141827A1 DATA TRANSFER BETWEEN CHIPS IN A MULTI-CHIP SEMICONDUCTOR DEVICE WITH AN INCREASED DATA TRANSFER SPEED 有权
标题翻译：多芯片半导体器件之间的数据传输与数据传输速度增加
公开(公告)号：US20090141827A1
公开(公告)日：2009-06-04
申请号：US12323922
申请日：2008-11-26
申请人： Hideaki SAITO , Hiroaki Ikeda
发明人： Hideaki SAITO , Hiroaki Ikeda
IPC分类号： H04L27/00
CPC分类号： H01L25/0657 , G11C5/04 , G11C29/025 , H01L24/48 , H01L24/49 , H01L2224/48137 , H01L2224/49175 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/14 , H01L2924/3011 , H01L2924/00 , H01L2224/45099
摘要： A data transfer method is disclosed in a multi-chip semiconductor device which comprises a plurality of inter-chip wires. First, a test is conducted to determine whether or not each inter-chip wire is capable of normally transferring data, on circuits arranged on chips between which the inter-chip wire is connected. When an inter-chip wire incapable of normally transferring data exists, the data transfer speed of the buffer circuit that is on the chip on the transmission and that is connected to an inter-chip wire capable of normally transferring data is increased. The buffer circuit, whose data transfer speed has been increased, transfers data which would otherwise be transferred through the inter-chip wire incapable of normally transferring data, together with the data which should be transferred thereby, to the chip on the reception side chip through an inter-chip wire connected to the buffer circuit at the data transfer speed.
摘要翻译：在包括多个芯片间线的多芯片半导体器件中公开了一种数据传输方法。首先，进行测试，以确定每个芯片间线路是否能够正常传输数据，在布置在芯片之间的芯片上连接的芯片之间。当存在不能正常传送数据的芯片间线时，增加了传输上的芯片上并连接到能够正常传送数据的芯片间线的缓冲电路的数据传输速度。数据传输速度增加的缓冲电路将通过不能正常传送数据的芯片间线路传送的数据与应传送的数据一起传送到接收侧芯片上的芯片，通过以数据传输速度连接到缓冲电路的芯片间线。

9. 发明授权

US07352067B2 Stacked semiconductor device 有权
标题翻译：堆叠半导体器件
公开(公告)号：US07352067B2
公开(公告)日：2008-04-01
申请号：US11166229
申请日：2005-06-27
申请人： Muneo Fukaishi , Hideaki Saito , Yasuhiko Hagihara , Masayuki Mizuno , Hiroaki Ikeda , Kayoko Shibata
发明人： Muneo Fukaishi , Hideaki Saito , Yasuhiko Hagihara , Masayuki Mizuno , Hiroaki Ikeda , Kayoko Shibata
IPC分类号： H01L29/40
CPC分类号： H01L23/525 , G11C5/02 , G11C5/04 , H01L23/481 , H01L25/0657 , H01L2224/16145 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/01019 , H01L2924/13091 , H01L2924/3011 , H01L2924/00
摘要： A stacked semiconductor device includes a plurality of semiconductor chips and a conductive path extending through at least one of the semiconductor chips. The semiconductor chips are stacked together. The semiconductor chips are electrically connected by the conductive path, and the conductive path has a plurality of through-connections extending through the corresponding semiconductor chip.
摘要翻译：叠层半导体器件包括多个半导体芯片和延伸穿过至少一个半导体芯片的导电路径。半导体芯片堆叠在一起。半导体芯片通过导电路径电连接，并且导电路径具有延伸穿过对应的半导体芯片的多个通孔。

10. 发明授权

US07221614B2 Stacked semiconductor memory device 有权
标题翻译：堆叠半导体存储器件
公开(公告)号：US07221614B2
公开(公告)日：2007-05-22
申请号：US11151220
申请日：2005-06-14
申请人： Hideaki Saito , Yasuhiko Hagihara , Muneo Fukaishi , Masayuki Mizuno , Hiroaki Ikeda , Kayoko Shibata
发明人： Hideaki Saito , Yasuhiko Hagihara , Muneo Fukaishi , Masayuki Mizuno , Hiroaki Ikeda , Kayoko Shibata
IPC分类号： G11C5/00
CPC分类号： G11C5/025 , G11C5/02 , G11C5/063
摘要： The stacked semiconductor memory device of the present invention has the object of reducing the cost of developing a wide variety of memory devices and includes: a memory cell array chip that is equipped with memory cell arrays, an interface chip that is stacked with the memory cell array chip and that is provided with a memory configuration switching circuit for changing the input/output bit configuration of the memory cell arrays, and a plurality of interchip wires for connecting the memory cell array chip and the interface chip.
摘要翻译：本发明的叠层半导体存储器件的目的是降低开发各种存储器件的成本，并且包括：存储单元阵列芯片，其配备有存储单元阵列，与存储单元堆叠的接口芯片阵列芯片，并且具有用于改变存储单元阵列的输入/输出位配置的存储器配置切换电路和用于连接存储单元阵列芯片和接口芯片的多个芯片间线。

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