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1. 发明授权

US5940442A High speed data receiver 失效
标题翻译：高速数据接收机
公开(公告)号：US5940442A
公开(公告)日：1999-08-17
申请号：US791381
申请日：1997-01-30
申请人： Hee Wong , Abhijit Phanse
发明人： Hee Wong , Abhijit Phanse
IPC分类号： H04B3/04 , H04L25/06 , H03H7/30 , H04L27/06
CPC分类号： H04L25/062 , H04B3/04
摘要： A high speed data receiver for recovering binary or MLT3 encoded data which has been received via a cable. An adaptive equalizer provides signal gain which increases with frequency and adapts according to the length of the cable. Control over such adaptive equalizing is achieved by monitoring the peak-to-peak amplitude, amplitude peaks and differences between amplitude peaks of the equalized data signal during defined time intervals. Baseline restoration and dynamic data slicing are also provided.
摘要翻译：用于恢复已经通过电缆接收的二进制或MLT3编码数据的高速数据接收器。自适应均衡器提供随频率增加的信号增益，并根据电缆的长度进行调整。通过在规定的时间间隔期间监视均衡数据信号的峰 - 峰幅度，振幅峰值和振幅峰值之间的差异来实现对这种自适应均衡的控制。还提供了基线恢复和动态数据切片。

2. 发明授权

US5784019A Digital to analog converter for generating distributive analog control signals utilizing digital signal generator and control signal generator 失效
标题翻译：数模转换器，用于利用数字信号发生器和控制信号发生器产生分布式模拟控制信号
公开(公告)号：US5784019A
公开(公告)日：1998-07-21
申请号：US791367
申请日：1997-01-30
申请人： Hee Wong , Abhijit Phanse
发明人： Hee Wong , Abhijit Phanse
IPC分类号： H03M1/66 , H03M1/00
CPC分类号： H03M1/662
摘要： A digital-to-analog converter for converting a multiple bit digital input signal into multiple representative analog output signals includes a pulse density modulator, a logic controller, signal selection logic circuits and resistive-capacitive lowpass output filters. The pulse density modulator receives the N-M least significant bits of an N-bit digital input signal and in accordance therewith generates a pulse density modulated digital signal with a pulse density corresponding to a digital count of such N-M least significant bits. The logic controller receives the M most significant bits of the N-bit digital input signal and in accordance therewith generates multiple pairs of digital control signals. Each of the signal selection logic circuits receives the pulse density modulated digital signal and a respective pair of the digital control signals and in accordance therewith provides a respective one of a number of digital output signals. Together, each pair of digital control signals determines whether one of them or the pulse density modulated digital signal is provided as the respective digital output signal. The output filters lowpass filter the digital output signals to convert them to analog signals. The resulting analog signals represent a digital count of the original digital signal bits.
摘要翻译：用于将多位数字输入信号转换为多个代表性模拟输出信号的数模转换器包括脉冲密度调制器，逻辑控制器，信号选择逻辑电路和电阻电容低通滤波器。脉冲浓度调制器接收N位数字输入信号的N-M个最低有效位，并且根据其生成脉冲密度调制的数字信号，脉冲密度对应于这样的N-M个最低有效位的数字计数。逻辑控制器接收N位数字输入信号的M个最高有效位，并根据其产生多对数字控制信号。每个信号选择逻辑电路接收脉冲密度调制数字信号和相应的一对数字控制信号，并根据其提供多个数字输出信号中的相应一个。一对数字控制信号一起确定它们中的一个或脉冲浓度调制的数字信号是否被提供为相应的数字输出信号。输出滤波器对数字输出信号进行低通滤波，将其转换为模拟信号。所得到的模拟信号表示原始数字信号位的数字计数。

3. 发明授权

US5841810A Multiple stage adaptive equalizer 失效
标题翻译：多级自适应均衡器
公开(公告)号：US5841810A
公开(公告)日：1998-11-24
申请号：US791382
申请日：1997-01-30
申请人： Hee Wong , Abhijit Phanse
发明人： Hee Wong , Abhijit Phanse
IPC分类号： H04B3/14 , H03H7/30 , H03K5/159
CPC分类号： H04B3/145 , H04L25/03885
摘要： An adaptive equalizer for adaptively equalizing a data signal received via a communications path having a signal loss magnitude which increases with signal frequency includes multiple, serially coupled adaptive filter stages. The input data signal is successively filtered and magnitude weighted by successive adaptive filter circuits in accordance with corresponding, respective adaptation control signals. The frequency domain ratio of output signals to corresponding input signals for each adaptive filter circuit represents a corresponding, respective adaptive filter transfer function. An equalizer controller, in accordance with a single equalization control signal, generates the multiple, individual adaptation control signals. The product of all of the adaptive filter transfer functions is an approximate inverse of the transfer function of the input data signal communications path, with each individual adaptive filter transfer function being an approximate inverse of a transfer function which corresponds to a portion of the input data signal communications path. The magnitude of the equalization control signal corresponds to the transfer function of the input data signal communications path, while the magnitude of each adaptation control signal corresponds to one of the transfer function corresponding to a portion of the input data signal communications path.
摘要翻译：用于自适应均衡经由具有随信号频率增加的信号损耗大小的通信路径接收的数据信号的自适应均衡器包括多个串联耦合的自适应滤波器级。输入数据信号根据相应的各自的自适应控制信号被连续滤波和连续的自适应滤波电路的幅度加权。每个自适应滤波电路的输出信号与相应输入信号的频域比表示相应的各自的自适应滤波器传递函数。均衡器控制器根据单个均衡控制信号产生多个单独的自适应控制信号。所有自适应滤波器传递函数的乘积是输入数据信号通信路径的传递函数的近似逆，每个单独的自适应滤波器传递函数是对应于输入数据的一部分的传递函数的近似逆信号通信路径。均衡控制信号的幅度对应于输入数据信号通信路径的传递函数，而每个自适应控制信号的幅度对应于与输入数据信号通信路径的一部分相对应的传递函数之一。

4. 发明授权

US07979483B1 Multiplexed proportional-integral-derivative filter architecture (Mux-PID) for control-loop applications 有权
标题翻译：用于控制环应用的多路比例积分微分滤波器架构（Mux-PID）
公开(公告)号：US07979483B1
公开(公告)日：2011-07-12
申请号：US11506189
申请日：2006-08-16
申请人： Hee Wong
发明人： Hee Wong
IPC分类号： G06F17/10
CPC分类号： G05B11/42
摘要： A multiplexed digital proportional-integral-derivative filter receives error signal samples and operates in different states during sub-cycles of a single system cycle. A single multiplier and a single adder within the filter calculate at least portions of a proportional control signal, an integral control signal and a derivative control signal for one error signal sample during successive sub-cycles. The calculated control signal portions are aggregated to produce a filtered error signal for the respective error signal sample. The original resolution at lower cost, or increased resolution at the original cost, are achieved, as well as full programmability of loop gain with only negligible increase in loop latency.
摘要翻译：复用的数字比例积分微分滤波器接收误差信号采样并在单个系统周期的子周期期间以不同的状态操作。滤波器内的单个乘法器和单个加法器在连续的子周期期间计算一个误差信号采样的比例控制信号，积分控制信号和微分控制信号的至少一部分。所计算的控制信号部分被聚合以产生用于相应误差信号样本的滤波误差信号。以较低的成本或原始成本提高分辨率的原始分辨率，以及环路增益的全面可编程性，环路延迟增加可忽略不计。

5. 发明授权

US07930334B1 Gain control coding within proportional-integral-derivative filters for control-loop applications 有权
标题翻译：用于控制环应用的比例积分微分滤波器内的增益控制编码
公开(公告)号：US07930334B1
公开(公告)日：2011-04-19
申请号：US11731962
申请日：2007-04-02
申请人： Hee Wong
发明人： Hee Wong
IPC分类号： G06F17/10
CPC分类号： G05B11/42
摘要： Proportional, integral and derivative error gains within a proportional-integral-derivative filter are selected based on a magnitude of the error value and with successively higher gain values corresponding to larger ranges of error values. Coding of the error gains is selected based on one or more of: large code-dynamic-range to achieve good transient and quiescent responses; small code-step ratio to achieve smooth transitions between consecutive steps; large gain control range to satisfy the differing gain coverage requirements of the three proportional, integral and derivative error; positive and negative code symmetry with small step increment about zero; reservation of code space for dead band elimination; allocation of code space to prevent overflow/underflow during multiplying and bit-shifting; and minimum cost and power.
摘要翻译：基于比例积分微分滤波器中的比例积分和微分误差增益是基于误差值的大小以及对应于较大范围误差值的连续较高增益值来选择的。基于以下一个或多个选择误差增益的编码：大代码 - 动态范围以实现良好的瞬态和静态响应; 小代码步长比实现连续步骤之间的平滑过渡; 大增益控制范围满足三种比例，积分和微分误差的不同增益覆盖要求; 正，负码对称，小步增量约零; 预留死区消除代码空间; 分配代码空间，以防止在乘法和位移期间的溢出/下溢; 最低成本和最低功耗。

6. 发明授权

US07227476B1 Dither scheme using pulse-density modulation (dither PDM) 有权
标题翻译：使用脉冲密度调制（抖动PDM）的抖动方案
公开(公告)号：US07227476B1
公开(公告)日：2007-06-05
申请号：US11204297
申请日：2005-08-14
申请人： Hee Wong
发明人： Hee Wong
IPC分类号： H03M5/08
CPC分类号： H03M5/08
摘要： Dithering for the output of a digital pulse width modulator is provided by a pulse-density modulator formed from an adder incrementing a pulse-density count and generating a carry signal latched to a plus-one generator, which in turn adds a phase-division period to each of one or more selected pulses within a predetermined series of pulses from the digital pulse width modulator. Selected pulses are advanced by triggering a leading edge of the pulse at a time one phase-division period before the system clock edge, allowing trailing edges to be extended and providing minimal latency delay.
摘要翻译：用于数字脉宽调制器输出的抖动由脉冲浓度调制器提供，该脉冲密度调制器由加法器增加脉冲密度计数器并产生锁存到一加法器的进位信号，进位信号又增加一个相位分割周期到来自数字脉冲宽度调制器的预定的一系列脉冲内的一个或多个所选脉冲中的每一个。通过在系统时钟边沿之前的一个相位分割周期的时间触发脉冲的前沿，允许后沿被延长并且提供最小的等待时间延迟，所选脉冲被提前。

7. 发明授权

US06839551B1 Radio frequency mixer and method of operation 有权
标题翻译：射频混频器及操作方法
公开(公告)号：US06839551B1
公开(公告)日：2005-01-04
申请号：US09862048
申请日：2001-05-21
申请人： Hee Wong
发明人： Hee Wong
IPC分类号： H03D7/16 , H04B1/26 , H04B15/00
CPC分类号： H03D7/161
摘要： There is disclosed a radio frequency (RF) demodulation circuit comprising: 1) a first RF mixer having a first input port for receiving an in-phase RF signal having a frequency of RF and a second input port for receiving an in-phase local oscillator (LO) signal having a frequency of LO, wherein LO is approximately equal to one-half of RF, and wherein the first RF mixer generates a first intermediate frequency (IF) signal having a frequency of LO; 2) a second RF mixer having a first input port for receiving an out-of-phase RF signal having a frequency of RF and a second input port for receiving an out-of-phase local oscillator (LO) signal having a frequency of LO, and wherein the second RF mixer generates a second intermediate frequency (IF) signal having a frequency of LO; and 3) a first signal combiner for combining the first and second IF signals to generate a composite IF signal, wherein the first signal combiner combines a first leakage signal from the first RF mixer and a second leakage signal from the second RF mixer such that the first and second leakage signals at least partially cancel each other to produce an output leakage signal that is less than either of the first and second leakage signals.
摘要翻译：公开了一种射频（RF）解调电路，包括：1）第一RF混频器，具有用于接收具有RF频率的同相RF信号的第一输入端口和用于接收同相本机振荡器的第二输入端口（LO）信号，其中LO大约等于RF的一半，并且其中第一RF混频器产生具有LO频率的第一中频（IF）信号; 2）具有用于接收具有RF频率的异相RF信号的第一输入端口和用于接收具有频率为LO的异相本地振荡器（LO））信号的第二输入端口的第二RF混频器，，并且其中所述第二RF混频器产生具有LO频率的第二中频（IF）信号; 以及3）第一信号组合器，用于组合第一和第二IF信号以产生复合IF信号，其中第一信号组合器组合来自第一RF混频器的第一泄漏信号和来自第二RF混频器的第二泄漏信号，使得第一和第二泄漏信号至少部分地彼此抵消以产生小于第一和第二泄漏信号中的任一个的输出泄漏信号。

8. 发明授权

US06452420B1 Multi-dimensional differential signaling (MDDS) 有权
标题翻译：多维差分信号（MDDS）
公开(公告)号：US06452420B1
公开(公告)日：2002-09-17
申请号：US09865162
申请日：2001-05-24
申请人： Hee Wong
发明人： Hee Wong
IPC分类号： H03K1716
CPC分类号： H04L5/20 , H01L2224/48137 , H01L2224/49175 , H01L2924/13062 , H01L2924/00
摘要： A multi-dimensional differential signaling (MDDS) system is provided. A current loop is formed between N different communication lines and a corresponding differential is produced by loads coupled between the communication lines. The MDDS system may be two-dimensional or multi-dimensional. The number of communications lines chosen for the MDDS system affects the number of differential pairs in the system as well as the bits of information that may be transmitted. More than two states are provided by the MDDS system. For example, if three communication lines are used within the system, six states are provided. A star or delta load is used to produce the differential across the communication lines.
摘要翻译：提供了一种多维差分信号（MDDS）系统。在N个不同的通信线路之间形成电流回路，并且由通信线路之间耦合的负载产生相应的差分。 MDDS系统可以是二维或多维的。为MDDS系统选择的通信线路数量会影响系统中差分对的数量以及可能传输的信息位。 MDDS系统提供了两个以上的状态。例如，如果在系统内使用三条通信线路，则提供六种状态。星形或三角形负载用于在通信线路之间产生差分。

9. 发明授权

US5351275A Digital serial loop filter for high speed control systems 失效
标题翻译：用于高速控制系统的数字串行环路滤波器
公开(公告)号：US5351275A
公开(公告)日：1994-09-27
申请号：US729973
申请日：1991-07-15
申请人： Hee Wong , Tsun-Kit Chin
发明人： Hee Wong , Tsun-Kit Chin
IPC分类号： H03L7/06 , H03H17/02 , H03L7/093 , H03L7/099 , H03D3/24
CPC分类号： H03L7/093 , H03L7/0991 , H03L2207/04
摘要： A digital programmable loop filter for high frequency control systems applications utilizing a serial processing technique on pulse densities. The loop filter contains a proportional signal path and an integral signal path. A 4-time-slot sequencer time-multiplexes the serial proportional and integral signals to emulate a 1-pole/1-zero filter. An acquisition speed control circuit controls the acquisition time as well as step sizes of the scaler (proportional path) and the integrator (integral path) to provide loop variable programmability.
摘要翻译：一种用于高频控制系统应用的数字可编程环路滤波器，利用脉冲密度的串行处理技术。环路滤波器包含比例信号路径和积分信号路径。 4时隙定序器对串行比例和积分信号进行时间复用，以模拟1极/ 1 - 零滤波器。采集速度控制电路控制采集时间以及缩放器（比例路径）和积分器（积分路径）的步长，以提供循环变量可编程性。

10. 发明授权

US5295079A Digital testing techniques for very high frequency phase-locked loops 失效
标题翻译：用于非常高频锁相环的数字测试技术
公开(公告)号：US5295079A
公开(公告)日：1994-03-15
申请号：US731963
申请日：1991-07-18
申请人： Hee Wong , Tsun-Kit Chin
发明人： Hee Wong , Tsun-Kit Chin
IPC分类号： G01R31/28 , H03L7/06 , H03L7/08 , H03L7/099 , G01R23/02
CPC分类号： H03L7/0991 , G01R31/282
摘要： A digital testing system providing for cost efficient comprehensive testing of very high frequency phase-locked loop performance parameters. The system tests PLL performance parameters both at integrated circuit level and communication board level. Cost efficiency of the testing system allows for volume testing by manufacturers.
摘要翻译：数字测试系统，提供高频锁相环性能参数的成本效益综合测试。该系统在集成电路级和通信板级测试PLL性能参数。测试系统的成本效率允许制造商进行批量测试。

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