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1. 发明授权

US07701034B2 Dummy patterns in integrated circuit fabrication 有权
标题翻译：集成电路制造中的虚拟模式
公开(公告)号：US07701034B2
公开(公告)日：2010-04-20
申请号：US11281030
申请日：2005-11-17
申请人： Harry Chuang , Kong-Beng Thei , Cheng-Cheng Kuo
发明人： Harry Chuang , Kong-Beng Thei , Cheng-Cheng Kuo
IPC分类号： H01L27/088
CPC分类号： H01L27/0207 , H01L21/823437 , H01L21/823481 , Y10S438/926
摘要： An embodiment of the invention provides a semiconductor integrated circuit device having a dummy pattern for improving micro-loading effects. The device comprises an active region in a substrate and an isolation region in the substrate adjacent the active region. A plurality of dummy patterns are formed over the isolation region, wherein each dummy pattern is aligned parallel to and lengthwise dimension of the active region. The dummy patterns may have non-uniform spacing or non-uniform aspect ratios. The dummy pattern may have, in plan view, a rectangular shape, wherein its length is greater than the lengthwise dimension of the active region. The spacing between the dummy pattern and the active region may be less than about 1500 nm.
摘要翻译：本发明的实施例提供了一种具有用于改善微负载效应的虚拟图案的半导体集成电路器件。该器件包括衬底中的有源区和邻近有源区的衬底中的隔离区。在隔离区域上形成多个虚拟图案，其中每个虚拟图案与活动区域平行且纵向尺寸排列。假图形可以具有不均匀的间隔或不均匀的纵横比。虚拟图案可以在平面图中具有矩形形状，其长度大于活动区域的纵向尺寸。虚拟图案和有源区域之间的间隔可以小于约1500nm。

2. 发明申请

US20060163665A1 Dummy patterns in integrated circuit fabrication 有权
标题翻译：集成电路制造中的虚拟模式
公开(公告)号：US20060163665A1
公开(公告)日：2006-07-27
申请号：US11281030
申请日：2005-11-17
申请人： Harry Chuang , Kong-Beng Thei , Cheng-Cheng Kuo
发明人： Harry Chuang , Kong-Beng Thei , Cheng-Cheng Kuo
IPC分类号： H01L29/76
CPC分类号： H01L27/0207 , H01L21/823437 , H01L21/823481 , Y10S438/926
摘要： An embodiment of the invention provides a semiconductor integrated circuit device having a dummy pattern for improving micro-loading effects. The device comprises an active region in a substrate and an isolation region in the substrate adjacent the active region. A plurality of dummy patterns are formed over the isolation region, wherein each dummy pattern is aligned parallel to and lengthwise dimension of the active region. The dummy patterns may have non-uniform spacing or non-uniform aspect ratios. The dummy pattern may have, in plan view, a rectangular shape, wherein its length is greater than the lengthwise dimension of the active region. The spacing between the dummy pattern and the active region may be less than about 1500 nm.
摘要翻译：本发明的实施例提供了一种具有用于改善微负载效应的虚拟图案的半导体集成电路器件。该器件包括衬底中的有源区和邻近有源区的衬底中的隔离区。在隔离区域上形成多个虚拟图案，其中每个虚拟图案与活动区域平行且纵向尺寸排列。假图形可以具有不均匀的间隔或不均匀的纵横比。虚拟图案可以在平面图中具有矩形形状，其长度大于活动区域的纵向尺寸。虚拟图案和有源区域之间的间隔可以小于约1500nm。

3. 发明授权

US09054025B2 Process for controlling shallow trench isolation step height 有权
标题翻译：控制浅沟槽隔离台阶高度的工艺
公开(公告)号：US09054025B2
公开(公告)日：2015-06-09
申请号：US12478135
申请日：2009-06-04
申请人： Su-Chen Lai , Kong-Beng Thei , Harry Chuang , Gary Shen , Shun-Jang Liao
发明人： Su-Chen Lai , Kong-Beng Thei , Harry Chuang , Gary Shen , Shun-Jang Liao
IPC分类号： H01L21/66 , H01L21/762
CPC分类号： H01L22/20 , H01L21/76224 , H01L22/12
摘要： A method for fabricating an integrated circuit with improved uniformity among the step heights of isolation regions is disclosed. The method comprises providing a substrate having one or more trenches; filling the one or more trenches; performing a chemical mechanical polishing on the one or more filled trenches, wherein each of the one or more filled trenches comprises a thickness; measuring the thickness of each of the one or more filled trenches; determining, based on the measured thickness of each of the one or more filled trenches, an amount of time to perform an etching process; and performing the etching process for the determined amount of time.
摘要翻译：公开了一种用于制造隔离区的台阶高度之间的均匀性提高的集成电路的方法。该方法包括提供具有一个或多个沟槽的衬底; 填充一个或多个沟槽; 在所述一个或多个填充的沟槽上执行化学机械抛光，其中所述一个或多个填充的沟槽中的每一个包括厚度; 测量所述一个或多个填充沟槽中的每一个的厚度; 基于所测量的一个或多个填充的沟槽中的每一个的厚度来确定进行蚀刻处理的时间量; 并对所确定的时间量进行蚀刻处理。

4. 发明申请

US20120146057A1 METHOD OF FABRICATING SPACERS IN A STRAINED SEMICONDUCTOR DEVICE 有权
标题翻译：在应变半导体器件中制作间隔物的方法
公开(公告)号：US20120146057A1
公开(公告)日：2012-06-14
申请号：US13399394
申请日：2012-02-17
申请人： Chen-Pin Hsu , Kong-Beng Thei , Harry Chuang
发明人： Chen-Pin Hsu , Kong-Beng Thei , Harry Chuang
IPC分类号： H01L29/78 , H01L29/24
CPC分类号： H01L29/66545 , H01L21/823807 , H01L21/823864 , H01L29/0847 , H01L29/165 , H01L29/4966 , H01L29/517 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： The present disclosure provides a method for fabricating a semiconductor device that includes forming a gate stack over a silicon substrate, forming dummy spacers on sidewalls of the gate stack, isotropically etching the silicon substrate to form recess regions on either side of the gate stack, forming a semiconductor material in the recess regions, the semiconductor material being different from the silicon substrate, removing the dummy spacers, forming spacer layers having an oxide-nitride-oxide configuration over the gate stack and the semiconductor material, and etching the spacer layers to form gate spacers on the sidewalls of the gate stack.
摘要翻译：本公开提供了一种制造半导体器件的方法，该方法包括在硅衬底上形成栅极叠层，在栅极叠层的侧壁上形成虚设间隔物，各向同性地蚀刻硅衬底以在栅叠层的任一侧上形成凹陷区，形成在所述凹部区域中的半导体材料，所述半导体材料与所述硅衬底不同，去除所述虚设衬垫，在所述栅极堆叠和所述半导体材料上形成具有氧化物 - 氮化物 - 氧化物构造的间隔层，并蚀刻所述间隔层以形成栅极叠层的侧壁上的栅极间隔物。

5. 发明授权

US08174091B2 Fuse structure 有权
标题翻译：保险丝结构
公开(公告)号：US08174091B2
公开(公告)日：2012-05-08
申请号：US12503641
申请日：2009-07-15
申请人： Kong-Beng Thei , Chung Long Cheng , Chung-Shi Liu , Harry Chuang , Shien-Yang Wu , Shi-Bai Chen
发明人： Kong-Beng Thei , Chung Long Cheng , Chung-Shi Liu , Harry Chuang , Shien-Yang Wu , Shi-Bai Chen
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer.
摘要翻译：提出了电熔丝及其形成方法。在基材上形成第一层导电线。在第一层导电线上形成通孔。通孔优选包括阻挡层和导电材料。在通孔上形成第二层导电线。第一外部焊盘形成为耦合到第一层导电线。第二外部焊盘形成为耦合到第二层导电线。通孔，第一导线和第二导线适于作为电熔丝。电熔丝可以通过施加电流而烧坏。优选实施例的垂直结构适合于形成任何层。

6. 发明授权

US08153498B2 Downsize polysilicon height for polysilicon resistor integration of replacement gate process 有权
标题翻译：多晶硅电阻尺寸缩小，替代栅极工艺集成
公开(公告)号：US08153498B2
公开(公告)日：2012-04-10
申请号：US12401876
申请日：2009-03-11
申请人： Chen-Pin Hsu , Chung-Long Cheng , Kong-Beng Thei , Harry Chuang
发明人： Chen-Pin Hsu , Chung-Long Cheng , Kong-Beng Thei , Harry Chuang
IPC分类号： H01L21/8232
CPC分类号： H01L27/0629 , H01L21/82345 , H01L27/088 , H01L29/66545 , Y10S438/926
摘要： A semiconductor device and method for fabricating a semiconductor device protecting a resistive structure in gate replacement processing is disclosed. The method comprises providing a semiconductor substrate; forming at least one gate structure including a dummy gate over the semiconductor substrate; forming at least one resistive structure including a gate over the semiconductor substrate; exposing a portion of the gate of the at least one resistive structure; forming an etch stop layer over the semiconductor substrate, including over the exposed portion of the gate; removing the dummy gate from the at least one gate structure to create an opening; and forming a metal gate in the opening of the at least one gate structure.
摘要翻译：公开了一种用于制造在栅极替换处理中保护电阻结构的半导体器件的半导体器件和方法。该方法包括提供半导体衬底; 在半导体衬底上形成包括虚拟栅极的至少一个栅极结构; 在半导体衬底上形成包括栅极的至少一个电阻结构; 暴露所述至少一个电阻结构的栅极的一部分; 在所述半导体衬底上形成蚀刻停止层，包括在所述栅极的暴露部分上方; 从所述至少一个门结构移除所述伪栅极以产生开口; 以及在所述至少一个栅极结构的开口中形成金属栅极。

7. 发明授权

US08093120B2 Integrating a first contact structure in a gate last process 有权
标题翻译：在最后一个进程中集成第一个接触结构
公开(公告)号：US08093120B2
公开(公告)日：2012-01-10
申请号：US12839994
申请日：2010-07-20
申请人： Chiung-Han Yeh , Ming-Yuan Wu , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
发明人： Chiung-Han Yeh , Ming-Yuan Wu , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
IPC分类号： H01L21/8238
CPC分类号： H01L29/66606 , H01L21/823814 , H01L21/823871
摘要： A method is provided that includes providing a substrate; forming a transistor in the substrate, the transistor having a dummy gate; forming a dielectric layer over the substrate and transistor; forming a contact feature in the dielectric layer; and after forming the contact feature, replacing the dummy gate of the transistor with a metal gate. An exemplary contact feature is a dual contact.
摘要翻译：提供了一种提供基板的方法，在衬底中形成晶体管，晶体管具有虚拟栅极; 在衬底和晶体管上形成介电层; 在介电层中形成接触特征; 并且在形成接触特征之后，用金属栅极替换晶体管的虚拟栅极。示例性接触特征是双重接触。

8. 发明授权

US08035165B2 Integrating a first contact structure in a gate last process 有权
标题翻译：在最后一个进程中集成第一个接触结构
公开(公告)号：US08035165B2
公开(公告)日：2011-10-11
申请号：US12341891
申请日：2008-12-22
申请人： Chiung-Han Yeh , Ming-Yuan Wu , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
发明人： Chiung-Han Yeh , Ming-Yuan Wu , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66606 , H01L21/823814 , H01L21/823871
摘要： A semiconductor device is provided which includes a semiconductor substrate, a transistor formed on the substrate, the transistor having a gate stack including a metal gate and high-k gate dielectric and a dual first contact formed on the substrate. The dual first contact includes a first contact feature, a second contact feature overlying the first contact feature, and a metal barrier formed on sidewalls and bottom of the second contact feature, the metal barrier layer coupling the first contact feature to the second contact feature.
摘要翻译：提供一种半导体器件，其包括半导体衬底，形成在衬底上的晶体管，晶体管具有包括金属栅极和高k栅极电介质的栅极堆叠以及形成在衬底上的双重第一接触。所述双重第一接触包括第一接触特征，覆盖所述第一接触特征的第二接触特征以及形成在所述第二接触特征的侧壁和底部上的金属屏障，所述金属阻挡层将所述第一接触特征耦合到所述第二接触特征。

9. 发明授权

US07977181B2 Method for gate height control in a gate last process 有权
标题翻译：门最后进程门控高度的方法
公开(公告)号：US07977181B2
公开(公告)日：2011-07-12
申请号：US12420254
申请日：2009-04-08
申请人： Su-Chen Lai , Kong-Beng Thei , Harry Chuang
发明人： Su-Chen Lai , Kong-Beng Thei , Harry Chuang
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/823842 , H01L21/28088 , H01L21/823814 , H01L21/82385 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/66628 , H01L29/66636
摘要： Provided is a method that includes forming first and second gate structures in first and second regions, respectively, the first gate structure including a first hard mask layer having a first thickness and the second gate structure including a second hard mask layer having a second thickness less than the first thickness, removing the second hard mask layer from the second gate structure, forming an inter-layer dielectric (ILD) over the first and second gate structures, performing a first chemical mechanical polishing (CMP), remove the silicon layer from the second gate structure thereby forming a first trench, forming a first metal layer to fill the first trench, performing a second CMP, remove the remaining portion of the first hard mask layer and the silicon layer from the first gate structure thereby forming a second trench, forming a second metal layer to fill the second trench, and performing a third CMP.
摘要翻译：提供了一种方法，其包括分别在第一和第二区域中形成第一和第二栅极结构，第一栅极结构包括具有第一厚度的第一硬掩模层，第二栅极结构包括具有第二厚度的第二硬掩模层从第二栅极结构去除第二硬掩模层，在第一和第二栅极结构上形成层间电介质（ILD），执行第一化学机械抛光（CMP），将硅层从第二栅极结构，由此形成第一沟槽，形成第一金属层以填充第一沟槽，执行第二CMP，从第一栅极结构移除第一硬掩模层和硅层的剩余部分，从而形成第二沟槽，形成第二金属层以填充第二沟槽，并执行第三CMP。

10. 发明授权

US07919792B2 Standard cell architecture and methods with variable design rules 有权
标题翻译：标准单元结构和具有可变设计规则的方法
公开(公告)号：US07919792B2
公开(公告)日：2011-04-05
申请号：US12338632
申请日：2008-12-18
申请人： Oscar M. K. Law , Manoj Achyutrao Joshi , Kong-Beng Thei , Harry Chuang
发明人： Oscar M. K. Law , Manoj Achyutrao Joshi , Kong-Beng Thei , Harry Chuang
IPC分类号： H01L27/10 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L27/11807 , H01L27/0207 , H01L2924/0002 , H01L2924/00
摘要： Structures and methods for standard cell layouts having variable rules for spacing of layers to cell boundaries are disclosed. In one embodiment, a first standard cell layout is provided with a conductive layer having at least two portions spaced apart by a minimum spacing distance, the conductive layer having at least one portion spaced from a cell boundary by a first spacing distance of less than half of the minimum spacing distance; a second standard cell disposed adjacent the first standard cell with at least one second portion of the conductive layer in the second cell disposed adjacent the first portion in the first standard cell and spaced apart from a common cell boundary by a second spacing greater than half of the minimum; wherein the sum of the first and second spacings is at least as great as the minimum spacing. A method for forming standard is disclosed.
摘要翻译：公开了具有层与单元边界间隔的可变规则的标准单元布局的结构和方法。在一个实施例中，第一标准单元布局设置有导电层，其具有间隔最小间隔距离的至少两个部分，所述导电层具有至少一个与单元边界隔开的部分，第一间隔距离小于一半的最小间距; 与所述第一标准单元相邻设置的第二标准单元，所述第二单元中的所述导电层的至少一个第二部分与所述第一标准单元中的所述第一部分相邻设置，并且与所述第一标准单元间隔开第二间隔，最小其中所述第一和第二间距的总和至少与所述最小间隔一样大。公开了一种形成标准的方法。

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