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1. 发明授权

US06544889B2 Method for tungsten chemical vapor deposition on a semiconductor substrate 有权
公开(公告)号：US06544889B2
公开(公告)日：2003-04-08
申请号：US09768151
申请日：2001-01-24
申请人： Hans Vercammen , Joris Baele
发明人： Hans Vercammen , Joris Baele
IPC分类号： C23C1608
CPC分类号： C23C16/14 , H01L21/28556 , H01L21/28568
摘要： This invention relates to a method for tungsten chemical vapor deposition on a semiconductor substrate, comprising positioning said substrate within a deposition chamber, heating said substrate and depositing under low pressure the tungsten on the substrate by contacting the latter with a mixture of gases flowing through the deposition chamber comprising tungsten hexafluoride (WF6), hydrogen (H2) and at least one carrier gas. The mixture of gases comprises also silane (SiH4) with such a flow rate that the flow ratio WF6/SiH4 is from 2.5 to 6, the flow rate of WF6 being from 30 to 60 sccm, while the pressure in the deposition chamber is maintained from 0.13 to 5.33 kPa (1 and 40 Torr).

2. 发明申请

US20090014785A1 SEMICONDUCTOR DEVICE WITH IMPROVED BREAKDOWN PROPERTIES AND MANUFACTURING METHOD THEREOF 有权
标题翻译：具有改进的破坏特性的半导体器件及其制造方法
公开(公告)号：US20090014785A1
公开(公告)日：2009-01-15
申请号：US11828973
申请日：2007-07-26
申请人： Peter Moens , Filip Bauwens , Joris Baele , Marnix Tack
发明人： Peter Moens , Filip Bauwens , Joris Baele , Marnix Tack
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/42368 , H01L29/4916 , H01L29/495 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/6656 , H01L29/66719 , H01L29/66734 , H01L29/7809
摘要： The present invention provides a semiconductor device (20) comprising a trench (5) formed in a semiconductor substrate formed of a stack (4) of layers (1,2,3), a layer (6) of a first, grown dielectric material covering sidewalls and bottom of the trench (5), the layer (6) including one or more notches (13) at the bottom of the trench (5) and one or more spacers (14) formed of a second, deposited dielectric material to fill the one or more notches (13) in the layer (6) formed of the first, grown dielectric material. The semiconductor device (20) according to the present invention shows improved breakdown voltage and on-resistance. The present invention furthermore provides a method for the manufacturing of such semiconductor devices (20).
摘要翻译：本发明提供一种半导体器件（20），其包括形成在由层（1,2,3）的叠层（4）形成的半导体衬底中的沟槽（5），第一生长电介质材料的层（6）覆盖所述沟槽（5）的侧壁和底部，所述层（6）在所述沟槽（5）的底部包括一个或多个凹口（13）以及一个或多个由第二沉积介电材料形成的间隔物（14）填充由第一种生长的电介质材料形成的层（6）中的一个或多个凹口（13）。根据本发明的半导体器件（20）显示出改进的击穿电压和导通电阻。本发明还提供了制造这种半导体器件（20）的方法。

3. 发明授权

US07709889B2 Semiconductor device with improved breakdown properties and manufacturing method thereof 有权
标题翻译：具有改进的击穿特性的半导体器件及其制造方法
公开(公告)号：US07709889B2
公开(公告)日：2010-05-04
申请号：US11828973
申请日：2007-07-26
申请人： Peter Moens , Filip Bauwens , Joris Baele , Marnix Tack
发明人： Peter Moens , Filip Bauwens , Joris Baele , Marnix Tack
IPC分类号： H01L29/00
CPC分类号： H01L29/7813 , H01L29/0619 , H01L29/42368 , H01L29/4916 , H01L29/495 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/6656 , H01L29/66719 , H01L29/66734 , H01L29/7809
摘要： The present invention provides a semiconductor device (20) comprising a trench (5) formed in a semiconductor substrate formed of a stack (4) of layers (1,2,3), a layer (6) of a first, grown dielectric material covering sidewalls and bottom of the trench (5), the layer (6) including one or more notches (13) at the bottom of the trench (5) and one or more spacers (14) formed of a second, deposited dielectric material to fill the one or more notches (13) in the layer (6) formed of the first, grown dielectric material. The semiconductor device (20) according to the present invention shows improved breakdown voltage and on-resistance. The present invention furthermore provides a method for the manufacturing of such semiconductor devices (20).
摘要翻译：本发明提供一种半导体器件（20），其包括形成在由层（1,2,3）的叠层（4）形成的半导体衬底中的沟槽（5），第一生长电介质材料的层（6）覆盖所述沟槽（5）的侧壁和底部，所述层（6）在所述沟槽（5）的底部包括一个或多个凹口（13）以及一个或多个由第二沉积介电材料形成的间隔物（14）填充由第一种生长的电介质材料形成的层（6）中的一个或多个凹口（13）。根据本发明的半导体器件（20）显示出改进的击穿电压和导通电阻。本发明还提供了制造这种半导体器件（20）的方法。

4. 发明授权

US08115273B2 Deep trench isolation structures in integrated semiconductor devices 有权
标题翻译：集成半导体器件中的深沟槽隔离结构
公开(公告)号：US08115273B2
公开(公告)日：2012-02-14
申请号：US12163909
申请日：2008-06-27
申请人： Peter Moens , Filip Bauwens , Joris Baele
发明人： Peter Moens , Filip Bauwens , Joris Baele
IPC分类号： H01L29/00
CPC分类号： H01L21/763 , H01L21/761 , H01L21/76237
摘要： A integrated semiconductor device has a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type over the first layer, a third semiconductor layer of a second conductivity type over the second layer, an isolation trench extending through the entire depth of the second and third layers into the first layer, and a first region of the second conductivity type located next to the isolation trench and extending from an interface between the second and third layers, along an interface between the second layer and the isolation trench. This first region can help reduce a concentration of field lines where the isolation trench meets the interface of the second and third layers, and hence provide a better reverse breakdown characteristic.
摘要翻译：集成半导体器件具有第一导电类型的第一半导体层，第一层上的第一导电类型的第二半导体层，第二层上的第二导电类型的第三半导体层，跨越整个第二导电类型的隔离沟槽第二和第三层的深度进入第一层，以及第二导电类型的第一区域，位于隔离沟槽的旁边，并且沿着第二层和隔离沟槽之间的界面从第二层和第三层之间的界面延伸。该第一区域有助于降低隔离沟槽与第二层和第三层的界面相遇的场线的集中，从而提供更好的反向击穿特性。

5. 发明申请

US20090039460A1 DEEP TRENCH ISOLATION STRUCTURES IN INTEGRATED SEMICONDUCTOR DEVICES 有权
标题翻译：集成半导体器件中的深度分离分离结构
公开(公告)号：US20090039460A1
公开(公告)日：2009-02-12
申请号：US12163909
申请日：2008-06-27
申请人： Peter Moens , Filip Bauwens , Joris Baele
发明人： Peter Moens , Filip Bauwens , Joris Baele
IPC分类号： H01L29/00 , H01L21/76
CPC分类号： H01L21/763 , H01L21/761 , H01L21/76237
摘要： A integrated semiconductor device has a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type over the first layer, a third semiconductor layer of a second conductivity type over the second layer, an isolation trench extending through the entire depth of the second and third layers into the first layer, and a first region of the second conductivity type located next to the isolation trench and extending from an interface between the second and third layers, along an interface between the second layer and the isolation trench. This first region can help reduce a concentration of field lines where the isolation trench meets the interface of the second and third layers, and hence provide a better reverse breakdown characteristic.
摘要翻译：集成半导体器件具有第一导电类型的第一半导体层，第一层上的第一导电类型的第二半导体层，第二层上的第二导电类型的第三半导体层，跨越整个第二导电类型的隔离沟槽第二和第三层的深度进入第一层，以及第二导电类型的第一区域，位于隔离沟槽的旁边，并且沿着第二层和隔离沟槽之间的界面从第二层和第三层之间的界面延伸。该第一区域有助于降低隔离沟槽与第二层和第三层的界面相遇的场线的集中，从而提供更好的反向击穿特性。

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