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1. 发明授权

US07480776B2 Circuits and methods for providing variable data I/O width for semiconductor memory devices 有权
标题翻译：用于为半导体存储器件提供可变数据I / O宽度的电路和方法
公开(公告)号：US07480776B2
公开(公告)日：2009-01-20
申请号：US10732868
申请日：2003-12-10
申请人： Han-gu Sohn , Hai-jeong Sohn , Sei-jin Kim , Woo-seop Jeong
发明人： Han-gu Sohn , Hai-jeong Sohn , Sei-jin Kim , Woo-seop Jeong
IPC分类号： G06F12/00
CPC分类号： G11C7/1057 , G06F12/04 , G11C7/10 , G11C7/1051 , G11C7/1078 , G11C7/1084
摘要： Circuits and methods for controlling data I/O operations in semiconductor memory devices to provide variable data I/O widths for read, write and active memory operations. Circuits and methods for selectively controlling a data width of a data I/O buffer “on the fly” to enable variable data I/O widths during memory access operations.
摘要翻译：用于控制半导体存储器件中数据I / O操作的电路和方法，为读，写和有效存储器操作提供可变数据I / O宽度。用于选择性地控制数据I / O缓冲器的数据宽度的电路和方法，以便在存储器访问操作期间实现可变数据I / O宽度。

2. 发明申请

US20080291727A1 Semiconductor memory system having volatile memory and non-volatile memory that share bus, and method of controlling operation of non-volatile memory 有权
标题翻译：具有共享总线的易失性存储器和非易失性存储器的半导体存储器系统以及控制非易失性存储器的操作的方法
公开(公告)号：US20080291727A1
公开(公告)日：2008-11-27
申请号：US12078422
申请日：2008-03-31
申请人： Hui-kwon Seo , Han-gu Sohn , Sei-jin Kim
发明人： Hui-kwon Seo , Han-gu Sohn , Sei-jin Kim
IPC分类号： G11C16/04 , G11C7/00
CPC分类号： G06F13/4234 , G06F13/1694
摘要： Example embodiments relate to a semiconductor memory system which may include a volatile memory and a non-volatile memory that share a common bus, and a method for controlling the operation of the non-volatile memory. The semiconductor memory system may include a non-volatile memory and a memory controller. The non-volatile memory may include a buffer memory that temporarily stores data to be read from or to be written to a memory cell array, and an internal controller. The memory controller may transmits a mode signal to the non-volatile memory in response to a control signal, the control signal corresponds to either a read mode or a write mode to be applied to the non-volatile memory. In response to the mode signal, the internal controller may control the data to be read to be stored in the buffer memory, if the read mode is to be applied, and the internal controller may control the buffer memory to stand-by until a write command is received, if the write mode is to be applied.
摘要翻译：示例性实施例涉及可包括易失性存储器和共享公共总线的非易失性存储器的半导体存储器系统，以及用于控制非易失性存储器的操作的方法。半导体存储器系统可以包括非易失性存储器和存储器控制器。非易失性存储器可以包括临时存储要从或将要写入存储单元阵列的数据的缓冲存储器和内部控制器。存储器控制器可以响应于控制信号将模式信号发送到非易失性存储器，该控制信号对应于要施加到非易失性存储器的读取模式或写入模式。响应于模式信号，如果要应用读取模式，则内部控制器可以控制要读取的数据被存储在缓冲存储器中，并且内部控制器可以控制缓冲存储器待机直到写入如果要应用写入模式，则接收命令。

3. 发明申请

US20050169061A1 Multi-port memory device for buffering between hosts and non-volatile memory devices 有权
标题翻译：用于在主机和非易失性存储器件之间进行缓冲的多端口存储器件
公开(公告)号：US20050169061A1
公开(公告)日：2005-08-04
申请号：US11046407
申请日：2005-01-28
申请人： Han-gu Sohn , Sei-jin Kim
发明人： Han-gu Sohn , Sei-jin Kim
IPC分类号： G06F12/00 , G06F12/02 , G11C7/00 , G11C7/10 , G11C8/10 , G11C8/16 , G11C11/4093
CPC分类号： G11C7/1075 , G11C8/10 , G11C8/16 , G11C2207/2245
摘要： A multi-port volatile memory device includes a first port configured for data transfer to/from an external host system and the device. A volatile main memory core is configured to store data received thereat and read requested stored data thereform. A volatile sub memory core is configured to store data received thereat and read requested stored data therefrom. A main interface circuit is coupled to the first port and configured to provide data to/from the volatile main memory core and the first port in a master mode and configured to provide data to/from the volatile sub memory core and the first port in a slave mode. A second port is configured for data transfer to/from an external non-volatile memory device and the device. A sub interface circuit is coupled to the second port and configured to provide data to/from the volatile sub memory core and the second port in the slave mode.
摘要翻译：多端口易失性存储器设备包括被配置为用于向/从外部主机系统传送数据的第一端口和该设备。易失性主存储器核心被配置为存储在其上接收的数据并且读取请求的存储数据。易失性子存储器内核被配置为存储从其接收的数据并从其读取请求的存储数据。主接口电路耦合到第一端口并且被配置为以主模式向易失性主存储器核心和第一端口提供数据，并且被配置为向/从易失性子存储器核心和第一端口提供数据从模式。第二端口被配置用于从外部非易失性存储器设备和设备传送数据。子接口电路耦合到第二端口并且被配置为在从模式中向/从易失性子存储器内核和第二端口提供数据。

4. 发明申请

US20080266988A1 MULTI- PORT MEMORY DEVICE FOR BUFFERING BETWEEN HOSTS AND NON-VOLATILE MEMORY DEVICES 有权
标题翻译：用于缓冲主机和非易失性存储器件的多端口存储器件
公开(公告)号：US20080266988A1
公开(公告)日：2008-10-30
申请号：US12164527
申请日：2008-06-30
申请人： Han-gu Sohn , Sei-jin Kim
发明人： Han-gu Sohn , Sei-jin Kim
IPC分类号： G11C8/16 , G11C7/00 , G11C5/14
CPC分类号： G11C7/1075 , G11C8/10 , G11C8/16 , G11C2207/2245
摘要： A multi-port volatile memory device can include a first port that is configured for data transfer to/from an external host system and the device. A volatile main memory core is configured to store data received thereat and read requested stored data thereform. A volatile sub memory core can be configured to store data received thereat and read requested stored data therefrom. A main interface circuit can be coupled to the first port and can be configured to provide data to/from the volatile main memory core and the first port in a master mode and can be configured to provide data to/from the volatile sub memory core and the first port in a slave mode. A second port can be configured for data transfer to/from an external non-volatile memory device and the device and a sub interface circuit can be coupled to the second port and configured to provide data to/from the volatile sub memory core and the second port in the slave mode.
摘要翻译：多端口易失性存储器设备可以包括配置用于向/从外部主机系统和设备传送数据的第一端口。易失性主存储器核心被配置为存储在其上接收的数据并且读取请求的存储数据。易失性子存储器内核可以被配置为存储从其接收的数据并从其读取请求的存储数据。主接口电路可以耦合到第一端口并且可以被配置为以主模式向易失性主存储器核心和第一端口提供数据，并且可以被配置为向/从易失性子存储器核心提供数据，以及第一个端口处于从模式。可以将第二端口配置为用于向/从外部非易失性存储器设备传送数据，并且该设备和子接口电路可以耦合到第二端口并且被配置为向/从易失性子存储器核心提供数据，并且第二端口端口处于从模式。

5. 发明申请

US20080285372A1 MULTI- PORT MEMORY DEVICE FOR BUFFERING BETWEEN HOSTS AND NON-VOLATILE MEMORY DEVICES 失效
公开(公告)号：US20080285372A1
公开(公告)日：2008-11-20
申请号：US12183923
申请日：2008-07-31
申请人： Han-gu Sohn , Sei-jin Kim
发明人： Han-gu Sohn , Sei-jin Kim
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C7/1075 , G11C8/10 , G11C8/16 , G11C2207/2245
摘要： A multi-port volatile memory device can include a first port that is configured for data transfer to/from an external host system and the device. A volatile main memory core is configured to store data received thereat and read requested stored data thereform. A volatile sub memory core can be configured to store data received thereat and read requested stored data therefrom. A main interface circuit can be coupled to the first port and can be configured to provide data to/from the volatile main memory core and the first port in a master mode and can be configured to provide data to/from the volatile sub memory core and the first port in a slave mode. A second port can be configured for data transfer to/from an external non-volatile memory device and the device and a sub interface circuit can be coupled to the second port and configured to provide data to/from the volatile sub memory core and the second port in the slave mode.

6. 发明授权

US07411859B2 Multi-port memory device for buffering between hosts 有权
标题翻译：用于在主机之间进行缓冲的多端口存储设备
公开(公告)号：US07411859B2
公开(公告)日：2008-08-12
申请号：US11046407
申请日：2005-01-28
申请人： Han-gu Sohn , Sei-jin Kim
发明人： Han-gu Sohn , Sei-jin Kim
IPC分类号： G11C8/00
CPC分类号： G11C7/1075 , G11C8/10 , G11C8/16 , G11C2207/2245
摘要： A multi-port volatile memory device includes a first port configured for data transfer to/from an external host system and the device. A volatile main memory core is configured to store data received thereat and read requested stored data thereform. A volatile sub memory core is configured to store data received thereat and read requested stored data therefrom. A main interface circuit is coupled to the first port and configured to provide data to/from the volatile main memory core and the first port in a master mode and configured to provide data to/from the volatile sub memory core and the first port in a slave mode. A second port is configured for data transfer to/from an external non-volatile memory device and the device. A sub interface circuit is coupled to the second port and configured to provide data to/from the volatile sub memory core and the second port in the slave mode.
摘要翻译：多端口易失性存储器设备包括被配置为用于向/从外部主机系统传送数据的第一端口和该设备。易失性主存储器核心被配置为存储在其上接收的数据并且读取请求的存储数据。易失性子存储器内核被配置为存储从其接收的数据并从其读取请求的存储数据。主接口电路耦合到第一端口并且被配置为以主模式向易失性主存储器核心和第一端口提供数据，并且被配置为向/从易失性子存储器核心和第一端口提供数据从模式。第二端口被配置用于从外部非易失性存储器设备和设备传送数据。子接口电路耦合到第二端口并且被配置为在从模式中向/从易失性子存储器内核和第二端口提供数据。

7. 发明申请

US20050168469A1 Circuits and methods for transmission of addressing information to display memory circuits over data lines for sequential access to display data 审中-公开
标题翻译：用于传输寻址信息的电路和方法，用于通过数据线显示存储器电路以顺序访问显示数据
公开(公告)号：US20050168469A1
公开(公告)日：2005-08-04
申请号：US10963256
申请日：2004-10-12
申请人： Han-gu Sohn , Woo-seop Jeong , Sei-jin Kim
发明人： Han-gu Sohn , Woo-seop Jeong , Sei-jin Kim
IPC分类号： H04N5/66 , G06F3/14 , G06T1/60 , G09G3/20 , G09G5/00 , G09G5/39 , G09G5/42
CPC分类号： G09G5/39 , G09G3/20 , G09G2360/12
摘要： A display data control circuit can include a sequentially accessed memory circuit that is configured to sequentially store/retrieve image data for display received via data pins of the sequentially accessed memory circuit and a timing controller circuit that is configured to provide addressing information to the sequentially accessed memory circuit via the data pins thereof.
摘要翻译：显示数据控制电路可以包括顺序访问的存储器电路，其被配置为顺序地存储/检索通过顺序访问的存储器电路的数据引脚接收的用于显示的图像数据;以及定时控制器电路，其被配置为向顺序存取的存储器电路提供寻址信息存储器电路经由其数据引脚。

8. 发明授权

US08767450B2 Memory controllers to refresh memory sectors in response to writing signals and memory systems including the same 有权
标题翻译：存储器控制器用于刷新内存扇区以响应写入信号和包括其的存储器系统
公开(公告)号：US08767450B2
公开(公告)日：2014-07-01
申请号：US12662949
申请日：2010-05-13
申请人： Doo-gon Kim , Hui-kwon Seo , Cheol-kyu Kim , Sei-jin Kim , Yoon-ho Khang , Han-gu Sohn , Tae-yon Lee , Dae-won Ha
发明人： Doo-gon Kim , Hui-kwon Seo , Cheol-kyu Kim , Sei-jin Kim , Yoon-ho Khang , Han-gu Sohn , Tae-yon Lee , Dae-won Ha
IPC分类号： G11C11/00
CPC分类号： G11C16/3431 , G11C11/005 , G11C13/0004 , G11C13/0033 , G11C13/0069 , G11C2013/0078 , G11C2013/0088 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1616
摘要： A memory system includes a memory cell array having a plurality of memory sectors. Each memory sector includes a plurality of memory cells. The memory system further includes a controller configured to write data to the memory cell array in response to a writing signal. The controller is further configured to refresh a memory sector among the plurality of memory sectors each time a writing signal is provided. When N (N is a positive integer) memory cells are programmed, a programming current is less than or equal to about 0.75 mA*N.
摘要翻译：存储器系统包括具有多个存储器扇区的存储单元阵列。每个存储器扇区包括多个存储单元。存储器系统还包括配置成响应于写入信号将数据写入存储单元阵列的控制器。控制器还被配置为在每次提供写入信号时刷新多个存储器扇区中的存储器扇区。当N（N是正整数）存储单元被编程时，编程电流小于或等于大约0.75mA * N。

9. 发明授权

US07907469B2 Multi-port memory device for buffering between hosts and non-volatile memory devices 失效
标题翻译：用于在主机和非易失性存储器件之间进行缓冲的多端口存储器件
公开(公告)号：US07907469B2
公开(公告)日：2011-03-15
申请号：US12183923
申请日：2008-07-31
申请人： Han-gu Sohn , Sei-jin Kim
发明人： Han-gu Sohn , Sei-jin Kim
IPC分类号： G11C8/00
CPC分类号： G11C7/1075 , G11C8/10 , G11C8/16 , G11C2207/2245
摘要： A multi-port volatile memory device can include a first port that is configured for data transfer to/from an external host system and the device. A volatile main memory core is configured to store data received thereat and read requested stored data thereform. A volatile sub memory core can be configured to store data received thereat and read requested stored data therefrom. A main interface circuit can be coupled to the first port and can be configured to provide data to/from the volatile main memory core and the first port in a master mode and can be configured to provide data to/from the volatile sub memory core and the first port in a slave mode. A second port can be configured for data transfer to/from an external non-volatile memory device and the device and a sub interface circuit can be coupled to the second port and configured to provide data to/from the volatile sub memory core and the second port in the slave mode.
摘要翻译：多端口易失性存储器设备可以包括配置用于向/从外部主机系统和设备传送数据的第一端口。易失性主存储器核心被配置为存储在其上接收的数据并且读取请求的存储数据。易失性子存储器内核可以被配置为存储从其接收的数据并从其读取请求的存储数据。主接口电路可以耦合到第一端口并且可以被配置为以主模式向易失性主存储器核心和第一端口提供数据，并且可以被配置为向/从易失性子存储器核心提供数据，以及第一个端口处于从模式。可以将第二端口配置为用于向/从外部非易失性存储器设备传送数据，并且该设备和子接口电路可以耦合到第二端口并且被配置为向/从易失性子存储器核心提供数据，并且第二端口端口处于从模式。

10. 发明申请

US20100246247A1 Phase-change random access memories, memory devices, memory systems, methods of operating and methods of manufacturing the same 有权
标题翻译：相变随机存取存储器，存储器件，存储器系统，操作方法及其制造方法
公开(公告)号：US20100246247A1
公开(公告)日：2010-09-30
申请号：US12662949
申请日：2010-05-13
申请人： Doo-gon Kim , Hui-kwon Seo , Cheol-kyu Kim , Sei-jin Kim , Yoon-ho Khang , Han-gu Sohn , Tae-von Lee , Dae-won Ha
发明人： Doo-gon Kim , Hui-kwon Seo , Cheol-kyu Kim , Sei-jin Kim , Yoon-ho Khang , Han-gu Sohn , Tae-von Lee , Dae-won Ha
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C16/3431 , G11C11/005 , G11C13/0004 , G11C13/0033 , G11C13/0069 , G11C2013/0078 , G11C2013/0088 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1616
摘要： A memory system includes a memory cell array having a plurality of memory sectors. Each memory sector includes a plurality of memory cells. The memory system further includes a controller configured to write data to the memory cell array in response to a writing signal. The controller is further configured to refresh a memory sector among the plurality of memory sectors each time a writing signal is provided. When N (N is a positive integer) memory cells are programmed, a programming current is less than or equal to about 0.75 mA*N.
摘要翻译：存储器系统包括具有多个存储器扇区的存储单元阵列。每个存储器扇区包括多个存储单元。存储器系统还包括配置成响应于写入信号将数据写入存储单元阵列的控制器。控制器还被配置为在每次提供写入信号时刷新多个存储器扇区中的存储器扇区。当N（N是正整数）存储单元被编程时，编程电流小于或等于大约0.75mA * N。

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