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1. 发明授权

US07055113B2 Simplified process to design integrated circuits 有权
标题翻译：集成电路设计简化过程
公开(公告)号：US07055113B2
公开(公告)日：2006-05-30
申请号：US10335360
申请日：2002-12-31
申请人： Robert Neal Carlton Broberg, III , Jonathan William Byrn , Gary Scott Delp , Michael K. Eneboe , Gary Paul McClannahan , George Wayne Nation , Paul Gary Reuland , Thomas Sandoval , Matthew Scott Wingren
发明人： Robert Neal Carlton Broberg, III , Jonathan William Byrn , Gary Scott Delp , Michael K. Eneboe , Gary Paul McClannahan , George Wayne Nation , Paul Gary Reuland , Thomas Sandoval , Matthew Scott Wingren
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A set of tools is provided herein that produces useful, proven, and correct integrated semiconductor chips. Having as input either a customer's requirements for a chip, or a design specification for a partially manufactured semiconductor chip, the tools generate the RTL for control plane interconnect; memory composition, test, and manufacture; embedded logic analysis, trace interconnection, and utilization of spare resources on the chip; I/O qualification, JTAG, boundary scan, and SSO analysis; testable clock generation, control, and distribution; interconnection of all of the shared logic in a testable manner from a transistor fabric and/or configurable blocks in the slice. The input customer requirements are first conditioned by RTL analysis tools to quickly implement its logic. The slice definition and the RTL shell provides the correct logic for a set of logic interfaces for the design specification to connect. The tools share a common database so that logical interactions do not require multiple entries. The designs are qualified, tested, and verified by other tools. The tools further optimize the placement and timing of the blocks on the chip with respect to each other and with respect to placement on a board. The suite may be run as batch processes or can be driven interactively through a common graphical user interface. The tools also have an iterative mode and a global mode. In the iterative mode, one or more of the selected tools can generate the blocks or modify a design incrementally and then look at the consequences of the addition, or change. In the global mode, the semiconductor product is designed all at once in a batch process as above and then optimized altogether. This suite of generation tools generates design views including a qualified netlist for a foundry to manufacture.
摘要翻译：本文提供了一组工具，其产生有用的，经过验证的和正确的集成半导体芯片。输入客户对芯片的要求或部分制造的半导体芯片的设计规范，这些工具产生用于控制平面互连的RTL; 记忆组成，测试和制造; 嵌入式逻辑分析，跟踪互连和芯片上备用资源的利用; I / O资格，JTAG，边界扫描和SSO分析; 可测时钟生成，控制和分配; 以可测试的方式从晶体管结构和/或片中的可配置块互连所有共享逻辑。输入客户要求首先由RTL分析工具进行调节，以快速实现其逻辑。切片定义和RTL外壳为设计规范要连接的一组逻辑接口提供正确的逻辑。这些工具共享一个公共数据库，以便逻辑交互不需要多个条目。这些设计经过其他工具的合格，测试和验证。这些工具进一步优化了芯片上的块相对于彼此以及关于板上的放置的布局和定时。该套件可以作为批处理进行运行，也可以通过通用图形用户界面进行交互式驱动。这些工具也具有迭代模式和全局模式。在迭代模式中，一个或多个所选择的工具可以生成块或逐渐修改设计，然后查看添加或更改的后果。在全球模式下，半导体产品在上述批量处理中一次性设计，然后完全优化。这套生成工具生成设计视图，包括用于制造铸造的合格网表。

2. 发明授权

US07430725B2 Suite of tools to design integrated circuits 失效
标题翻译：套件设计集成电路的工具
公开(公告)号：US07430725B2
公开(公告)日：2008-09-30
申请号：US11156319
申请日：2005-06-18
申请人： Robert Neal Carlton Broberg, III , Jonathan William Byrn , Gary Scott Delp , Michael K. Eneboe , Gary Paul McClannahan , George Wayne Nation , Paul Gary Reuland , Thomas Sandoval , Matthew Scott Wingren
发明人： Robert Neal Carlton Broberg, III , Jonathan William Byrn , Gary Scott Delp , Michael K. Eneboe , Gary Paul McClannahan , George Wayne Nation , Paul Gary Reuland , Thomas Sandoval , Matthew Scott Wingren
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A set of tools is provided herein that produces useful, proven, and correct integrated semiconductor chips. Having as input either a customer's requirements for a chip, or a design specification for a partially manufactured semiconductor chip, the tools generate the RTL for control plane interconnect; memory composition, test, and manufacture; embedded logic analysis, trace interconnection, and utilization of spare resources on the chip; I/O qualification, JTAG, boundary scan, and SSO analysis; testable clock generation, control, and distribution; interconnection of all of the shared logic in a testable manner from a transistor fabric and/or configurable blocks in the slice. The input customer requirements are first conditioned by RTL analysis tools to quickly implement its logic. The slice definition and the RTL shell provides the correct logic for a set of logic interfaces for the design specification to connect. The tools share a common database so that logical interactions do not require multiple entries. The designs are qualified, tested, and verified by other tools. The tools further optimize the placement and timing of the blocks on the chip with respect to each other and with respect to placement on a board. The suite may be run as batch processes or can be driven interactively through a common graphical user interface. The tools also have an iterative mode and a global mode. In the iterative mode, one or more of the selected tools can generate the blocks or modify a design incrementally and then look at the consequences of the addition, or change. In the global mode, the semiconductor product is designed all at once in a batch process as above and then optimized altogether. This suite of generation tools generates design views including a qualified netlist for a foundry to manufacture.
摘要翻译：本文提供了一组工具，其产生有用的，经过验证的和正确的集成半导体芯片。输入客户对芯片的要求或部分制造的半导体芯片的设计规范，这些工具产生用于控制平面互连的RTL; 记忆组成，测试和制造; 嵌入式逻辑分析，跟踪互连和芯片上备用资源的利用; I / O资格，JTAG，边界扫描和SSO分析; 可测时钟生成，控制和分配; 以可测试的方式从晶体管结构和/或片中的可配置块互连所有共享逻辑。输入客户要求首先由RTL分析工具进行调节，以快速实现其逻辑。切片定义和RTL外壳为设计规范要连接的一组逻辑接口提供正确的逻辑。这些工具共享一个公共数据库，以便逻辑交互不需要多个条目。这些设计经过其他工具的合格，测试和验证。这些工具进一步优化了芯片上的块相对于彼此以及关于板上的放置的布局和定时。该套件可以作为批处理进行运行，也可以通过通用图形用户界面进行交互式驱动。这些工具也具有迭代模式和全局模式。在迭代模式中，一个或多个所选择的工具可以生成块或逐渐修改设计，然后查看添加或更改的后果。在全球模式下，半导体产品在上述批量处理中一次性设计，然后完全优化。这套生成工具生成设计视图，包括用于制造铸造的合格网表。

3. 发明授权

US07069523B2 Automated selection and placement of memory during design of an integrated circuit 有权
标题翻译：在集成电路设计期间自动选择和放置存储器
公开(公告)号：US07069523B2
公开(公告)日：2006-06-27
申请号：US10318623
申请日：2002-12-13
申请人： George Wayne Nation , Gary Scott Delp , Paul Gary Reuland
发明人： George Wayne Nation , Gary Scott Delp , Paul Gary Reuland
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/64
摘要： A tool for designing integrated circuits that optimizes the placement and timing of memory blocks within the circuit. Given a manufactured slice that has a number of blocks already diffused and logically integrated, the memory generation tool herein automatically considers the available diffused memory and the gate array of the slices to configure and optimize them into a customer's requirements for memory. The memory generation tool has a memory manager, a memory resource database, a memory resource selector, and a memory composer. Together these all interact to generate memories from the available memories within the memory resource database. The memory composer actually generates the RTL logic shells for the memories, and outputs the memory designs in Verilog, VHDL, or other tool synthesis language. Once a memory is created, it is tested. Upon successful testing, the memory manager updates the memory resource database to indicate the successfully tested memory is no longer available as a resource for the generation of further memories. A design integrator may review the memory designs output and further integrate the memory, its timing, testing, etc. with other blocks and functions of the integrated circuit.
摘要翻译：用于设计集成电路的工具，可优化电路内存储块的位置和时序。给定已经扩散和逻辑整合的多个块的制造片，这里的存储器生成工具自动考虑片的可用扩散存储器和门阵列，以将其配置和优化成客户对存储器的要求。存储器生成工具具有存储器管理器，存储器资源数据库，存储器资源选择器和存储器编程器。这些都一起进行交互以从存储器资源数据库内的可用存储器生成存储器。内存作曲家实际上为存储器生成RTL逻辑外壳，并以Verilog，VHDL或其他工具合成语言输出内存设计。一旦创建内存，就会进行测试。成功测试后，内存管理员更新内存资源数据库，以指示成功测试的内存不再可用作生成更多内存的资源。设计集成商可以检查存储器设计输出，并将存储器，其定时，测试等与集成电路的其他块和功能进一步集成。

4. 发明授权

US06823502B2 Placement of configurable input/output buffer structures during design of integrated circuits 失效
标题翻译：在集成电路设计期间配置输入/输出缓冲结构
公开(公告)号：US06823502B2
公开(公告)日：2004-11-23
申请号：US10334568
申请日：2002-12-31
申请人： Matthew Scott Wingren , George Wayne Nation , Gary Scott Delp , Jonathan William Byrn
发明人： Matthew Scott Wingren , George Wayne Nation , Gary Scott Delp , Jonathan William Byrn
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F2217/64
摘要： A tool for designing an integrated circuit and semiconductor product that generates correct RTL for I/O buffer structures in consideration of the requirements of diffused configurable I/O blocks and/or I/O hardmacs of the product. Given either a slice description of a partially manufactured semiconductor product, a designer can generate the I/O resources of an application set. Then given an application set having a transistor fabric, and the diffused configurable I/O blocks and/or the I/O hardmacs, and a plurality of accompanying shells, the I/O generation tool herein automatically reads a database having the slice description and generates the I/O buffer structures from the transistor fabric. The I/O generation tool further conditions and integrates input from either or both customer having her/his own logic and requesting a specific semiconductor product or from IP cores with their preestablished logic. The I/O generation tool creates correct RTL from the transistor fabric for correct placement, timing, testing, and function of I/O buffer amplifiers for the semiconductor product, either incrementally or globally. Once I/O buffer structures are created, they are qualified by a plurality of shells including a verification shell, a static timing analysis shell, a manufacturing test shell, and a RTL analysis shell.
摘要翻译：考虑到产品的扩散可配置I / O块和/或I / O硬件的要求，用于设计集成电路和半导体产品的工具，为I / O缓冲结构生成正确的RTL。给定部分制造的半导体产品的切片描述，设计者可以生成应用集的I / O资源。然后给出具有晶体管结构以及扩散的可配置I / O块和/或I / O硬件以及多个伴随壳的应用组，这里的I / O生成工具自动读取具有切片描述的数据库和从晶体管结构生成I / O缓冲结构。 I / O生成工具进一步调整并集成了具有自己的逻辑的客户的两个或两个客户的输入，并且请求特定的半导体产品或者从它们的预先建立的逻辑获得IP核。 I / O生成工具可以从晶体管结构创建正确的RTL，以正确布局，定时，测试和半导体产品的I / O缓冲放大器的功能，无论是增量还是全局。一旦创建了I / O缓冲区结构，它们就被多个shell限定，包括验证shell，静态时序分析shell，制造测试shell和RTL分析shell。

5. 发明授权

US07831653B2 Flexible template having embedded gate array and composable memory for integrated circuits 有权
标题翻译：具有嵌入式门阵列和集成电路可组合存储器的灵活模板
公开(公告)号：US07831653B2
公开(公告)日：2010-11-09
申请号：US10318792
申请日：2002-12-13
申请人： George Wayne Nation , Gary Scott Delp , William D. Scharf , Narayanan Raman , John N. Fryar, III , Majid Bemanian
发明人： George Wayne Nation , Gary Scott Delp , William D. Scharf , Narayanan Raman , John N. Fryar, III , Majid Bemanian
IPC分类号： G06F15/16
CPC分类号： H04L69/12
摘要： A partially manufactured semiconductor chip comprising a slice and a number of shells is a template for a communication and networking chip. The slice has a number of I/O ports, blocks, and PHYs. The hardmac PHYs are established to correspond to a high speed data transmission protocol. The interior of the template comprises logic gate arrays and configurable memory. Once particular protocols of data receipt and transmission are selected, the logic gate arrays and configurable memory can be programmed and otherwise configured to develop protocol layers for data networking and communication.
摘要翻译：包括片和多个壳的部分制造的半导体芯片是用于通信和网络芯片的模板。该片具有多个I / O端口，块和PHY。硬件PHY被建立为对应于高速数据传输协议。模板的内部包括逻辑门阵列和可配置存储器。一旦选择了数据接收和传输的特定协议，逻辑门阵列和可配置存储器可以被编程，否则被配置为开发用于数据联网和通信的协议层。

6. 发明授权

US07684326B2 Methods and structures for improved buffer management and dynamic adaptation of flow control status in high-speed communication networks 有权
标题翻译：改进缓冲管理和流量控制状态在高速通信网络中动态调整的方法和结构
公开(公告)号：US07684326B2
公开(公告)日：2010-03-23
申请号：US11873585
申请日：2007-10-17
申请人： George Wayne Nation , Gurumani Senthil , Gary Scott Delp
发明人： George Wayne Nation , Gurumani Senthil , Gary Scott Delp
IPC分类号： G06F11/00 , H04L12/28 , H04J3/07
CPC分类号： H04L47/39 , H04L47/10 , H04L47/30 , H04L49/90
摘要： Methods and structure for standardized, high-speed serial communication to reduce memory capacity requirements within receiving elements of a high-speed serial communication channel. In an exemplary SPI compliant embodiment of the invention, the semantic meaning of the STARVING, HUNGRY and SATISFIED flow control states is modified to allow the transmitting and receiving elements to manage buffer storage in a more efficient manner to thereby reduce memory capacity requirements while maintaining the integrity of flow control contracts and commitments. The methods and structure further provide for generation of storage metric information to dynamically update the flow control status information asynchronously with respect to data packet transmissions.
摘要翻译：用于标准化，高速串行通信的方法和结构，以减少高速串行通信信道的接收元件内的存储容量要求。在本发明的示例性SPI兼容实施例中，修改STARVING，HUNGRY和SATISFIED流控制状态的语义意义，以允许发送和接收元件以更有效的方式来管理缓冲存储器，从而降低存储容量要求，同时保持流动控制合同和承诺的完整性。所述方法和结构进一步提供用于产生存储度量信息以便相对于数据分组传输异步地动态地更新流控制状态信息。

7. 发明授权

US07301906B2 Methods and structures for improved buffer management and dynamic adaption of flow control status in high-speed communication networks 失效
标题翻译：改进缓冲管理和动态调整高速通信网络流量控制状态的方法和结构
公开(公告)号：US07301906B2
公开(公告)日：2007-11-27
申请号：US10232051
申请日：2002-08-30
申请人： George Wayne Nation , Gurumani Senthil , Gary Scott Delp
发明人： George Wayne Nation , Gurumani Senthil , Gary Scott Delp
IPC分类号： G06F11/00 , H04L12/28
CPC分类号： H04L47/39 , H04L47/10 , H04L47/30 , H04L49/90
摘要： Methods and structure for standardized, high-speed serial communication to reduce memory capacity requirements within receiving elements of a high-speed serial communication channel. In an exemplary SPI compliant embodiment of the invention, the semantic meaning of the STARVING, HUNGRY and SATISFIED flow control states is modified to allow the transmitting and receiving elements to manage buffer storage in a more efficient manner to thereby reduce memory capacity requirements while maintaining the integrity of flow control contracts and commitments. The methods and structure further provide for generation of storage metric information to dynamically update the flow control status information asynchronously with respect to data packet transmissions.
摘要翻译：用于标准化，高速串行通信的方法和结构，以减少高速串行通信信道的接收元件内的存储容量要求。在本发明的示例性SPI兼容实施例中，修改STARVING，HUNGRY和SATISFIED流控制状态的语义意义，以允许发送和接收元件以更有效的方式来管理缓冲存储器，从而降低存储容量要求，同时保持流动控制合同和承诺的完整性。所述方法和结构进一步提供用于产生存储度量信息以便相对于数据分组传输异步地动态地更新流控制状态信息。

8. 发明授权

US07491579B2 Composable system-in-package integrated circuits and process of composing the same 失效
标题翻译：可组合的系统级封装集成电路及其组成过程
公开(公告)号：US07491579B2
公开(公告)日：2009-02-17
申请号：US11079028
申请日：2005-03-14
申请人： Gary S. Delp , George Wayne Nation
发明人： Gary S. Delp , George Wayne Nation
IPC分类号： H01L21/00
CPC分类号： G06F17/5045 , G06F2217/64
摘要： An SIP for performing a plurality of hard and soft functions comprises standard IC die and custom platforms mounted to a substrate. Die are identified for each standard hard function, such as memory, processing, I/O and other standard functions and one or more user-configurable base platforms are selected that, when configured, execute the custom soft functions. Optionally, the substrate is laminated to the die and the platforms are attached to the substrate. Testing is performed by defining the configured base platforms coupled to logic representing the die and their connections and performing placement and timing closure on the combination.
摘要翻译：用于执行多个硬和软功能的SIP包括安装到基板的标准IC裸片和定制平台。针对每个标准硬功能（例如存储器，处理，I / O和其他标准功能）识别芯片，并且选择一个或多个用户可配置的基本平台，当配置时，执行定制软件功能。可选地，将基底层压到模具上，并将平台附接到基底。通过定义耦合到表示芯片及其连接的逻辑的配置的基础平台并在组合上执行放置和时序闭合来执行测试。

9. 发明授权

US6041324A System and method for identifying valid portion of computer resource identifier 失效
标题翻译：用于识别计算机资源标识符的有效部分的系统和方法
公开(公告)号：US6041324A
公开(公告)日：2000-03-21
申请号：US972106
申请日：1997-11-17
申请人： Joel Ray Earl , David John Goodman , George Wayne Nation
发明人： Joel Ray Earl , David John Goodman , George Wayne Nation
IPC分类号： G06F17/30 , H04L29/06 , H04L29/12
CPC分类号： H04L29/06 , G06F17/30887 , H04L29/12009 , H04L61/00 , H04L67/42 , Y10S707/99939 , Y10S707/99945
摘要： A system and method for receiving and validating user input for a computer resource entered into a computing system or network, and distinguishing valid and invalid portions of the user input. The invalid resource identifier, which ranges from a least specific portion to a most specific portion, is partitioned into a plurality of fields. At least one of the fields corresponding to the most specific portion of the invalid resource identifier is removed from the invalid resource identifier to create a modified resource identifier, wherein the modified resource identifier is used to attempt to access a higher level computer resource. The fields corresponding to the most specific portion of the resource identifier are removed until the modified resource identifier proves to be a valid resource identifier which can access a computer resource. The valid resource identifier is distinguished from the invalid resource identifier entered by the user, so that the user can easily determine a point at which the input is invalid.
摘要翻译：一种用于接收和验证输入到计算系统或网络的计算机资源的用户输入以及区分用户输入的有效和无效部分的系统和方法。从最小特定部分到最特定部分的无效资源标识符被划分为多个字段。从无效资源标识符中删除与无效资源标识符的最具体部分相对应的字段中的至少一个，以创建修改的资源标识符，其中修改的资源标识符用于尝试访问较高级别的计算机资源。删除对应于资源标识符的最具体部分的字段，直到修改的资源标识符被证明是可以访问计算机资源的有效资源标识符。有效资源标识符与用户输入的无效资源标识不同，使用户可以容易地确定输入无效点。

10. 发明授权

US5983244A Indicating when clickable image link on a hypertext image map of a computer web browser has been traversed 失效
标题翻译：指示计算机网络浏览器的超文本图像映射上的可点击图像链接已经遍历
公开(公告)号：US5983244A
公开(公告)日：1999-11-09
申请号：US721490
申请日：1996-09-27
申请人： George Wayne Nation
发明人： George Wayne Nation
IPC分类号： G06F17/30 , G06F17/21
CPC分类号： G06F17/30899
摘要： The invention is a method to mark hypertext links in an image map that have been traversed. The invention actually modifies the image map of the links by inserting a marker or changing the color associated with the coordinates of a particular image link on the image map. The history files of links that have been traversed are first checked to determine if the image has changed or is otherwise out of date. The image map or a copy of the image map is then modified and displayed.
摘要翻译：本发明是用于标记已经遍历的图像映射中的超文本链接的方法。本发明通过在图像映射上插入标记或改变与特定图像链接的坐标相关联的颜色来实际地修改链接的图像映射。首先检查已经遍历的链接的历史文件，以确定图像是否已更改或过时。然后修改和显示图像映射或图像映射的副本。

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