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1. 发明授权

US07613050B2 Sense-amplifier assist (SAA) with power-reduction technique 失效
标题翻译：功率减小技术的感应放大器辅助（SAA）
公开(公告)号：US07613050B2
公开(公告)日：2009-11-03
申请号：US11764237
申请日：2007-06-18
申请人： George Maria Braceras , Harold Pilo , Fred John Towler
发明人： George Maria Braceras , Harold Pilo , Fred John Towler
IPC分类号： G11C7/06 , G11C8/00 , H01L29/00
CPC分类号： G11C7/06 , G11C7/02 , G11C7/12 , G11C11/41 , G11C11/419 , G11C29/08
摘要： A design structure comprising an apparatus which reduces the power in memory devices in general and, in particular, static random access memory (SRAM) arrays featuring sense amplifier assist (SAA) circuitry. The design structure limits the implementation of the SAA circuitry to SRAM array blocks that do not meet the application voltage requirements.
摘要翻译：一种设计结构，其包括通常降低存储器件功率的装置，特别是具有读出放大器辅助（SAA）电路的静态随机存取存储器（SRAM）阵列。设计结构将SAA电路的实现限制在不符合应用电压要求的SRAM阵列块中。

2. 发明授权

US08611164B2 Device and method for detecting resistive defect 有权
标题翻译：用于检测电阻缺陷的装置和方法
公开(公告)号：US08611164B2
公开(公告)日：2013-12-17
申请号：US13195114
申请日：2011-08-01
申请人： George Maria Braceras , Harold Pilo , George E. Rudgers
发明人： George Maria Braceras , Harold Pilo , George E. Rudgers
IPC分类号： G11C29/00 , G11C7/12
CPC分类号： G11C29/025 , G11C11/41 , G11C29/50008 , G11C2029/1202 , G11C2029/1204
摘要： The invention provides a device and method for detecting a resistive defect in a static random access memory (SRAM) device. A first aspect of the invention provides a static random access memory (SRAM) device comprising: a bitline; a wordline; a bitline precharge circuit electrically connected to the bitline and adapted to provide to the bitline a first precharge voltage for precharging the bitline during normal operation of the SRAM device and a second precharge voltage less than the first precharge voltage for testing the SRAM device for a resistive defect between the bitline and the wordline.
摘要翻译：本发明提供一种用于检测静态随机存取存储器（SRAM）装置中的电阻性缺陷的装置和方法。本发明的第一方面提供了一种静态随机存取存储器（SRAM）装置，包括：位线; 一字电位连接到所述位线的位线预充电电路，并且适于向所述位线提供用于在所述SRAM器件的正常操作期间对所述位线进行预充电的第一预充电电压以及小于所述第一预充电电压的第二预充电电压，以用于测试所述SRAM器件的电阻位线和字线之间的缺陷。

3. 发明申请

US20130033948A1 DEVICE AND METHOD FOR DETECTING RESISTIVE DEFECT 有权
标题翻译：用于检测电阻缺陷的装置和方法
公开(公告)号：US20130033948A1
公开(公告)日：2013-02-07
申请号：US13195114
申请日：2011-08-01
申请人： George Maria Braceras , Harold Pilo , George E. Rudgers
发明人： George Maria Braceras , Harold Pilo , George E. Rudgers
IPC分类号： G11C29/00 , G11C7/12
CPC分类号： G11C29/025 , G11C11/41 , G11C29/50008 , G11C2029/1202 , G11C2029/1204
摘要： The invention provides a device and method for detecting a resistive defect in a static random access memory (SRAM) device. A first aspect of the invention provides a static random access memory (SRAM) device comprising: a bitline; a wordline; a bitline precharge circuit electrically connected to the bitline and adapted to provide to the bitline a first precharge voltage for precharging the bitline during normal operation of the SRAM device and a second precharge voltage less than the first precharge voltage for testing the SRAM device for a resistive defect between the bitline and the wordline.
摘要翻译：本发明提供一种用于检测静态随机存取存储器（SRAM）装置中的电阻性缺陷的装置和方法。本发明的第一方面提供了一种静态随机存取存储器（SRAM）装置，包括：位线; 一字电位连接到所述位线的位线预充电电路，并且适于向所述位线提供用于在所述SRAM器件的正常操作期间对所述位线进行预充电的第一预充电电压以及小于所述第一预充电电压的第二预充电电压，以用于测试所述SRAM器件的电阻位线和字线之间的缺陷。

4. 发明授权

US08233337B2 SRAM delay circuit that tracks bitcell characteristics 有权
标题翻译：跟踪位单元特性的SRAM延迟电路
公开(公告)号：US08233337B2
公开(公告)日：2012-07-31
申请号：US12581440
申请日：2009-10-19
申请人： Igor Arsovski , George Maria Braceras , Robert M. Houle , Harold Pilo
发明人： Igor Arsovski , George Maria Braceras , Robert M. Houle , Harold Pilo
IPC分类号： G11C7/00 , G11C7/02 , G11C11/00
CPC分类号： G11C11/419 , G11C7/04 , G11C7/08 , G11C7/14 , G11C7/22 , G11C7/222 , G11C7/227 , G11C11/413
摘要： An SRAM delay circuit that tracks bitcell characteristics. A circuit is disclosed that includes an input node for receiving an input signal; a reference node for capturing a reference current from a plurality of reference cells; a capacitance network having a discharge that is controlled by the reference current; and an output circuit that outputs the input signal with a delay, wherein the delay is controlled by the discharge of the capacitance network.
摘要翻译：跟踪位单元特性的SRAM延迟电路。公开了一种电路，其包括用于接收输入信号的输入节点; 用于从多个参考单元捕获参考电流的参考节点; 具有由参考电流控制的放电的电容网络; 以及输出电路，其输出具有延迟的输入信号，其中通过电容网络的放电来控制延迟。

5. 发明申请

US20110090750A1 SRAM DELAY CIRCUIT THAT TRACKS BITCELL CHARACTERISTICS 有权
标题翻译： SRAM延迟电路跟踪比特尔特性
公开(公告)号：US20110090750A1
公开(公告)日：2011-04-21
申请号：US12581440
申请日：2009-10-19
申请人： Igor Arsovski , George Maria Braceras , Robert M. Houle , Harold Pilo
发明人： Igor Arsovski , George Maria Braceras , Robert M. Houle , Harold Pilo
IPC分类号： G11C7/00 , G11C7/02 , G11C11/00
CPC分类号： G11C11/419 , G11C7/04 , G11C7/08 , G11C7/14 , G11C7/22 , G11C7/222 , G11C7/227 , G11C11/413
摘要： An SRAM delay circuit that tracks bitcell characteristics. A circuit is disclosed that includes an input node for receiving an input signal; a reference node for capturing a reference current from a plurality of reference cells; a capacitance network having a discharge that is controlled by the reference current; and an output circuit that outputs the input signal with a delay, wherein the delay is controlled by the discharge of the capacitance network.
摘要翻译：跟踪位单元特性的SRAM延迟电路。公开了一种电路，其包括用于接收输入信号的输入节点; 用于从多个参考单元捕获参考电流的参考节点; 具有由参考电流控制的放电的电容网络; 以及输出电路，其输出具有延迟的输入信号，其中通过电容网络的放电来控制延迟。

6. 发明授权

US08611169B2 Fine granularity power gating 有权
标题翻译：细粒度电源门控
公开(公告)号：US08611169B2
公开(公告)日：2013-12-17
申请号：US13315604
申请日：2011-12-09
申请人： Robert M. Houle , Steven H. Lamphier , Harold Pilo
发明人： Robert M. Houle , Steven H. Lamphier , Harold Pilo
IPC分类号： G11C5/14
CPC分类号： G11C11/413 , G11C8/08 , G11C8/10
摘要： An approach for providing fine granularity power gating of a memory array is described. In one embodiment, power supply lines are disposed in a horizontal dimension of the memory array parallel to the word lines that access cells arranged in rows and columns of the array, wherein each of the supply lines are shared by adjacent cells in the memory. Power supply lines that activate a row selected by one of the word lines are supplied a full-power voltage value and power supply lines that activate rows adjacent to the selected row are supplied a half-power voltage value, while the power supply lines of the remaining rows in the memory array are supplied a power-gated voltage value.
摘要翻译：描述了一种用于提供存储器阵列的精细粒度电源门控的方法。在一个实施例中，电源线被布置在存储器阵列的水平维度上，平行于访问以阵列的行和列排列的单元的字线，其中每个供电线由存储器中的相邻单元共享。激活由一条字线选择的行的电源线被提供全功率电压值，并且激活与所选行相邻的行的电源线被提供半电源电压值，而电源线存储器阵列中的剩余行被提供电源门控电压值。

7. 发明申请

US20120075919A1 Methods and Systems for Adjusting Wordline Up-Level Voltage to Improve Production Yield Relative to SRAM-Cell Stability 有权
标题翻译：用于调整字面上升电压的方法和系统，以提高相对于SRAM单元稳定性的产量
公开(公告)号：US20120075919A1
公开(公告)日：2012-03-29
申请号：US12892191
申请日：2010-09-28
申请人： Igor Arsovski , George M. Braceras , Kevin W. Gorman , Robert M. Houle , Harold Pilo
发明人： Igor Arsovski , George M. Braceras , Kevin W. Gorman , Robert M. Houle , Harold Pilo
IPC分类号： G11C11/00
CPC分类号： G11C11/413 , G11C8/08
摘要： Methods of setting wordline up-level voltage in as-fabricated SRAM. In one example, the method includes determining the relative speed, or strength, of 1) the combination of the pass-gate and pull-down devices and 2) the pull-up devices in the bitcells of the SRAM. These relative strengths are then used to adjust the wordline up-level voltage, if needed, to decrease the likelihood of the SRAM experiencing a stability failure. Corresponding systems are provided for determining the relative strengths of the devices of interest, for determining the amount of up-level voltage adjustment needed, and for selecting and setting the up-level voltage.
摘要翻译：在制造的SRAM中设置字线上电压的方法。在一个示例中，该方法包括确定1）通过栅极和下拉器件的组合的相对速度或强度，以及2）SRAM的位单元中的上拉器件。然后，如果需要，这些相对强度可用于调整字线上电压，以降低SRAM遇到稳定性故障的可能性。提供相应的系统用于确定感兴趣的装置的相对强度，用于确定所需的上限电压调整量以及用于选择和设定上限电压。

8. 发明授权

US07894291B2 Circuit and method for controlling a standby voltage level of a memory 有权
标题翻译：用于控制存储器的待机电压电平的电路和方法
公开(公告)号：US07894291B2
公开(公告)日：2011-02-22
申请号：US11162847
申请日：2005-09-26
申请人： George M. Braceras , John A. Fifield , Harold Pilo
发明人： George M. Braceras , John A. Fifield , Harold Pilo
IPC分类号： G11C5/14
CPC分类号： G11C11/417 , G11C5/147
摘要： A memory is provided which can be operated at an active rate of power consumption in an active operational mode and at a predetermined reduced rate of power consumption in a standby operational mode. The memory includes a current generating circuit which is operable to supply a predetermined magnitude of current to a sample power supply input terminal of a sample memory cell representative of memory cells of the memory, the predetermined magnitude of current corresponding to the predetermined reduced rate of power consumption. A voltage follower circuit is operable to output a standby voltage level equal to a voltage level at the sample power supply input terminal when the predetermined magnitude of current is supplied thereto. A memory cell array of the memory is operable to store data. In the standby operational mode, a switching circuit is operable to supply power at the standby voltage level to a power supply input terminal of the memory cell array. This permits data to remain stored in the memory during the standby mode. During an active operational mode, the switching circuit is operable to connect the power supply input terminal at the power supply to supply power at the active voltage level to the memory cell array. During the active operational mode, data can be stored into the memory cell array and retrieved from the memory cell array.
摘要翻译：提供一种存储器，其可以在主动操作模式中以在备用操作模式中以预定的降低的功率消耗速率以有效的功率消耗速率操作。存储器包括电流产生电路，其可操作以向代表存储器的存储器单元的采样存储单元的采样电源输入端提供预定大小的电流，与预定的降低的功率比相对应的预定电流值消费。电压跟随器电路可操作以当提供预定电流大小时输出等于采样电源输入端的电压电平的备用电压电平。存储器的存储单元阵列可操作以存储数据。在待机操作模式中，切换电路可操作以将备用电压电平的电力提供给存储单元阵列的电源输入端。这在待机模式期间允许数据保存在存储器中。在有效操作模式期间，开关电路可操作地连接电源处的电源输入端，以将有源电压电平的电力提供给存储单元阵列。在主动操作模式期间，可将数据存储到存储单元阵列中并从存储单元阵列检索。

9. 发明授权

US07548080B2 Method and apparatus for burn-in optimization 失效
标题翻译：老化优化的方法和装置
公开(公告)号：US07548080B2
公开(公告)日：2009-06-16
申请号：US11538833
申请日：2006-10-05
申请人： Wagdi W. Abadeer , Harold Pilo , Daryl M. Seitzer
发明人： Wagdi W. Abadeer , Harold Pilo , Daryl M. Seitzer
IPC分类号： G01R31/02
CPC分类号： G01R31/287 , G01R31/2874
摘要： The present invention provides a method and apparatus for optimizing the burn-in of integrated circuits. One embodiment of the method comprises: performing a first portion of the burn-in process of the integrated circuit; monitoring a power dissipation of the integrated circuit during the first portion of the burn-in process; increasing a burn-in temperature until the power dissipation of the integrated circuit reaches a predetermined maximum power dissipation; and performing a subsequent portion of the burn-in process of the integrated circuit at the increased burn-in temperature.
摘要翻译：本发明提供一种用于优化集成电路的老化的方法和装置。该方法的一个实施例包括：执行集成电路的老化过程的第一部分; 在老化过程的第一部分期间监测集成电路的功耗; 增加老化温度，直到集成电路的功耗达到预定的最大功耗; 以及在增加的老化温度下执行集成电路的老化过程的后续部分。

10. 发明申请

US20090080276A1 Temperature Dependent Bias for Minimal Stand-by Power in CMOS Circuits 审中-公开
标题翻译：用于CMOS电路中最小待机功率的温度偏置偏置
公开(公告)号：US20090080276A1
公开(公告)日：2009-03-26
申请号：US11859775
申请日：2007-09-23
申请人： Jin Cai , Randy William Mann , Harold Pilo
发明人： Jin Cai , Randy William Mann , Harold Pilo
IPC分类号： G05F1/567 , G11C7/04 , H03K17/16
CPC分类号： H03K19/0016 , H03K19/00369
摘要： A circuit is disclosed which generates such a bias voltage that when this bias voltage is received by a large plurality of devices of a semiconductor chip, power consumption is reduced in the stand-by mode at any particular operating temperature. The disclosed circuit contains at least one monitor FET, which is kept in its off-state, and which has common properties with the large plurality of FET devices. The temperature dependent leakage current of the monitor FET is sensed, and used to generate the bias voltage in proportion to the leakage current. This bias voltage is received by the large plurality FET devices on their gate electrodes, or on their body terminals.
摘要翻译：公开了一种产生这种偏置电压的电路，当偏置电压由半导体芯片的大量多个器件接收时，在待机模式下，在任何特定的工作温度下都会降低功耗。所公开的电路包括至少一个监控FET，其保持在其截止状态，并且与大量多个FET器件具有共同的特性。检测监控FET的温度依赖性漏电流，并用于产生与泄漏电流成正比的偏置电压。该偏置电压由大型多个FET器件在其栅极电极或其主体端子上接收。

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