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1. 发明授权

US06546439B1 Method and system for improved data access 有权
标题翻译：改进数据访问的方法和系统
公开(公告)号：US06546439B1
公开(公告)日：2003-04-08
申请号：US09207970
申请日：1998-12-09
申请人： Geoffrey S. Strongin , Qadeer A. Qureshi
发明人： Geoffrey S. Strongin , Qadeer A. Qureshi
IPC分类号： G06F1200
CPC分类号： G06T1/60
摘要： A method and system which will increase the ability of memory controllers to intelligently schedule accesses to system memory. The method and system provide a memory controller and a requested memory operation buffer structured so that at least one source attribute of a requested memory operation can be identified. In one instance, the requested memory operation buffer has queues, associated with data buses, which can be utilized to identify source attributes of requested memory operations. Examples of such queues are an Accelerated Graphics Port Interconnect queue associated with an Accelerated Graphics Port interconnect, a system bus queue associated with a system bus, and a Peripheral Component Interconnect bus queue associated with a Peripheral Component Interconnect bus where the queues can be utilized by a memory controller to identify the specific bus from which a requested memory operation originated. In another instance, the queues, associated with data buses, are structured such that one or more further source attributes—such as the identity of the request initiator, the priority of the request, whether the request is speculative, etcetera—of particular queued requested memory operations can be identified. In yet another instance, the requested memory operation buffer is structured such that one or more source attributes—such as the identity of the request initiator, the priority of the request, whether the request is speculative, etcetera—of particular queued requested memory operations can be identified.
摘要翻译：一种将增加存储器控制器智能调度对系统存储器访问的能力的方法和系统。所述方法和系统提供存储器控制器和被请求的存储器操作缓冲器，其被构造为使得可以识别所请求的存储器操作的至少一个源属性。在一个实例中，所请求的存储器操作缓冲器具有与数据总线相关联的队列，其可用于识别请求的存储器操作的源属性。这样的队列的示例是与加速图形端口互连相关联的加速图形端口互连队列，与系统总线相关联的系统总线队列以及与外围组件互连总线相关联的外围组件互连总线队列，其中队列可以由存储器控制器，用于识别发起请求的存储器操作的特定总线。在另一种情况下，与数据总线相关联的队列被构造成使得一个或多个另外的源属性（诸如请求发起者的身份，请求的优先级，请求是否是推测性的）等待特定排队请求可以识别内存操作。在另一个实例中，所请求的存储器操作缓冲器被构造成使得一个或多个源属性（诸如请求发起者的身份，请求的优先级，请求是否是推测性的）等特定排队请求的存储器操作可以被确定。

2. 发明授权

US06260123B1 Method and system for memory control and access in data processing systems 失效
标题翻译：数据处理系统中存储器控制和访问的方法和系统
公开(公告)号：US06260123B1
公开(公告)日：2001-07-10
申请号：US09208570
申请日：1998-12-09
申请人： Geoffrey S. Strongin , Qadeer A. Qureshi
发明人： Geoffrey S. Strongin , Qadeer A. Qureshi
IPC分类号： G06F1200
CPC分类号： G06F12/0215
摘要： It has been discovered that a method and system can be produced which will, among other things, provide data processing systems having memory controllers with the ability to look ahead and intelligently schedule accesses to system memory. A method and system which improve data processing system memory access. The method and system provide a first-stage origin-sensitive memory access request reordering device, and a second-stage destination-sensitive memory access request reordering device operably coupled to said first-stage origin-sensitive memory access request reordering device. The first-stage origin-sensitive memory access request reordering device receives memory access requests having associated origin information, and reorders the memory access requests based upon the associated origin information. The first-stage origin-sensitive memory access request reordering device delivers to the second-stage destination-sensitive memory access request reordering device one or more memory access requests which the first-stage origin-sensitive memory access request reordering device has deemed to be the requests which should be next executed. The second-stage destination-sensitive memory access request reordering device receives such one or more reordered memory access requests from the first stage and, in conjunction with the state of various system memory devices, again reorders the requests on the basis of the state of various system memory devices, prior to executing the one or more requests.
摘要翻译：已经发现，可以产生一种方法和系统，其将特别提供具有存储器控制器的数据处理系统，该存储器控制器具有前瞻性和智能地调度对系统存储器的访问的能力。改进数据处理系统存储器访问的方法和系统。该方法和系统提供第一级原始敏感存储器访问请求重排序设备，以及可操作地耦合到所述第一级原点敏感存储器访问请求重排序设备的第二级目的地敏感存储器访问请求重排序设备。第一级原始敏感存储器访问请求重新排序装置接收具有相关联的原始信息的存储器访问请求，并且基于相关联的原始信息重新排序存储器访问请求。第一级原始敏感存储器访问请求重排序设备向第二级目的地敏感存储器访问请求重新排序设备传递一个或多个存储器访问请求，其中第一级原始敏感存储器访问请求重新排序设备被认为是下次执行的请求第二级目的地敏感存储器访问请求重新排序装置从第一级接收这样的一个或多个重新排序的存储器访问请求，并且结合各种系统存储器设备的状态，再次根据各种状态的状态重新排序请求系统存储器设备，在执行一个或多个请求之前。

3. 发明授权

US06510497B1 Method and system for page-state sensitive memory control and access in data processing systems 有权
标题翻译：数据处理系统中页面状态敏感内存控制和访问的方法和系统
公开(公告)号：US06510497B1
公开(公告)日：2003-01-21
申请号：US09207971
申请日：1998-12-09
申请人： Geoffrey S. Strongin , Qadeer A. Qureshi
发明人： Geoffrey S. Strongin , Qadeer A. Qureshi
IPC分类号： G06F1200
CPC分类号： G06F12/0215 , G06F13/1626
摘要： A method and system which will provide data processing systems having memory controllers with the ability to intelligently schedule accesses to system memory. The method and system provide a memory controller having a page-state sensitive memory arbiter. The method and system further include one or more memory state tracking units operably coupled to the page-state sensitive memory arbiter, and the one or more memory state tracking units operably coupled to a system memory. The one or more memory state tracking units operably coupled to a system memory further include the one or more memory state tracking units operably coupled to one or more system memory devices. The method and system track system memory status, monitor pending memory access requests, and schedule one or more pending memory access requests for execution dependent upon the system memory status and the pending memory access requests.
摘要翻译：一种方法和系统，其将提供具有能够智能调度对系统存储器的访问的能力的具有存储器控制器的数据处理系统。该方法和系统提供具有页状态敏感存储器仲裁器的存储器控制器。该方法和系统还包括可操作地耦合到页状态敏感存储器仲裁器的一个或多个存储器状态跟踪单元，以及可操作地耦合到系统存储器的一个或多个存储器状态跟踪单元。可操作地耦合到系统存储器的一个或多个存储器状态跟踪单元还包括可操作地耦合到一个或多个系统存储器件的一个或多个存储器状态跟踪单元。所述方法和系统跟踪系统存储器状态，监视未决的存储器访问请求，并根据系统存储器状态和未决的存储器访问请求调度一个或多个待执行的待执行存储器访问请求以进行执行。

4. 发明授权

US06381683B1 Method and system for destination-sensitive memory control and access in data processing systems 失效
标题翻译：数据处理系统中目标敏感内存控制和访问的方法和系统
公开(公告)号：US06381683B1
公开(公告)日：2002-04-30
申请号：US09208522
申请日：1998-12-09
申请人： Geoffrey S. Strongin , Qadeer A. Qureshi
发明人： Geoffrey S. Strongin , Qadeer A. Qureshi
IPC分类号： G06F1200
CPC分类号： G06F12/0215
摘要： A method and system providing a memory controller having a destination-sensitive memory request reordering device. The destination-sensitive memory request reordering device includes a centralized state machine operably connected to one or more memory devices and one or more reorder and bank select engines. The centralized state machine is structured such that control information can be received from at least one of the one or more reorder and bank select engines over the one or more control lines. The centralized state machine is structured such that memory status information can be received from at least one of the one or more reorder and bank select engines over the one or more memory status lines, or such that memory status information can be determined by tracking past memory related activity. Additionally, the centralized state machine is structured to accept memory access requests having associated origin information. The centralized state machine executes the memory access requests based upon the associated origin information and the memory status information. Other embodiments function analogously, with the addition that the centralized state machine incorporates one or more device arbiter and state engines which function as autonomous units generally dedicated to one specific system memory device. The device arbiter and state engines receive identical inputs as discussed for the centralized state machine, except that typically each device arbiter and state engine is dedicated to one particular memory device, and thus generally receives memory status from the memory device with which it is associated via its dedicated memory status line.
摘要翻译：一种提供具有目的地敏感存储器请求重新排序装置的存储器控制器的方法和系统。目的地敏感存储器请求重排序设备包括可操作地连接到一个或多个存储器设备和一个或多个重新排序和存储体选择引擎的集中式状态机。集中式状态机的结构使得可以通过一个或多个控制线路从一个或多个重新排序和分组选择引擎中的至少一个接收控制信息。集中式状态机被构造成使得可以通过一个或多个存储器状态行从一个或多个重新排序和存储体选择引擎中的至少一个接收存储器状态信息，或者可以通过跟踪过去的存储器来确定存储器状态信息相关活动。此外，集中式状态机被构造为接受具有相关联的原始信息的存储器访问请求。集中式状态机基于相关联的原始信息和存储器状态信息来执行存储器访问请求。其他实施例类似地起作用，另外，集中式状态机包括一个或多个设备仲裁器和状态引擎，其作为一般专用于一个特定系统存储器设备的自主单元。设备仲裁器和状态引擎接收与集中式状态机所讨论的相同的输入，除了通常每个设备仲裁器和状态引擎都专用于一个特定的存储设备，因此通常从与其相关联的存储器设备中接收存储器状态其专用内存状态行。

5. 发明授权

US06226721B1 Method and system for generating and utilizing speculative memory access requests in data processing systems 有权
标题翻译：用于在数据处理系统中生成和利用推测性存储器访问请求的方法和系统
公开(公告)号：US06226721B1
公开(公告)日：2001-05-01
申请号：US09208569
申请日：1998-12-09
申请人： Geoffrey S. Strongin , Qadeer A. Qureshi
发明人： Geoffrey S. Strongin , Qadeer A. Qureshi
IPC分类号： G06F1318
CPC分类号： G06F13/1626
摘要： A method and system for generating and utilizing speculative memory accesses in data processing systems. The method and system provide a memory controller having at least one origin-sensitive speculative memory access request generator. The origin-sensitive speculative memory access request generator is associated with one or more origins of memory access requests. In some embodiments, the origins are buses over which the one or more memory access request travel; in other embodiments the origins are sources of the one or more memory access requests. The origin-sensitive speculative memory access request generator monitors reorder buffers associated with the one or more origins, and in response to space in the reorder buffers generates speculative memory access requests of a type likely to be received by the reorder buffers in the future. The generated origin-related speculative memory access requests are received by a speculative memory access request response buffer checking-and-logic-control unit associated with system memory. The speculative memory access request response buffer checking-and-logic-control unit associated with system memory examines the state of system memory, and, if appropriate, executes some or all of the speculative memory access requests. Subsequent to execution, the responses to the speculative memory access requests are stored in a speculative memory access request response buffer, and thereafter such results are utilized to satisfy non-speculative requests subsequently received.
摘要翻译：一种用于在数据处理系统中生成和利用推测存储器访问的方法和系统。该方法和系统提供具有至少一个原点敏感推测存储器访问请求生成器的存储器控制器。原点敏感的推测存储器访问请求生成器与存储器访问请求的一个或多个来源相关联。在一些实施例中，起点是一个或多个存储器访问请求行进的总线; 在其他实施例中，起点是一个或多个存储器访问请求的源。原点敏感推测存储器访问请求生成器监视与一个或多个源相关联的重新排序缓冲器，并且响应于重新排序缓冲器中的空间，将生成可能由重新排序缓冲器接收的类型的推测存储器访问请求。生成的与源相关的推测存储器访问请求由与系统存储器相关联的推测存储器访问请求响应缓冲器检查和逻辑控制单元接收。与系统存储器相关联的推测存储器访问请求响应缓冲器检查和逻辑控制单元检查系统存储器的状态，并且如果合适，执行部分或全部推测性存储器访问请求。在执行之后，对推测存储器访问请求的响应被存储在推测存储器访问请求响应缓冲器中，此后，这些结果被用于满足随后接收的非推测性请求。

6. 发明授权

US06559850B1 Method and system for improved memory access in accelerated graphics port systems 失效
标题翻译：加速图形端口系统中改进内存访问的方法和系统
公开(公告)号：US06559850B1
公开(公告)日：2003-05-06
申请号：US09183205
申请日：1998-10-30
申请人： Geoffrey S. Strongin , Qadeer A. Qureshi
发明人： Geoffrey S. Strongin , Qadeer A. Qureshi
IPC分类号： G06F1314
CPC分类号： G06F13/1626 , G09G5/363 , G09G5/39
摘要： A method and system for improving memory access in Accelerated Graphics Port systems. The method and system associate a transaction id with individual data transactions within a number of Accelerated Graphics Port (AGP) pipelined data transactions, and identify the individual data transactions within the number of AGP pipelined data transactions via the transaction id. In one instance, the association of a transaction id with individual data transactions includes but is not limited to associating a transaction id with each individual memory read request within a number of AGP pipelined memory read requests and associating an identical transaction id with each individual data unit, within a number of pipelined data units, corresponding to each individual memory read request within the number of AGP pipelined memory requests. In another instance, the association of a transaction id with individual memory read requests within a number of AGP pipelined memory read requests includes but is not limited to placing a transaction id on a Side Band Addressing bus substantially immediately after placing a read request on the same Side Band Addressing bus, and the association of an identical transaction id with individual data units within a number of the data units associated with pipelined data units corresponding to each of the AGP pipelined memory read requests includes but is not limited to placing a transaction id on a ST[2::0] bus while substantially simultaneously placing a data unit on an AGP Interconnect.
摘要翻译：一种用于改进加速图形端口系统中的存储器访问的方法和系统。该方法和系统将事务ID与多个加速图形端口（AGP）流水线数据事务中的各个数据事务相关联，并通过事务标识识别AGP流水线数据事务数量内的各个数据事务。在一个实例中，事务id与各个数据事务的关联包括但不限于在多个AGP流水线存储器读取请求中将事务ID与每个单独的存储器读取请求相关联，并且将相同的事务ID与每个单独的数据单元相关联在多个流水线数据单元内，对应于AGP流水线存储器请求数量内的每个单独的存储器读取请求。在另一个实例中，事务ID与多个AGP流水线存储器读取请求中的各个存储器读取请求的关联包括但不限于在将读取请求放在同一边缘上之后立即在边带寻址总线上放置事务ID 边带寻址总线，以及与相应于每个AGP流水线存储器读取请求的流水线数据单元相关联的数量的数据单元中的相同事务ID与各个数据单元的关联包括但不限于将事务ID放在 ST [2 :: 0]总线，同时将数据单元同时放置在AGP互连上。

7. 发明授权

US06219769B1 Method and system for origin-sensitive memory control and access in data processing systems 有权
标题翻译：数据处理系统中原点敏感存储器控制和访问的方法和系统
公开(公告)号：US06219769B1
公开(公告)日：2001-04-17
申请号：US09208305
申请日：1998-12-09
申请人： Geoffrey S. Strongin , Qadeer A. Qureshi
发明人： Geoffrey S. Strongin , Qadeer A. Qureshi
IPC分类号： G06F1318
CPC分类号： G06F13/1626
摘要： A method and system which improve data processing system memory access. The method and system provide a memory controller having an origin-sensitive memory request reordering device. The origin-sensitive memory request reordering device includes one or more reorder and bank select engines, with at least one of such reorder and bank select engines associated with at least one origin of one or more memory access requests. In one embodiment, the origin of the memory access request is a bus (bus over which one or more memory access requests travel); in another embodiment the origin is a source. The reorder buffers are structured such that the reorder buffers can receive origin information related to specific memory access requests, where such information can include the identity of a source of a specific request, and various attributes of the specific request, such as the priority of the source associated with the request, an ordinal number of the request, the nature of the request, etc. The reorder and bank select engines reorder the requests on the basis of origin and/or origin information related to specific memory access requests in order to present the memory access requests in an efficient memory utilization fashion. In another embodiment, best choice registers communicate with the reorder and bank select engines and select from the reorder buffers the operations which should be next executed in addition to, or in the alternative of, reordering the requests in the reorder buffers.
摘要翻译：改进数据处理系统存储器访问的方法和系统。该方法和系统提供具有原点敏感存储器请求重新排序装置的存储器控制器。原点敏感存储器请求重新排序装置包括一个或多个重新排序和库选择引擎，其中至少一个这样的重新排序和存储体选择引擎与一个或多个存储器访问请求的至少一个来源相关联。在一个实施例中，存储器访问请求的来源是总线（一个或多个存储器访问请求行进的总线）; 在另一个实施例中，起点是源。重排序缓冲器被构造成使得重排序缓冲器可以接收与特定存储器访问请求相关的原始信息，其中这样的信息可以包括特定请求的来源的身份以及特定请求的各种属性，诸如与请求相关联的源，请求的序号，请求的性质等。重新排序和银行选择引擎基于与特定存储器访问请求相关的原始和/或原始信息来重新排序请求，以便呈现存储器访问请求以有效的存储器利用方式。在另一个实施例中，最佳选择寄存器与重新排序和存储库选择引擎进行通信，并且从重新排序缓冲器中选择除了重新排序重排序缓冲器中的请求之外还是替代地，下一步执行的操作。

8. 发明授权

US07362645B2 Integrated circuit fuses having corresponding storage circuitry 有权
标题翻译：集成电路保险丝具有相应的存储电路
公开(公告)号：US07362645B2
公开(公告)日：2008-04-22
申请号：US10955356
申请日：2004-09-30
申请人： Qadeer A. Qureshi , John J. Vaglica , William C. Moyer , Ryan D. Bedwell
发明人： Qadeer A. Qureshi , John J. Vaglica , William C. Moyer , Ryan D. Bedwell
IPC分类号： G11C17/18 , G11C17/00 , G11C7/10 , G11C7/00
CPC分类号： G11C17/18
摘要： Storage circuitry (66) may be used to store the values of fuses (77) so that storage circuitry (66) can be read instead of fuses (77). By accessing the fuse values from storage circuitry (66) rather than from fuses (77), there will be no sense current to fuses (77) that may cause marginal fuse blowage for fuses that have not yet been blown. This helps to prevent the situation in which an unblown fuse is erroneously read as having been blown. The use of storage circuitry (66) thus significantly improves the reliability of fuse module (20). For some embodiments, selection storage circuitry (64) may be used to determine whether storage circuitry (66) may be read or whether one of fuses (77) must be read in order to retrieve the desired current fuse value. The fuse value stored in storage circuitry (66) can also be used as direct hardware signals (80).
摘要翻译：存储电路（66）可以用于存储熔丝（77）的值，使得可以读取存储电路（66）而不是保险丝（77）。通过从存储电路（66）而不是保险丝（77）访问熔丝值，对熔断器（77）将没有感应电流可能导致尚未熔断的熔断器的边缘熔断器。这有助于防止未熔断的保险丝被错误地读取为已被吹灭的情况。因此，存储电路（66）的使用显着地提高了熔丝模块（20）的可靠性。对于一些实施例，可以使用选择存储电路（64）来确定是否可以读取存储电路（66），或者是否必须读取保险丝（77）之一以便检索所需的当前熔丝值。存储在存储电路（66）中的熔丝值也可以用作直接硬件信号（80）。

9. 发明授权

US07295484B2 Temperature based DRAM refresh 有权
公开(公告)号：US07295484B2
公开(公告)日：2007-11-13
申请号：US11685419
申请日：2007-03-13
申请人： Arnaldo R. Cruz , Qadeer A. Qureshi
发明人： Arnaldo R. Cruz , Qadeer A. Qureshi
IPC分类号： G11C7/00 , G11C7/04 , G11C5/06
CPC分类号： G11C11/406 , G11C11/40626
摘要： A system for controlling the refresh cycles of a DRAM cell array based upon a temperature measurement. During active mode, a refresh request indication based on a measured temperature is provided to a DRAM controller (e.g. of another integrated circuit die), wherein the DRAM controller initiates a refresh cycle of the DRAM cell array in response thereto. In a self refreshing mode, the DRAM controller does not initiate refresh cycles, but refresh cycles are performed by a controller on the integrated circuit die of the array based upon a temperature measurement.

10. 发明授权

US09384856B2 Memories having a built-in self-test (BIST) feature 有权
标题翻译：具有内置自检（BIST）功能的记忆体
公开(公告)号：US09384856B2
公开(公告)日：2016-07-05
申请号：US14102727
申请日：2013-12-11
申请人： Henning F. Spruth , Qadeer A. Qureshi , Reinaldo Silveira
发明人： Henning F. Spruth , Qadeer A. Qureshi , Reinaldo Silveira
IPC分类号： G11C29/00 , G11C29/38 , G06F11/263 , G11C29/42 , G11C29/44
CPC分类号： G11C29/38 , G06F11/263 , G11C29/42 , G11C29/44 , G11C2029/4402
摘要： A memory system includes a memory and a built-in self-test (BIST) unit coupled to the memory. The BIST unit is configured to run a test pattern on the memory to accumulate a fault signature, and store fault signature information based on the accumulated fault signature at multiple locations in the memory.
摘要翻译：存储器系统包括存储器和耦合到存储器的内置自检（BIST）单元。 BIST单元被配置为在存储器上运行测试模式以累积故障签名，并且基于存储器中的多个位置处的累积故障签名来存储故障签名信息。

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