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1. 发明授权

US6081569A Method and apparatus for determining the change in frequency of a reference signal 失效
标题翻译：用于确定参考信号的频率变化的方法和装置
公开(公告)号：US6081569A
公开(公告)日：2000-06-27
申请号：US613434
申请日：1996-02-29
申请人： Gary D. Hanson , Ioan V. Teodorescu
发明人： Gary D. Hanson , Ioan V. Teodorescu
IPC分类号： G01R23/10 , H03D13/00 , H03L7/07 , H04J3/06 , H04L7/04
CPC分类号： H03D13/002 , G01R23/10 , H03L7/07 , H04J3/0685
摘要： A method for determining the change in frequency of a clock signal (168). The method includes the step of counting the number of clock signal cycles (168) that occur over at least two time windows (162, 164). The number of clock signal cycles counted in the first time window (162) is compared to the number of clock signal cycles counted in the second time window (164).
摘要翻译：一种用于确定时钟信号（168）的频率变化的方法。该方法包括对在至少两个时间窗口（162,164）上发生的时钟信号周期（168）的数目进行计数的步骤。将在第一时间窗口（162）中计数的时钟信号周期的数量与在第二时间窗口中计数的时钟信号周期数（164）进行比较。

2. 发明授权

US5748569A Apparatus and method for clock alignment and switching 失效
标题翻译：用于时钟对准和切换的装置和方法
公开(公告)号：US5748569A
公开(公告)日：1998-05-05
申请号：US769370
申请日：1996-12-19
申请人： Ioan V. Teodorescu , Anthony Mazzurco
发明人： Ioan V. Teodorescu , Anthony Mazzurco
IPC分类号： H04J3/06 , G04F8/00 , H04L7/00
CPC分类号： H04J3/0688
摘要： In a telecommunication system having multiple timing subsystems receiving and distributing redundant timing signals, there is provided a circuitry (8, 100) for aligning first and second redundant timing signals (10, 12, 110, 112) and switching therebetween. The circuitry includes first and second phase-locked loops (18, 20, 118, 120) for receiving first and second redundant timing signals (10, 12, 110, 112), respectively, and multiplying the frequency of first and second redundant timing signals (10, 12, 110, 112) by a factor of N. The circuitry further includes a selecting and switching circuitry (34, 134) for receiving the multiplied first and second redundant timing signals (22, 23, 122, 124) and designating one as ACTIVE and the other as INACTIVE, and providing the ACTIVE timing signal as an output timing reference signal (54, 154). The selecting and switching circuitry further operating to switch the ACTIVE and INACTIVE timing signal designations and output timing reference signal in response to detecting a fault or a clock switching command. The ACTIVE timing signal is provided to a phase integrator (40, 140), which integrates phase transients out of the ACTIVE timing signal to avoid jitter in the output timing reference (54, 154).
摘要翻译：在具有接收和分配冗余定时信号的多个定时子系统的电信系统中，提供了用于对准第一和第二冗余定时信号（10,12,110,112）并在其间切换的电路（8,100）。电路包括用于分别接收第一和第二冗余定时信号（10,12,110,112）的第一和第二锁相环（18,20，118，120），并且将第一和第二冗余定时信号的频率相乘（10,12,110,112）。该电路还包括用于接收相乘的第一和第二冗余定时信号（22,23,122,124）的选择和切换电路（34,134），并指定一个作为ACTIVE，另一个作为INACTIVE，并且提供ACTIVE定时信号作为输出定时参考信号（54,154）。选择和切换电路进一步操作以响应于检测到故障或时钟切换命令来切换ACTIVE和INACTIVE定时信号指定并输出定时参考信号。 ACTIVE定时信号被提供给相位积分器（40,140），该相位积分器将相位瞬变集成在ACTIVE定时信号之外，以避免输出定时参考（54,154）中的抖动。

3. 发明授权

US4908819A Integrated data voice multiplexer supporting handshake and loop-back protocols 失效
标题翻译：集成数据语音复用器支持握手和回送协议
公开(公告)号：US4908819A
公开(公告)日：1990-03-13
申请号：US293531
申请日：1988-12-23
申请人： Donald R. Casady , Ioan V. Teodorescu
发明人： Donald R. Casady , Ioan V. Teodorescu
IPC分类号： H04M11/06
CPC分类号： H04M11/062
摘要： An integrated data voice multiplexer (IDVM) capable of simultaneously supporting loop-back and communication handshake protocols with no performance degradation. This allows the IDVM to be used in both point-to-point and packet switch networks. The IDVM is of the type using frequency shift keyed FSK modulation of two or more carriers to send a data signal. The presence or absence of carrier signals indicates loop-back state. Narrowband modulation is selectively added to at least one carrier to support handshake protocol. The preferred narrowband modulation is biphase at a rate lower than the FSK modulation rate. Encoder, decoder, data hold and detect circuits for supporting standard RS232 protocol are disclosed.
摘要翻译：能够同时支持环回和通信握手协议而不降低性能的集成数据语音多路复用器（IDVM）。这允许IDVM在点对点和分组交换网络中使用。 IDVM是使用两个或多个载波的频移键控FSK调制来发送数据信号的类型。载波信号的存在或不存在表示环回状态。选择性地将窄带调制添加到至少一个载波以支持握手协议。优选的窄带调制是以比FSK调制速率低的速率双相。公开了用于支持标准RS232协议的编码器，解码器，数据保持和检测电路。

4. 发明授权

US06909701B1 Method and system for distributing a timing signal 失效
标题翻译：用于分配定时信号的方法和系统
公开(公告)号：US06909701B1
公开(公告)日：2005-06-21
申请号：US09541387
申请日：2000-03-31
申请人： Ioan V. Teodorescu
发明人： Ioan V. Teodorescu
IPC分类号： H04J3/06 , H04Q11/00
CPC分类号： H04J3/0688 , H04Q2213/13213 , H04Q2213/13214 , H04Q2213/13299
摘要： A system for distributing a timing signal is disclosed. A timing generator inserts a phase of a timing signal and a command signal into a framed signal. A distribution module receives the framed signal from the timing generator. A bus control module receives the framed signal from the distribution module and distributes the framed signal to a telecommunication system. A method for distributing a timing signal in a telecommunication system is disclosed. A phase of a timing signal and a command signal is inserted into a framed signal using a timing generator. The framed signal is transmitted to a distribution module. The framed signal is transmitted to a bus control module. The framed signal is distributed to a telecommunication system using the bus control module.
摘要翻译：公开了一种用于分配定时信号的系统。定时发生器将定时信号和命令信号的相位插入成帧信号。分配模块从定时发生器接收成帧信号。总线控制模块从分配模块接收成帧信号，并将成帧信号分配给电信系统。公开了一种用于在电信系统中分配定时信号的方法。使用定时发生器将定时信号和指令信号的相位插入成帧信号。成帧信号被传送到分配模块。成帧信号被传送到总线控制模块。帧信号使用总线控制模块分配到电信系统。

5. 发明授权

US5835543A Digital desynchronizer 失效
标题翻译：数字去同步器
公开(公告)号：US5835543A
公开(公告)日：1998-11-10
申请号：US895143
申请日：1997-07-16
申请人： Anthony Mazzurco , Ioan V. Teodorescu , Stewart W. Shankel, III , Richard C. Witinski , Pavlina Ennghillis , Harry W. Hartjes
发明人： Anthony Mazzurco , Ioan V. Teodorescu , Stewart W. Shankel, III , Richard C. Witinski , Pavlina Ennghillis , Harry W. Hartjes
IPC分类号： H04J3/07 , H04L7/00
CPC分类号： H04J3/076
摘要： A digital desynchronizer device (10) includes an elastic store unit (12) that receives data in an asynchronous manner and synchronously transmits the data in response to a synchronization clock generated by a clock generator (14). The clock generator (14) operates off of a reference oscillator unit (16). The clock generator (14) generates the synchronization clock signal in response to pointer adjustments identified by a pointer movement unit (18). The clock generator (14) also generates the synchronization clock signal in response to mapping jitter identified by a mapping unit (20). The pointer movement unit (18) and the mapping unit (20) identify pointer adjustments and mapping jitter, respectively, independent of each other. The clock generator (14) adjusts a width of a specific pulse bit in response to pointer adjustments identified by the pointer movement unit (18). Clock generator (14) also adjusts a width of a specific bit position, separate from the pulse bit position used for pointer adjustments, in response to mapping jitter identified by the mapping unit (20).
摘要翻译：数字去同步装置（10）包括弹性存储单元（12），其以异步方式接收数据，并响应于由时钟发生器（14）产生的同步时钟同步发送数据。时钟发生器（14）工作在参考振荡器单元（16）之外。时钟发生器（14）响应于由指针移动单元（18）识别的指针调整产生同步时钟信号。响应由映射单元（20）识别的映射抖动，时钟发生器（14）还产生同步时钟信号。指针移动单元（18）和映射单元（20）分别独立地识别指针调整和映射抖动。时钟发生器（14）响应于由指针移动单元（18）识别的指针调整来调整特定脉冲位的宽度。响应于由映射单元（20）识别的映射抖动，时钟发生器（14）还调整与用于指针调整的脉冲位位置分离的特定位位置的宽度。

6. 发明授权

US06977926B1 Method and system for providing a feedback signal in a telecommunications network 有权
标题翻译：在电信网络中提供反馈信号的方法和系统
公开(公告)号：US06977926B1
公开(公告)日：2005-12-20
申请号：US09539405
申请日：2000-03-31
申请人： Ioan V. Teodorescu
发明人： Ioan V. Teodorescu
IPC分类号： H04J3/06 , H04Q3/00 , H04Q11/00
CPC分类号： H04J3/0685 , H04Q3/0029
摘要： A system for providing a feedback signal in a telecommunications network is provided that includes a plurality of bus control modules, a lower level distribution module, and a timing generator. The bus control modules are operable to generate a feedback signal. The lower level distribution module is coupled to the bus control modules. The lower level distribution module is operable to receive the feedback signal and to insert feedback information for the lower level distribution module into the feedback signal. The timing generator is coupled to the lower level distribution module. The timing generator is operable to receive the feedback signal and to provide the feedback signal to a controller for response.
摘要翻译：提供了一种用于在电信网络中提供反馈信号的系统，其包括多个总线控制模块，下层分配模块和定时发生器。总线控制模块可操作以产生反馈信号。下层分配模块耦合到总线控制模块。低级分配模块可操作以接收反馈信号并将反馈信息插入下级分配模块进入反馈信号。定时发生器耦合到下层分配模块。定时发生器可操作以接收反馈信号并将反馈信号提供给控制器以进行响应。

7. 发明授权

US06763016B1 Method and system for distributing a synchronization signal in a telecommunications network 失效
标题翻译：用于在电信网络中分发同步信号的方法和系统
公开(公告)号：US06763016B1
公开(公告)日：2004-07-13
申请号：US09539368
申请日：2000-03-31
申请人： Ioan V. Teodorescu
发明人： Ioan V. Teodorescu
IPC分类号： H04J306
CPC分类号： H04J3/0691 , H04Q11/04 , H04Q2213/13003 , H04Q2213/13213 , H04Q2213/13216 , H04Q2213/13299 , H04Q2213/13345 , H04Q2213/1336
摘要： A system for distributing a synchronization signal in a telecommunications network is provided that includes a timing generator, a lower level distribution module, a bus control module and a plurality of cards. The timing generator is operable to provide a synchronization signal comprising timing and control signals. The lower level distribution module is coupled to the timing generator. The lower level distribution module is operable to receive and distribute the synchronization signal. The bus control module is coupled to the lower level distribution module. The bus control module is operable to receive and distribute the synchronization signal. The plurality of cards are coupled to the bus control module. Each card is operable to receive the synchronization signal and to synchronize based on the timing signals.
摘要翻译：提供了一种用于在电信网络中分发同步信号的系统，其包括定时发生器，下位分配模块，总线控制模块和多个卡。定时发生器可操作以提供包括定时和控制信号的同步信号。下位分配模块耦合到定时发生器。较低级分配模块可操作以接收和分配同步信号。总线控制模块耦合到下层分配模块。总线控制模块可操作以接收和分配同步信号。多个卡耦合到总线控制模块。每个卡可操作以接收同步信号并且基于定时信号进行同步。

8. 发明授权

US06721896B1 System and method for converting a selected signal into a timing signal and inserting the phase of the timing signal into a framed signal 有权
标题翻译：将所选择的信号转换为定时信号并将定时信号的相位插入成帧信号的系统和方法
公开(公告)号：US06721896B1
公开(公告)日：2004-04-13
申请号：US09539362
申请日：2000-03-31
申请人： John H. Bond , Ioan V. Teodorescu
发明人： John H. Bond , Ioan V. Teodorescu
IPC分类号： G06F104
CPC分类号： H04J3/0685
摘要： A system for generating a timing signal is disclosed. A processor generates a selection command. A clock receives a signal selected in response to the selection command and converts the selected signal to a timing signal. A framing module inserts a phase of the timing signal into a framed signal. A method for generating a timing signal for a telecommunication system is disclosed. A selection command is generated using a processor. A signal is selected in response to the selection command. The selected signal is converted to a timing signal using a clock. A phase of the timing signal is inserted into a framed signal using a framing module.
摘要翻译：公开了一种用于产生定时信号的系统。处理器产生选择命令。时钟接收响应于选择命令选择的信号，并将所选择的信号转换为定时信号。成帧模块将定时信号的相位插入成帧信号。公开了一种用于产生电信系统的定时信号的方法。使用处理器生成选择命令。响应于选择命令选择信号。所选择的信号使用时钟转换为定时信号。使用成帧模块将定时信号的相位插入成帧信号。

9. 发明授权

US5699391A Digital desynchronizer 失效
标题翻译：数字去同步器
公开(公告)号：US5699391A
公开(公告)日：1997-12-16
申请号：US456235
申请日：1995-05-31
申请人： Anthony Mazzurco , Ioan V. Teodorescu , Stewart W. Shankel, III , Richard C. Witinski , Pavlina Ennghillis , Harry W. Hartjes
发明人： Anthony Mazzurco , Ioan V. Teodorescu , Stewart W. Shankel, III , Richard C. Witinski , Pavlina Ennghillis , Harry W. Hartjes
IPC分类号： H04J3/07 , H03D3/24
CPC分类号： H04J3/076
摘要： A digital desynchronizer device (10) includes an elastic store unit (12) that receives data in an asynchronous manner and synchronously transmits the data in response to a synchronization clock generated by a clock generator (14). The clock generator (14) operates off of a reference oscillator unit (16). The clock generator (14) generates the synchronization clock signal in response to pointer adjustments identified by a pointer movement unit (18). The clock generator (14) also generates the synchronization clock signal in response to mapping jitter identified by a mapping unit (20). The pointer movement unit (18) and the mapping unit (20) identify pointer adjustments and mapping jitter, respectively, independent of each other. The clock generator (14) adjusts a width of a specific pulse bit in response to pointer adjustments identified by the pointer movement unit (18). Clock generator (14) also adjusts a width of a specific bit position, separate from the pulse bit position used for pointer adjustments, in response to mapping jitter identified by the mapping unit (20).
摘要翻译：数字去同步装置（10）包括弹性存储单元（12），其以异步方式接收数据，并响应于由时钟发生器（14）生成的同步时钟同步发送数据。时钟发生器（14）工作在参考振荡器单元（16）之外。时钟发生器（14）响应于由指针移动单元（18）识别的指针调整产生同步时钟信号。响应由映射单元（20）识别的映射抖动，时钟发生器（14）还产生同步时钟信号。指针移动单元（18）和映射单元（20）分别独立地识别指针调整和映射抖动。时钟发生器（14）响应于由指针移动单元（18）识别的指针调整来调整特定脉冲位的宽度。响应于由映射单元（20）识别的映射抖动，时钟发生器（14）还调整与用于指针调整的脉冲位位置分开的特定位位置的宽度。

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