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1. 发明申请

US20180175180A1 BIPOLAR JUNCTION TRANSISTORS WITH A COMBINED VERTICAL-LATERAL ARCHITECTURE 审中-公开
公开(公告)号：US20180175180A1
公开(公告)日：2018-06-21
申请号：US15383171
申请日：2016-12-19
申请人： GLOBALFOUNDRIES Inc.
发明人： Vibhor Jain , Qizhi Liu , David L. Harame , Renata Camillo-Castillo
IPC分类号： H01L29/737 , H01L29/06 , H01L29/66 , H01L29/165 , H01L29/417 , H01L21/265 , H01L29/735 , H01L27/12
CPC分类号： H01L29/737 , H01L21/26513 , H01L27/1203 , H01L29/0653 , H01L29/165 , H01L29/41708 , H01L29/66242 , H01L29/735
摘要： Device structures and fabrication methods for a bipolar junction transistor. The device structure includes an intrinsic base, an emitter having a vertical arrangement relative to the intrinsic base, and a collector having a lateral arrangement relative to the intrinsic base. The device structure may be fabricated by forming the intrinsic base and the collector in a semiconductor layer, and epitaxially growing the emitter on the intrinsic base and with a vertical arrangement relative to the intrinsic base. The collector and the intrinsic base have a lateral arrangement within the semiconductor layer.

2. 发明申请

US20170098699A1 IMPLEMENTING STRESS IN A BIPOLAR JUNCTION TRANSISTOR 有权
公开(公告)号：US20170098699A1
公开(公告)日：2017-04-06
申请号：US14874039
申请日：2015-10-02
申请人： GLOBALFOUNDRIES INC.
发明人： Renata Camillo-Castillo , Qizhi Liu , Vibhor Jain , James W. Adkisson , David L. Harame
IPC分类号： H01L29/732 , H01L29/66 , H01L29/06 , H01L21/02 , H01L29/04 , H01L21/762 , H01L21/225
CPC分类号： H01L29/732 , H01L21/76 , H01L21/762 , H01L29/0642 , H01L29/0821 , H01L29/66242 , H01L29/66272 , H01L29/7371
摘要： Device structure and fabrication methods for a bipolar junction transistor. One or more trench isolation regions are formed in a substrate to define a device region having a first width. A protect layer is formed on a top surface of the one or more trench isolation regions and a top surface of the device region. An opening is formed in the protect layer. The opening is coincides with the top surface of the first device region and has a second width that is less than or equal to the first width of the first device region. A base layer is formed that has a first section on the device region inside the first opening and a second section on the protect layer.

3. 发明申请

US20160225917A1 FIELD EFFECT TRANSISTOR (FET) WITH SELF-ALIGNED DOUBLE GATES ON BULK SILICON SUBSTRATE, METHODS OF FORMING, AND RELATED DESIGN STRUCTURES 审中-公开
公开(公告)号：US20160225917A1
公开(公告)日：2016-08-04
申请号：US15092976
申请日：2016-04-07
申请人： GLOBALFOUNDRIES Inc.
发明人： James W. Adkisson , James S. Dunn , Blaine J. Gross , David L. Harame , Qizhi Liu , John J. Pekarik
IPC分类号： H01L29/808 , G06F17/50 , H01L29/161 , H01L29/06 , H01L29/47
CPC分类号： H01L29/808 , G06F17/5045 , G06F17/505 , G06F17/5072 , H01L21/28026 , H01L21/306 , H01L21/8232 , H01L29/0657 , H01L29/161 , H01L29/47 , H01L29/475 , H01L29/66901 , H01L29/66924 , H01L29/7782 , H01L29/8124
摘要： At least one isolation trench formed in a layer stack including substrate, channel, and upper gate layers define a channel in the channel layer. Lateral etching from the isolation trench(es) can form lateral cavities in the substrate and upper gate layer to substantially simultaneously form self-aligned lower and upper gates. The lower gate undercuts the channel, the upper gate is narrower than the channel, and a source and a drain can be formed on opposed ends of the channel. As a result, source-drain capacitance and gate-drain capacitance can be reduced, increasing speed of the resulting FET.

4. 发明授权

US09349845B2 Self-aligned bipolar junction transistors 有权
标题翻译：自对准双极结型晶体管
公开(公告)号：US09349845B2
公开(公告)日：2016-05-24
申请号：US14495057
申请日：2014-09-24
申请人： GLOBALFOUNDRIES INC.
发明人： David L. Harame , Qizhi Liu
IPC分类号： H01L29/66 , H01L29/735 , H01L29/732 , H01L29/06 , H01L29/10 , H01L27/082 , H01L29/73 , G06F17/50
CPC分类号： H01L29/735 , G06F17/5045 , H01L27/0823 , H01L29/0649 , H01L29/1004 , H01L29/1008 , H01L29/66234 , H01L29/66272 , H01L29/73 , H01L29/732
摘要： Device structures and design structures for a bipolar junction transistor. An intrinsic base is formed on the substrate, a terminal is formed on the intrinsic base, and an extrinsic base is formed that is arranged in juxtaposition with the intrinsic base on the substrate. The intrinsic base and terminal are respectively comprised of first and second semiconductor materials.
摘要翻译：双极结型晶体管的器件结构和设计结构。在基板上形成本征基底，在本征基底上形成端子，并且形成与本征基底并列布置在基底上的非本征基底。本征基极和端子分别由第一和第二半导体材料构成。

5. 发明授权

US09312370B2 Bipolar transistor with extrinsic base region and methods of fabrication 有权
标题翻译：具有外在基极区域的双极晶体管及其制造方法
公开(公告)号：US09312370B2
公开(公告)日：2016-04-12
申请号：US14300944
申请日：2014-06-10
申请人： GLOBALFOUNDRIES INC.
发明人： James W. Adkisson , David L. Harame , Michael L. Kerbaugh , Qizhi Liu , John J. Pekarik
IPC分类号： H01L29/73 , H01L29/732 , H01L29/66 , H01L29/10
CPC分类号： H01L29/732 , H01L29/04 , H01L29/0649 , H01L29/0657 , H01L29/0804 , H01L29/0821 , H01L29/0826 , H01L29/1004 , H01L29/161 , H01L29/45 , H01L29/456 , H01L29/66242 , H01L29/66287 , H01L29/7327 , H01L29/7371 , H01L29/7378
摘要： The present disclosure relates to integrated circuit (IC) structures and methods of forming the same. An IC structure according to the present disclosure can include: a doped substrate region adjacent to an insulating region; a crystalline base structure including: an intrinsic base region located on and contacting the doped substrate region, the intrinsic base region having a first thickness; an extrinsic base region adjacent to the insulating region, wherein the extrinsic base region has a second thickness greater than the first thickness; a semiconductor layer located on the intrinsic base region of the crystalline base structure; and a doped semiconductor layer located on the semiconductor layer.
摘要翻译：本公开涉及集成电路（IC）结构及其形成方法。根据本公开的IC结构可以包括：与绝缘区域相邻的掺杂衬底区域; 晶体基底结构，其包括：位于掺杂衬底区域上并与其接触的本征基极区域，本征基极区域具有第一厚度; 与所述绝缘区域相邻的外部基极区域，其中所述非本征基极区域具有大于所述第一厚度的第二厚度; 位于所述晶体基底结构的本征基极区上的半导体层; 以及位于半导体层上的掺杂半导体层。

6. 发明授权

US09245951B1 Profile control over a collector of a bipolar junction transistor 有权
标题翻译：对双极结型晶体管的集电极进行剖面控制
公开(公告)号：US09245951B1
公开(公告)日：2016-01-26
申请号：US14487582
申请日：2014-09-16
申请人： GLOBALFOUNDRIES INC.
发明人： Renata Camillo-Castillo , David L. Harame , Vibhor Jain , Vikas K. Kaushal , Marwan H. Khater
IPC分类号： H01L21/331 , H01L29/08 , H01L29/732 , H01L29/66 , H01L29/10
CPC分类号： H01L29/0826 , H01L21/31056 , H01L21/31111 , H01L21/31144 , H01L29/0804 , H01L29/0821 , H01L29/1004 , H01L29/66234 , H01L29/66242 , H01L29/66272 , H01L29/732 , H01L29/7325 , H01L29/7378
摘要： Device structures and fabrication methods for a bipolar junction transistor. A layer is formed on a top surface of a substrate. A trench is formed in the layer and has a plurality of sidewalls with a width between an opposite pair of the sidewalls that varies with increasing distance from the top surface of the substrate. A collector pedestal of the bipolar junction transistor is formed in the trench.
摘要翻译：双极结型晶体管的器件结构和制造方法。在衬底的顶表面上形成一层。在该层中形成沟槽并且具有多个侧壁，其宽度在相对的一对侧壁之间的宽度随着距离衬底顶表面的距离的增加而变化。在沟槽中形成双极结型晶体管的集电极基座。

7. 发明申请

US20160064484A1 LATERAL BIPOLAR JUNCTION TRANSISTORS ON A SILICON-ON-INSULATOR SUBSTRATE WITH A THIN DEVICE LAYER THICKNESS 有权
标题翻译：具有薄膜厚度的绝缘子硅衬底上的侧向双极晶体管
公开(公告)号：US20160064484A1
公开(公告)日：2016-03-03
申请号：US14476007
申请日：2014-09-03
申请人： GLOBALFOUNDRIES INC.
发明人： David L. Harame , Michael L. Kerbaugh , Qizhi Liu
IPC分类号： H01L29/10 , H01L29/08 , H01L27/12 , H01L21/84 , H01L29/66 , H01L29/732
CPC分类号： H01L29/1004 , H01L21/84 , H01L27/12 , H01L29/0821 , H01L29/41708 , H01L29/66272 , H01L29/732
摘要： Methods of forming bipolar device structures and bipolar device structures. An opening may be formed in a device layer of a silicon-on-insulator substrate that extends to a buried insulator layer of the silicon-on-insulator substrate. An intrinsic base layer may be grown within the device layer opening by lateral growth on opposite first and second sidewalls of the device layer bordering the opening. A first collector of a first bipolar junction transistor of the device structure may be formed at a first spacing from the first sidewall. A second collector of a second bipolar junction transistor of the device structure may be formed at a second spacing from the second sidewall. An emitter, which is shared by the first bipolar junction transistor and the second bipolar transistor, is formed inside the opening. Portions of the intrinsic base layer may supply respective intrinsic bases for the first and second bipolar junction transistors.
摘要翻译：形成双极器件结构和双极器件结构的方法。可以在绝缘体上硅衬底的器件层中形成开口，该器件层延伸到绝缘体上硅衬底的掩埋绝缘体层。内部基极层可以通过在与开口相邻的器件层的相对的第一和第二侧壁上的横向生长而在器件层内生长。器件结构的第一双极结型晶体管的第一集电极可以以与第一侧壁隔开的第一间隔形成。器件结构的第二双极结晶体管的第二集电极可以形成在距离第二侧壁的第二间隔处。在开口内形成由第一双极结型晶体管和第二双极晶体管共用的发射极。本征基极层的一部分可以为第一和第二双极结型晶体管提供相应的本征基极。

8. 发明授权

US09608096B1 Implementing stress in a bipolar junction transistor 有权
公开(公告)号：US09608096B1
公开(公告)日：2017-03-28
申请号：US14874039
申请日：2015-10-02
申请人： GLOBALFOUNDRIES INC.
发明人： Renata Camillo-Castillo , Qizhi Liu , Vibhor Jain , James W. Adkisson , David L. Harame
IPC分类号： H01L29/49 , H01L29/732 , H01L21/762 , H01L29/66 , H01L21/225 , H01L21/02 , H01L29/04 , H01L29/06
CPC分类号： H01L29/732 , H01L21/76 , H01L21/762 , H01L29/0642 , H01L29/0821 , H01L29/66242 , H01L29/66272 , H01L29/7371
摘要： Device structure and fabrication methods for a bipolar junction transistor. One or more trench isolation regions are formed in a substrate to define a device region having a first width. A protect layer is formed on a top surface of the one or more trench isolation regions and a top surface of the device region. An opening is formed in the protect layer. The opening is coincides with the top surface of the first device region and has a second width that is less than or equal to the first width of the first device region. A base layer is formed that has a first section on the device region inside the first opening and a second section on the protect layer.

9. 发明授权

US09570564B2 Self-aligned emitter-base bipolar junction transistor with reduced base resistance and base-collector capacitance 有权
标题翻译：具有降低的基极电阻和基极集电极电容的自对准发射极 - 基极双极结型晶体管
公开(公告)号：US09570564B2
公开(公告)日：2017-02-14
申请号：US14451716
申请日：2014-08-05
申请人： GLOBALFOUNDRIES INC.
发明人： Deborah A. Alperstein , David L. Harame , Alvin J. Joseph , Qizhi Liu , Keith J. Machia , Christa R. Willets
IPC分类号： H01L29/66 , H01L29/417 , H01L29/732 , H01L29/08 , H01L29/10 , H01L29/423 , H01L29/737
CPC分类号： H01L29/41708 , H01L29/0821 , H01L29/0826 , H01L29/1004 , H01L29/42304 , H01L29/66242 , H01L29/66272 , H01L29/732 , H01L29/7371
摘要： Device structures and fabrication methods for a bipolar junction transistor. A first semiconductor layer is formed on a substrate containing a first terminal. An etch stop layer is formed on the first semiconductor layer, and a second semiconductor layer is formed on the etch stop layer. The second semiconductor layer is etched to define a second terminal at a location of an etch mask on the second semiconductor layer. A first material comprising the etch stop layer and a second material comprising the second semiconductor layer are selected such that the second material of the second semiconductor layer etches at a greater etch rate than the first material of the etch stop layer. The first semiconductor layer may be a base layer that is used to form an intrinsic base and an extrinsic base of the bipolar junction transistor.
摘要翻译：双极结型晶体管的器件结构和制造方法。在包含第一端子的基板上形成第一半导体层。在第一半导体层上形成蚀刻停止层，在蚀刻停止层上形成第二半导体层。蚀刻第二半导体层以在第二半导体层上的蚀刻掩模的位置处限定第二端子。选择包括蚀刻停止层的第一材料和包括第二半导体层的第二材料，使得第二半导体层的第二材料以比蚀刻停止层的第一材料更高的蚀刻速率蚀刻。第一半导体层可以是用于形成双极结型晶体管的本征基极和非本征基极的基极层。

10. 发明授权

US09553145B2 Lateral bipolar junction transistors on a silicon-on-insulator substrate with a thin device layer thickness 有权
标题翻译：具有薄的器件层厚度的绝缘体上硅衬底上的侧向双极结型晶体管
公开(公告)号：US09553145B2
公开(公告)日：2017-01-24
申请号：US14476007
申请日：2014-09-03
申请人： GLOBALFOUNDRIES INC.
发明人： David L. Harame , Michael L. Kerbaugh , Qizhi Liu
IPC分类号： H01L29/737 , H01L29/10 , H01L29/732 , H01L27/12 , H01L21/84 , H01L29/08 , H01L29/417 , H01L29/66
CPC分类号： H01L29/1004 , H01L21/84 , H01L27/12 , H01L29/0821 , H01L29/41708 , H01L29/66272 , H01L29/732
摘要： Methods of forming bipolar device structures and bipolar device structures. An opening may be formed in a device layer of a silicon-on-insulator substrate that extends to a buried insulator layer of the silicon-on-insulator substrate. An intrinsic base layer may be grown within the device layer opening by lateral growth on opposite first and second sidewalls of the device layer bordering the opening. A first collector of a first bipolar junction transistor of the device structure may be formed at a first spacing from the first sidewall. A second collector of a second bipolar junction transistor of the device structure may be formed at a second spacing from the second sidewall. An emitter, which is shared by the first bipolar junction transistor and the second bipolar transistor, is formed inside the opening. Portions of the intrinsic base layer may supply respective intrinsic bases for the first and second bipolar junction transistors.
摘要翻译：形成双极器件结构和双极器件结构的方法。可以在绝缘体上硅衬底的器件层中形成开口，该器件层延伸到绝缘体上硅衬底的掩埋绝缘体层。内部基极层可以通过在与开口相邻的器件层的相对的第一和第二侧壁上的横向生长而在器件层内生长。器件结构的第一双极结型晶体管的第一集电极可以以与第一侧壁隔开的第一间隔形成。器件结构的第二双极结晶体管的第二集电极可以形成在距离第二侧壁的第二间隔处。在开口内形成由第一双极结型晶体管和第二双极晶体管共用的发射极。本征基极层的一部分可以为第一和第二双极结型晶体管提供相应的本征基极。

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