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1. 发明授权

US09019667B2 Protection device and related fabrication methods 有权
标题翻译：保护装置及相关制造方法
公开(公告)号：US09019667B2
公开(公告)日：2015-04-28
申请号：US13671623
申请日：2012-11-08
申请人： Freescale Semiconductor Inc.
发明人： Chai Ean Gill , Changsoo Hong , Rouying Zhan , William G. Cowden
IPC分类号： H01L21/8222 , H02H9/04
CPC分类号： H02H9/044 , H01L21/8222 , H01L27/0259 , H01L27/0664
摘要： Protection device structures and related fabrication methods are provided. An exemplary protection device includes a first bipolar junction transistor, a second bipolar junction transistor, a first zener diode, and a second zener diode. The collectors of the first bipolar junction transistors are electrically coupled. A cathode of the first zener diode is coupled to the collector of the first bipolar transistor and an anode of the first zener diode is coupled to the base of the first bipolar transistor. A cathode of the second zener diode is coupled to the collector of the second bipolar transistor and an anode of the second zener diode is coupled to the base of the second bipolar transistor. In exemplary embodiments, the base and emitter of the first bipolar transistor are coupled at a first interface and the base and emitter of the second bipolar transistor are coupled at a second interface.
摘要翻译：提供了保护装置结构和相关制造方法。示例性保护装置包括第一双极结型晶体管，第二双极结型晶体管，第一齐纳二极管和第二齐纳二极管。第一双极结晶体管的集电极电耦合。第一齐纳二极管的阴极耦合到第一双极晶体管的集电极，第一齐纳二极管的阳极耦合到第一双极晶体管的基极。第二齐纳二极管的阴极耦合到第二双极晶体管的集电极，并且第二齐纳二极管的阳极耦合到第二双极晶体管的基极。在示例性实施例中，第一双极晶体管的基极和发射极在第一接口处耦合，并且第二双极晶体管的基极和发射极在第二接口处耦合。

2. 发明授权

US10483257B2 Low voltage NPN with low trigger voltage and high snap back voltage for ESD protection 有权
公开(公告)号：US10483257B2
公开(公告)日：2019-11-19
申请号：US14182937
申请日：2014-02-18
申请人： Freescale Semiconductor, Inc.
发明人： Chai Ean Gill , Changsoo Hong
IPC分类号： H01L27/02 , H01L29/66 , H01L29/735 , H01L29/06 , H01L29/08 , H01L29/10 , H01L21/762
摘要： An area-efficient, low voltage ESD protection device (200) is provided for protecting low voltage pins (229, 230) against ESD events by using one or more stacked low voltage NPN bipolar junction transistors, each formed in a p-type material with an N+ collector region (216) and P+ base region (218) formed on opposite sides of an N+ emitter region (217) with separate halo extension regions (220-222) formed around at least the collector and emitter regions to improve the second trigger or breakdown current (It2) and set the snapback voltage (Vsb) and triggering voltage (Vt1) at the desired level.

3. 发明申请

US20140126091A1 Protection Device And Related Fabrication Methods 有权
标题翻译：保护装置及相关制作方法
公开(公告)号：US20140126091A1
公开(公告)日：2014-05-08
申请号：US13671623
申请日：2012-11-08
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： Chai Ean Gill , Changsoo Hong , Rouying Zhan , William G. Cowden
IPC分类号： H02H9/04 , H01L21/8222
CPC分类号： H02H9/044 , H01L21/8222 , H01L27/0259 , H01L27/0664
摘要： Protection device structures and related fabrication methods are provided. An exemplary protection device includes a first bipolar junction transistor, a second bipolar junction transistor, a first zener diode, and a second zener diode. The collectors of the first bipolar junction transistors are electrically coupled. A cathode of the first zener diode is coupled to the collector of the first bipolar transistor and an anode of the first zener diode is coupled to the base of the first bipolar transistor. A cathode of the second zener diode is coupled to the collector of the second bipolar transistor and an anode of the second zener diode is coupled to the base of the second bipolar transistor. In exemplary embodiments, the base and emitter of the first bipolar transistor are coupled at a first interface and the base and emitter of the second bipolar transistor are coupled at a second interface.
摘要翻译：提供了保护装置结构和相关制造方法。示例性保护装置包括第一双极结型晶体管，第二双极结型晶体管，第一齐纳二极管和第二齐纳二极管。第一双极结晶体管的集电极电耦合。第一齐纳二极管的阴极耦合到第一双极晶体管的集电极，第一齐纳二极管的阳极耦合到第一双极晶体管的基极。第二齐纳二极管的阴极耦合到第二双极晶体管的集电极，并且第二齐纳二极管的阳极耦合到第二双极晶体管的基极。在示例性实施例中，第一双极晶体管的基极和发射极在第一接口处耦合，并且第二双极晶体管的基极和发射极在第二接口处耦合。

4. 发明申请

US20150236009A1 Low Voltage NPN with Low Trigger Voltage and High Snap Back Voltage for ESD Protection 审中-公开
标题翻译：低电压NPN，具有低触发电压和高捕捉背压，用于ESD保护
公开(公告)号：US20150236009A1
公开(公告)日：2015-08-20
申请号：US14182937
申请日：2014-02-18
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： Chai Ean Gill , Changsoo Hong
IPC分类号： H01L27/02 , H01L29/735 , H01L21/266 , H01L29/08 , H01L29/10 , H01L21/762 , H01L29/66 , H01L29/06
CPC分类号： H01L27/0259 , H01L21/76283 , H01L29/0649 , H01L29/0808 , H01L29/0821 , H01L29/1008 , H01L29/6625 , H01L29/735
摘要： An area-efficient, low voltage ESD protection device (200) is provided for protecting low voltage pins (229, 230) against ESD events by using one or more stacked low voltage NPN bipolar junction transistors, each formed in a p-type material with an N+ collector region (216) and P+ base region (218) formed on opposite sides of an N+ emitter region (217) with separate halo extension regions (220-222) formed around at least the collector and emitter regions to improve the second trigger or breakdown current (It2) and set the snapback voltage (Vsb) and triggering voltage (Vt1) at the desired level.
摘要翻译：提供了一种区域有效的低压ESD保护装置（200），用于通过使用一个或多个堆叠的低压NPN双极结型晶体管来保护低电压引脚（229,230）以抵抗ESD事件，每个形成在p型材料中，形成在N +发射极区域（217）的相对侧上的N +集电极区域（216）和P +基极区域（218），其具有形成在至少集电极和发射极区域周围的分开的卤素延伸区域（220-222），以改善第二触发或击穿电流（It2），并将快速恢复电压（Vsb）和触发电压（Vt1）设置在所需的电平。

5. 发明授权

US09018071B2 Methods for forming electrostatic discharge protection clamps with increased current capabilities 有权
标题翻译：用于形成具有增加的电流能力的静电放电保护夹的方法
公开(公告)号：US09018071B2
公开(公告)日：2015-04-28
申请号：US14168807
申请日：2014-01-30
申请人： Freescale Semiconductor Inc.
发明人： Rouying Zhan , Amaury Gendron , Chai Ean Gill
IPC分类号： H01L21/8222 , H01L23/62 , H01L21/8228 , H01L27/02 , H01L29/66
CPC分类号： H01L21/8228 , H01L27/0259 , H01L29/66234
摘要： Methods for forming an electrostatic discharge protection (ESD) clamps are provided. In one embodiment, the method includes forming at least one transistor having a first well region of a first conductivity type extending into a substrate. At least one transistor is formed having another well region of a second opposite conductivity type, which extends into the substrate to partially form a collector. The lateral edges of the transistor well regions are separated by a distance D, which at least partially determines a threshold voltage Vt1 of the ESD clamp. A base contact of the first conductivity type is formed in the first well region and separated from an emitter of the second conductivity type by a lateral distance Lbe. The first doping density and the lateral distance Lbe are selected to provide a parasitic base-emitter resistance Rbe in the range of 1
摘要翻译：提供了形成静电放电保护（ESD）夹具的方法。在一个实施例中，该方法包括形成至少一个具有延伸到衬底中的第一导电类型的第一阱区的晶体管。至少一个晶体管形成有具有第二相反导电类型的另一阱区，其延伸到衬底中以部分地形成集电极。晶体管阱区的横向边缘被隔开距离D，距离D至少部分地确定ESD钳位的阈值电压Vt1。第一导电类型的基极接触形成在第一阱区中，并且与第二导电类型的发射极分开横向距离Lbe。选择第一掺杂浓度和横向距离Lbe以在1

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