专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US4385380A Digital concentrator switch 失效
标题翻译：数字集中开关
公开(公告)号：US4385380A
公开(公告)日：1983-05-24
申请号：US240228
申请日：1981-03-03
申请人： Frederick H. Rees , Daniel F. Martin , Joseph P. Ryness
发明人： Frederick H. Rees , Daniel F. Martin , Joseph P. Ryness
IPC分类号： H04M7/14 , H04Q11/04 , H04J3/14
CPC分类号： H04Q11/04
摘要： In a fully digital telephone switching system, a digital switch may serve a number of PCM sub systems each having separate forward and reverse highways and each serving a number of subscribers' lines. The highways are grouped in blocks of eight, from which intelligence is received in serial byte-interleaved form and converted by serial-parallel converters to parallel byte-interleaved form. While in this form they are switched to other channels and applied to a super-multiplexer which they leave in parallel byte-interleaved form from which they are restored by another converter to serial byte-interleaved form for application to the switch's outputs. For the reverse channel the arrangement is the reverse of the above, i.e. serial-parallel conversion, switching and parallel-serial conversion to the line multiplex highways. For local calls a loop-back connection is provided via a fixed delay of half a frame time. Thus, if the outputs fail, the arrangement can still handle local calls. Further it is usable on its own as a small exchange.
摘要翻译：在全数字电话交换系统中，数字交换机可以服务多个PCM子系统，每个PCM子系统具有单独的正向和反向高速公路，并且每个服务于多个订户的线路。高速公路被分组成八个块，其中以串行字节交织形式接收智能，并且由串行并行转换器转换成并行字节交织形式。虽然以这种形式，它们被切换到其他通道并且被应用于超级多路复用器，它们以并行的字节交错形式离开，由另一个转换器将它们恢复为串行字节交错形式，以应用于交换机的输出。对于反向信道，该布置与上述相反，即串行并行转换，开关和并行 - 串行转换到线路多路复用高速公路。对于本地呼叫，通过半帧时间的固定延迟来提供环回连接。因此，如果输出失败，则该配置仍然可以处理本地呼叫。此外，它可以自己作为一个小交换。

2. 发明授权

US07360203B2 Program tracing in a multithreaded processor 有权
标题翻译：在多线程处理器中进行程序跟踪
公开(公告)号：US07360203B2
公开(公告)日：2008-04-15
申请号：US10774193
申请日：2004-02-06
申请人： Robert E. Ober , Daniel F. Martin , Roger D. Arnold , Erik K. Norden
发明人： Robert E. Ober , Daniel F. Martin , Roger D. Arnold , Erik K. Norden
IPC分类号： G06F9/45
CPC分类号： G06F9/3851 , G06F9/3824 , G06F9/3826 , G06F9/3861
摘要： A multithreaded processor includes a thread ID for each set of fetched bits in an instruction fetch and issue unit. The thread ID attaches to the instructions and operands of the set of fetched bits. Pipeline stages in the multithreaded processor stores the thread ID associated with each operand or instruction in the pipeline stage. The thread ID are used to maintain data coherency and to generate program traces that include thread information for the instructions executed by the multithreaded processor.
摘要翻译：多线程处理器包括在指令获取和发布单元中的每组提取位的线程ID。线程ID附加到获取位集合的指令和操作数。多线程处理器中的管道级存储与流水线级中的每个操作数或指令相关联的线程ID。线程ID用于维护数据一致性并生成包含由多线程处理器执行的指令的线程信息的程序跟踪。

3. 发明授权

US07774585B2 Interrupt and trap handling in an embedded multi-thread processor to avoid priority inversion and maintain real-time operation 有权
标题翻译：嵌入式多线程处理器中的中断和陷阱处理，以避免优先级倒置并保持实时操作
公开(公告)号：US07774585B2
公开(公告)日：2010-08-10
申请号：US10712473
申请日：2003-11-12
申请人： Robert E. Ober , Roger D. Arnold , Daniel F. Martin , Erik K. Norden
发明人： Robert E. Ober , Roger D. Arnold , Daniel F. Martin , Erik K. Norden
IPC分类号： G06F9/00
CPC分类号： G06F9/4812 , G06F9/462 , G06F13/26
摘要： A real-time, multi-threaded embedded system includes rules for handling traps and interrupts to avoid problems such as priority inversion and re-entrancy. By defining a global interrupt priority value for all active threads and only accepting interrupts having a priority higher than the interrupt priority value, priority inversion can be avoided. Switching to the same thread before any interrupt servicing, and disabling interrupts and thread switching during interrupt servicing can simplify the interrupt handling logic. By storing trap background data for traps and servicing traps only in their originating threads, trap traceability can be preserved. By disabling interrupts and thread switching during trap servicing, unintended trap re-entrancy and servicing disruption can be prevented.
摘要翻译：一个实时的多线程嵌入式系统包括处理陷阱和中断的规则，以避免诸如优先级倒置和重入的问题。通过为所有活动线程定义全局中断优先级值，并且仅接受优先级高于中断优先级值的中断，可以避免优先级反转。在任何中断服务之前切换到同一个线程，并且在中断服务期间禁用中断和线程切换可以简化中断处理逻辑。通过仅在其始发线程中存储陷阱和维护陷阱的陷阱后台数据，可以保留陷阱跟踪性。通过在陷阱维护期间禁用中断和线程切换，可以防止意外的陷阱重入和服务中断。

4. 发明授权

US07263599B2 Thread ID in a multithreaded processor 有权
标题翻译：多线程处理器中的线程ID
公开(公告)号：US07263599B2
公开(公告)日：2007-08-28
申请号：US10774226
申请日：2004-02-06
申请人： Erik K. Norden , Robert E. Ober , Roger D. Arnold , Daniel F. Martin
发明人： Erik K. Norden , Robert E. Ober , Roger D. Arnold , Daniel F. Martin
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/3808
摘要： A multithreaded processor includes a thread ID for each set of fetched bits in an instruction fetch and issue unit. The thread ID attaches to the instructions and operands of the set of fetched bits. Pipeline stages in the multithreaded processor stores the thread ID associated with each operand or instruction in the pipeline stage. The thread ID are used to maintain data coherency and to generate program traces that include thread information for the instructions executed by the multithreaded processor.
摘要翻译：多线程处理器包括在指令获取和发布单元中的每组提取位的线程ID。线程ID附加到获取位集合的指令和操作数。多线程处理器中的管道级存储与流水线级中的每个操作数或指令相关联的线程ID。线程ID用于维护数据一致性并生成包含由多线程处理器执行的指令的线程信息的程序跟踪。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式