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1. 发明申请

US20070164350A1 Method and structure for a self-aligned silicided word line and polysilicon plug during the formation of a semiconductor device 有权
标题翻译：在形成半导体器件期间自对准硅化物字线和多晶硅插塞的方法和结构
公开(公告)号：US20070164350A1
公开(公告)日：2007-07-19
申请号：US11545163
申请日：2006-10-10
申请人： Frederick Fishburn , Terrence McDaniel , Richard Lane
发明人： Frederick Fishburn , Terrence McDaniel , Richard Lane
IPC分类号： H01L29/788 , H01L29/00
CPC分类号： H01L21/28052 , H01L21/76889 , H01L21/76897 , H01L27/1052 , H01L27/10873 , H01L29/4933 , H01L29/66545
摘要： A method used to form a semiconductor device provides a silicide layer on a plurality of transistor word lines and on a plurality of conductive plugs. In one embodiment, the word lines, one or more sacrificial dielectric layers on the word lines, conductive plugs, and a conductive enhancement layer are formed through the use of a single mask. An in-process semiconductor device which may be formed using one embodiment of the inventive method is also described.
摘要翻译：用于形成半导体器件的方法在多个晶体管字线和多个导电插塞上提供硅化物层。在一个实施例中，通过使用单个掩模形成字线，字线上的一个或多个牺牲电介质层，导电插塞和导电增强层。还描述了可以使用本发明方法的一个实施例形成的过程中半导体器件。

2. 发明申请

US20060292838A1 Ion implanting methods 有权
标题翻译：离子注入方法
公开(公告)号：US20060292838A1
公开(公告)日：2006-12-28
申请号：US11168893
申请日：2005-06-28
申请人： Randall Culver , Terrence McDaniel , Hongmei Wang , James Dale , Richard Lane , Fred Fishburn
发明人： Randall Culver , Terrence McDaniel , Hongmei Wang , James Dale , Richard Lane , Fred Fishburn
IPC分类号： H01L21/22 , H01L21/31
CPC分类号： H01L21/26586 , H01L21/266
摘要： An ion implanting method includes forming a pair of spaced and adjacent features projecting outwardly from a substrate. At least outermost portions of the pair of spaced features are laterally pulled away from one another with a patterned photoresist layer received over the features and which has an opening therein received intermediate the pair of spaced features. While such spaced features are laterally pulled, a species is ion implanted into substrate material which is received lower than the pair of spaced features. After the ion implanting, the patterned photoresist layer is removed from the substrate. Other aspects and implementations are contemplated.
摘要翻译：离子注入方法包括形成从衬底向外突出的一对间隔且相邻的特征。所述一对间隔特征中的至少最外部的部分被横向地拉离彼此，图案化的光致抗蚀剂层被接收在特征上，并且其中具有开口，其中接收有一对隔开的特征。虽然这种间隔的特征被横向拉伸，但是一种物质被离子注入到被接收低于该对间隔特征的基底材料中。在离子注入之后，从衬底去除图案化的光致抗蚀剂层。考虑了其他方面和实现。

3. 发明申请

US20050009343A1 Method and structure for a self-aligned silicided word line and polysilicon plug during the formation of a semiconductor device 有权
标题翻译：在形成半导体器件期间自对准硅化物字线和多晶硅插塞的方法和结构
公开(公告)号：US20050009343A1
公开(公告)日：2005-01-13
申请号：US10619052
申请日：2003-07-10
申请人： Fredrick Fishburn , Terrence McDaniel , Richard Lane
发明人： Fredrick Fishburn , Terrence McDaniel , Richard Lane
IPC分类号： H01L21/28 , H01L21/285 , H01L21/336 , H01L21/60 , H01L21/768 , H01L21/8239 , H01L21/8242 , H01L29/49 , H01L21/302 , H01L21/461
CPC分类号： H01L21/28052 , H01L21/76889 , H01L21/76897 , H01L27/1052 , H01L27/10873 , H01L29/4933 , H01L29/66545
摘要： A method used to form a semiconductor device provides a silicide layer on a plurality of transistor word lines and on a plurality of conductive plugs. In one embodiment, the word lines, one or more sacrificial dielectric layers on the word lines, conductive plugs, and a conductive enhancement layer are formed through the use of a single mask. An in-process semiconductor device which can be formed using one embodiment of the inventive method is also described.
摘要翻译：用于形成半导体器件的方法在多个晶体管字线和多个导电插塞上提供硅化物层。在一个实施例中，通过使用单个掩模形成字线，字线上的一个或多个牺牲电介质层，导电插塞和导电增强层。还描述了可以使用本发明方法的一个实施例形成的过程中半导体器件。

4. 发明授权

US07902057B2 Methods of fabricating dual fin structures 有权
标题翻译：制造双鳍结构的方法
公开(公告)号：US07902057B2
公开(公告)日：2011-03-08
申请号：US11831296
申请日：2007-07-31
申请人： Terrence McDaniel
发明人： Terrence McDaniel
IPC分类号： H01L21/3205
CPC分类号： H01L29/66795 , H01L29/7854
摘要： Fin-FET devices and methods of fabrication are disclosed. The Fin-FET devices include dual fins that may be used to provide a trench region between a source region and a drain region. In some embodiments, the dual fins may be formed by forming a trench with fin structures on opposite sides in a protruding region of a substrate. The dual fins may be useful in forming single-gate, double-gate or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed.
摘要翻译：披露了Fin-FET器件及其制造方法。 Fin-FET器件包括可以用于在源极区域和漏极区域之间提供沟槽区域的双鳍片。在一些实施例中，可以通过在衬底的突出区域中的相对侧上形成具有翅片结构的沟槽来形成双翅片。双翅片可用于形成单栅极，双栅极或三栅极鳍FET器件。还公开了包括这种鳍式FET器件的电子系统。

5. 发明授权

US07445996B2 Low resistance peripheral contacts while maintaining DRAM array integrity 有权
标题翻译：低电阻外围触点，同时保持DRAM阵列的完整性
公开(公告)号：US07445996B2
公开(公告)日：2008-11-04
申请号：US11074563
申请日：2005-03-08
申请人： Terrence McDaniel
发明人： Terrence McDaniel
IPC分类号： H01L21/336
CPC分类号： H01L21/76855 , H01L21/76816 , H01L21/76846 , H01L21/76877 , H01L27/10888 , H01L27/10894
摘要： A process and apparatus directed to forming low resistance contacts in both the memory cell array and peripheral logic circuitry areas of a semiconductor device, for example, a DRAM memory device, is disclosed. In a buried bit line connection process flow, the present invention utilizes chemical vapor deposition of titanium to form titanium silicide in contact structures of the peripheral logic circuitry areas and physical vapor deposition to provide a metal mode (metallic) titanium layer in contact with the poly plugs in the memory cell array area of a semiconductor device, for example, a DRAM memory device according to the present invention. In this manner, the present invention avoids the potential drawbacks such as voiding in the poly plugs of the memory cell array due to the present of titanium silicide, which can cause significant reduction of device drain current and in extreme cases cause electrical discontinuity.
摘要翻译：公开了一种用于在半导体器件（例如DRAM存储器件）的存储单元阵列和外围逻辑电路区域中形成低电阻触点的工艺和装置。在掩埋位线连接工艺流程中，本发明利用钛的化学气相沉积在外围逻辑电路区域和物理气相沉积的接触结构中形成硅化钛，以提供与聚对苯二甲酸丁酯接触的金属模（金属）钛层插入半导体器件的存储单元阵列区域，例如根据本发明的DRAM存储器件。以这种方式，本发明避免了由于存在硅化钛的现象导致的存储单元阵列的多晶硅栓堵塞的潜在缺点，这可能导致器件漏极电流的显着降低，并且在极端情况下导致电不连续性。

6. 发明申请

US20070040224A1 Method for forming a buried digit line with self aligning spacing layer and contact plugs during the formation of a semiconductor device, semiconductor devices, and systems including same 有权
标题翻译：在形成半导体器件期间形成具有自对准间隔层和接触插塞的掩埋数字线的方法，半导体器件和包括其的系统
公开(公告)号：US20070040224A1
公开(公告)日：2007-02-22
申请号：US11208972
申请日：2005-08-22
申请人： James Green , Terrence McDaniel
发明人： James Green , Terrence McDaniel
IPC分类号： H01L29/94
CPC分类号： H01L21/76897 , H01L21/31111 , H01L21/31116 , H01L21/31144 , H01L27/10808 , H01L27/10885
摘要： A method for use during fabrication of a semiconductor device comprises the formation of buried digit lines and contacts. During formation, a buried bit line layer may be used as a mask to etch one or more openings in a dielectric layer. A conductive layer is then formed in the one or more openings in the dielectric layer, and is then planarized to form one or more individual contact plugs. Next, the buried bit line layer is etched to recess the buried bit line layer, and a capacitor plate is formed to contact the contact plug.
摘要翻译：在制造半导体器件期间使用的方法包括形成掩埋的数字线和触点。在形成期间，掩埋位线层可以用作掩模以蚀刻电介质层中的一个或多个开口。然后在电介质层的一个或多个开口中形成导电层，然后将其平坦化以形成一个或多个单独的接触插塞。接下来，蚀刻掩埋位线层以使埋入的位线层凹陷，并且形成电容器板以接触接触插塞。

7. 发明授权

US08026542B2 Low resistance peripheral local interconnect contacts with selective wet strip of titanium 有权
标题翻译：低电阻外围局部互连接触与选择性湿条钛
公开(公告)号：US08026542B2
公开(公告)日：2011-09-27
申请号：US11512004
申请日：2006-08-29
申请人： Terrence McDaniel , Sandra Tagg , Fred Fishburn
发明人： Terrence McDaniel , Sandra Tagg , Fred Fishburn
IPC分类号： H01L27/108
CPC分类号： H01L23/48 , H01L21/02068 , H01L21/28052 , H01L21/2855 , H01L21/32134 , H01L21/76843 , H01L21/76846 , H01L21/76895 , H01L21/76897 , H01L27/10888 , H01L27/10894 , H01L29/4933 , H01L2924/0002 , H01L2924/00
摘要： Methods for forming memory devices and integrated circuitry, for example, DRAM circuitry, structures and devices resulting from such methods, and systems that incorporate the devices are provided.
摘要翻译：提供了用于形成存储器件和集成电路的方法，例如由这些方法产生的DRAM电路，结构和器件，以及结合该器件的系统。

8. 发明申请

US20110101429A1 SEMICONDUCTOR DEVICE STRUCTURES WITH DUAL FIN STRUCTURES AND ELECTRONIC DEVICE 审中-公开
标题翻译：具有双重结构和电子器件的半导体器件结构
公开(公告)号：US20110101429A1
公开(公告)日：2011-05-05
申请号：US12987746
申请日：2011-01-10
申请人： Terrence McDaniel
发明人： Terrence McDaniel
IPC分类号： H01L29/78 , H01L29/06
CPC分类号： H01L29/66795 , H01L29/7854
摘要： Fin-FET devices and methods of fabrication are disclosed. The Fin-FET devices include dual fins that may be used to provide a trench region between a source region and a drain region. In some embodiments, the dual fins may be formed by forming a trench with fin structures on opposite sides in a protruding region of a substrate. The dual fins may be useful in forming single-gate, double-gate or triple-gate fin-PET devices. Electronic systems including such fin-FET devices are also disclosed.
摘要翻译：披露了Fin-FET器件及其制造方法。 Fin-FET器件包括可以用于在源极区域和漏极区域之间提供沟槽区域的双鳍片。在一些实施例中，可以通过在衬底的突出区域中的相对侧上形成具有翅片结构的沟槽来形成双翅片。双翅片可用于形成单栅极，双栅极或三栅极鳍式PET器件。还公开了包括这种鳍式FET器件的电子系统。

9. 发明申请

US20060289918A1 Low resistance peripheral local interconnect contacts with selective wet strip of titanium 有权
标题翻译：低电阻外围局部互连接触与选择性湿条钛
公开(公告)号：US20060289918A1
公开(公告)日：2006-12-28
申请号：US11512004
申请日：2006-08-29
申请人： Terrence McDaniel , Sandra Tagg , Fred Fishburn
发明人： Terrence McDaniel , Sandra Tagg , Fred Fishburn
IPC分类号： H01L29/94 , H01L23/48
CPC分类号： H01L23/48 , H01L21/02068 , H01L21/28052 , H01L21/2855 , H01L21/32134 , H01L21/76843 , H01L21/76846 , H01L21/76895 , H01L21/76897 , H01L27/10888 , H01L27/10894 , H01L29/4933 , H01L2924/0002 , H01L2924/00
摘要： Methods for forming memory devices and integrated circuitry, for example, DRAM circuitry, structures and devices resulting from such methods, and systems that incorporate the devices are provided.
摘要翻译：提供了用于形成存储器件和集成电路的方法，例如由这些方法产生的DRAM电路，结构和器件，以及结合该器件的系统。

10. 发明申请

US20080113501A1 Methods of Forming Semiconductor Constructions 有权
标题翻译：形成半导体结构的方法
公开(公告)号：US20080113501A1
公开(公告)日：2008-05-15
申请号：US11971747
申请日：2008-01-09
申请人： Terrence McDaniel , Scott Southwick , Fred Fishburn
发明人： Terrence McDaniel , Scott Southwick , Fred Fishburn
IPC分类号： H01L21/44
CPC分类号： H01L27/10885 , H01L27/10852 , H01L27/10894 , H01L27/10897 , H01L28/90
摘要： The invention includes methods of forming semiconductor constructions in which electrically conductive structures are formed between bitlines to electrically connect with storage node contacts. The bitlines can be formed within trenches having faceted top portions. The invention also includes semiconductor structures containing trenches with faceted top portions, and containing bitlines within the trenches.
摘要翻译：本发明包括形成半导体结构的方法，其中在位线之间形成导电结构以与存储节点接触电连接。位线可以形成在具有多边形顶部的沟槽内。本发明还包括含有具有多面顶部的沟槽并且在沟槽内包含位线的半导体结构。

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