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1. 发明申请

US20110121934A1 Lead Frame-based Discrete Power Inductor 有权
标题翻译：引线框架离散功率电感器
公开(公告)号：US20110121934A1
公开(公告)日：2011-05-26
申请号：US13021347
申请日：2011-02-04
申请人： Francois Hébert , Tao Feng , Xiaotian Zhang , Jun Lu
发明人： Francois Hébert , Tao Feng , Xiaotian Zhang , Jun Lu
IPC分类号： H01F5/04
CPC分类号： H01F17/062
摘要： A lead frame-based discrete power inductor is disclosed. The power inductor includes top and bottom lead frames, the leads of which form a coil around a single closed-loop magnetic core. The coil includes interconnections between inner and outer contact sections of the top and bottom lead frames, the magnetic core being sandwiched between the top and bottom lead frames. Ones of the leads of the top and bottom lead frames have a generally non-linear, stepped configuration such that the leads of the top lead frame couple adjacent leads of the bottom lead frame about the magnetic core to form the coil.
摘要翻译：公开了一种基于引线框架的分立功率电感器。功率电感器包括顶部和底部引线框架，其引线围绕单个闭环磁芯形成线圈。线圈包括顶部和底部引线框架的内部和外部接触部分之间的互连，磁芯夹在顶部和底部引线框架之间。顶部引线框架和底部引线框架的引线的一部分具有大致非线性的阶梯状构造，使得顶部引线框架的引线将底部引线框架的相邻引线围绕磁芯耦合以形成线圈。

2. 发明授权

US07948346B2 Planar grooved power inductor structure and method 有权
公开(公告)号：US07948346B2
公开(公告)日：2011-05-24
申请号：US12165423
申请日：2008-06-30
申请人： Francois Hébert , Tao Feng , Jun Lu
发明人： Francois Hébert , Tao Feng , Jun Lu
IPC分类号： H01F5/00
CPC分类号： H01F17/0033 , H01F1/344 , H01F41/046 , H01F2017/002 , Y10T29/4902
摘要： An inductor may include a planar ferrite core. A first group of one or more grooves is formed in a first side of the ferrite core. A second group of two or more grooves is formed in a second side of the ferrite core. The grooves in the first and second groups are oriented such that each groove in the first group overlaps with two corresponding grooves in the second group. A first plurality of vias communicates through the ferrite core between the first and second sides of the ferrite core. Each via is located where a groove in the first group overlaps with a groove in the second group. A conductive material is disposed in the first and second groups of grooves and in the vias to form an inductor coil.

3. 发明申请

US20160351658A1 Configurations and Methods for Manufacturing Charged Balanced Devices 审中-公开
标题翻译：制造充电平衡器件的配置和方法
公开(公告)号：US20160351658A1
公开(公告)日：2016-12-01
申请号：US15182416
申请日：2016-06-14
申请人： Francois Hébert
发明人： Francois Hébert
IPC分类号： H01L29/06 , H01L29/66 , H01L21/265 , H01L29/78
CPC分类号： H01L29/0634 , H01L21/26513 , H01L21/26586 , H01L29/0878 , H01L29/0886 , H01L29/66734 , H01L29/7813
摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of deep trenches. The deep trenches are filled with an epitaxial layer thus forming a top epitaxial layer covering areas above a top surface of the deep trenches covering over the semiconductor substrate. The semiconductor power device further includes a plurality of transistor cells disposed in the top epitaxial layer whereby a device performance of the semiconductor power device is dependent on a depth of the deep trenches and not dependent on a thickness of the top epitaxial layer. Each of the plurality of transistor cells includes a trench DMOS transistor cell having a trench gate opened through the top epitaxial layer and filled with a gate dielectric material.
摘要翻译：本发明公开了一种设置在半导体衬底中的半导体功率器件，半导体衬底具有多个深沟槽。深沟槽填充有外延层，从而形成覆盖半导体衬底上的深沟槽顶表面上方的区域的顶部外延层。半导体功率器件还包括设置在顶部外延层中的多个晶体管单元，由此半导体功率器件的器件性能取决于深沟槽的深度，而不依赖于顶部外延层的厚度。多个晶体管单元中的每一个包括沟槽DMOS晶体管单元，其沟槽栅极通过顶部外延层开口并且填充有栅极电介质材料。

4. 发明申请

US20110306175A1 HIGH POWER AND HIGH TEMPERATURE SEMICONDUCTOR POWER DEVICES PROTECTED BY NON-UNIFORM BALLASTED SOURCES 有权
标题翻译：非均匀电压源保护的高功率和高温半导体功率器件
公开(公告)号：US20110306175A1
公开(公告)日：2011-12-15
申请号：US13199251
申请日：2011-08-23
申请人： Francois Hébert , Anup Bhalla
发明人： Francois Hébert , Anup Bhalla
IPC分类号： H01L21/02
CPC分类号： H01L29/7802 , H01L24/05 , H01L29/0696 , H01L29/086 , H01L29/41741 , H01L29/41775 , H01L29/456 , H01L29/7803 , H01L2224/0603 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/00
摘要： A semiconductor power device is formed on a semiconductor substrate. The semiconductor power device includes a plurality of transistor cells distributed over different areas having varying amount of ballasting resistances depending on a local thermal dissipation in each of the different areas. An exemplary embodiment has the transistor cells with a lower ballasting resistance formed near a peripheral area and the transistor cells having a higher ballasting resistance are formed near a bond pad area. Another exemplary embodiment comprises cells with a highest ballasting resistance formed in an area around a wire-bonding pad, the transistor cells having a lower resistance are formed underneath the wire-bonding pad connected to bonding wires for dissipating heat and the transistor cells having a lowest ballasting resistance are formed in an areas away from the bonding pad.
摘要翻译：半导体功率器件形成在半导体衬底上。半导体功率器件包括分布在不同区域上的多个晶体管单元，其具有取决于每个不同区域中的局部散热的不同量的镇流电阻。示例性实施例具有在周边区域附近形成的具有较低的镇流电阻的晶体管电池，并且在接合焊盘区域附近形成具有较高耐压电性的晶体管电池。另一个示例性实施例包括形成在引线焊盘周围的区域中具有最高镇流电阻的电池，具有较低电阻的晶体管单元形成在连接到用于散热的接合线的引线接合焊盘下方，并且具有最低的晶体管电池在距离接合焊盘的区域中形成耐压性。

5. 发明申请

US20100140693A1 Inverted-trench grounded-source FET structure using conductive substrates, with highly doped substrates 有权
标题翻译：使用导电衬底的反向沟槽接地源FET结构，具有高度掺杂的衬底
公开(公告)号：US20100140693A1
公开(公告)日：2010-06-10
申请号：US12653354
申请日：2009-12-11
申请人： Francois Hébert
发明人： Francois Hébert
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/26586 , H01L29/0865 , H01L29/0878 , H01L29/0886 , H01L29/407 , H01L29/4175 , H01L29/4236 , H01L29/66689 , H01L29/66704 , H01L29/66719 , H01L29/66734 , H01L29/781 , H01L29/7811 , H01L29/7825
摘要： This invention discloses an inverted field-effect-transistor (iT-FET) semiconductor device that includes a source disposed on a bottom and a drain disposed on a top of a semiconductor substrate. The semiconductor power device further comprises a trench-sidewall gate placed on sidewalls at a lower portion of a vertical trench surrounded by a body region encompassing a source region with a low resistivity body-source structure connected to a bottom source electrode and a drain link region disposed on top of said body regions thus constituting a drift region. The drift region is operated with a floating potential said iT-FET device achieving a self-termination.
摘要翻译：本发明公开了一种反相场效应晶体管（iT-FET）半导体器件，其包括设置在半导体衬底顶部的底部的源极和漏极。该半导体功率器件还包括一个沟槽侧壁栅极，该沟槽侧壁栅极位于垂直沟槽的下部的侧壁上，该垂直沟槽被包围源极区域的主体区域围绕，该源区域具有连接到底部源极电极和漏极连接区域的低电阻率主体 - 设置在所述身体区域的顶部，从而构成漂移区域。漂移区域以浮动电位工作，所述iT-FET器件实现自终止。

6. 发明申请

US20100133644A1 Bottom anode Schottky diode structure and method 有权
标题翻译：底部阳极肖特基二极管的结构和方法
公开(公告)号：US20100133644A1
公开(公告)日：2010-06-03
申请号：US12653345
申请日：2009-12-11
申请人： Francois Hébert
发明人： Francois Hébert
IPC分类号： H01L29/872 , H01L21/30
CPC分类号： H01L29/872 , H01L29/402 , H01L29/66143 , H01L29/861 , H01L2924/0002 , H01L2924/00
摘要： This invention discloses a bottom-anode Schottky (BAS) diode that includes an anode electrode disposed on a bottom surface of a semiconductor substrate. The bottom-anode Schottky diode further includes a sinker dopant region disposed at a depth in the semiconductor substrate extending substantially to the anode electrode disposed on the bottom surface of the semiconductor and the sinker dopant region covered by a buried Schottky barrier metal functioning as a Schottky anode. The BAS diode further includes a lateral cathode region extended laterally from a cathode electrode near a top surface of the semiconductor substrate opposite the Schottky barrier metal wherein the lateral cathode region doped with an opposite dopant from the sinker dopant region and interfacing the sinker dopant region whereby a current path is formed from the cathode electrode to the anode electrode through the lateral cathode region and the sinker dopant region in applying a forward bias voltage and the sinker dopant region depleting the cathode region in applying a reverse bias voltage for blocking a leakage current.
摘要翻译：本发明公开了一种底阳极肖特基（BAS）二极管，其包括设置在半导体衬底的底表面上的阳极电极。底部阳极肖特基二极管还包括设置在半导体衬底中的深度处的沉降片掺杂剂区域，其基本上延伸到设置在半导体底表面上的阳极电极和由用作肖特基的埋地肖特基势垒金属覆盖的沉降弧掺杂区域阳极。 BAS二极管进一步包括从阴极延伸到靠近半导体衬底的与肖特基势垒金属相对的顶表面的横向阴极区域，其中侧向阴极区域掺杂有与沉降弧掺杂区域相反的掺杂剂，并且与沉淀弧掺杂区域接合，由此在施加正偏压时，通过横向阴极区和沉降弧掺杂区形成电流路径，并且在施加用于阻断泄漏电流的反向偏置电压时消耗阴极区的沉降掺杂区。

7. 发明授权

US06437416B1 Semiconductor structure having a planar junction termination with high breakdown voltage and low parasitic capacitance 失效
标题翻译：具有具有高击穿电压和低寄生电容的平面结端接的半导体结构
公开(公告)号：US06437416B1
公开(公告)日：2002-08-20
申请号：US08634310
申请日：1996-04-12
申请人： Francois Hébert
发明人： Francois Hébert
IPC分类号： H01L2947
CPC分类号： H01L29/408 , H01L21/76202 , H01L21/765 , H01L29/66272
摘要： The breakdown voltage of a semiconductor device, such as a transistor fabricated in a device region in and abutting the surface of a semiconductor body with a field oxide surrounding the device region, is improved by etching the field oxide abutting the device region to reduce the thickness thereof to about 0.6-1.4 &mgr;m and then forming a field plate in the recessed field oxide which is capacitively coupled to the underlying semiconductor body. The field plate can be floating, connected to a voltage potential, or connected to the semiconductor device.
摘要翻译：通过蚀刻邻近器件区域的场氧化物来减小半导体器件的击穿电压，例如晶体管在器件区域内制造的半导体器件的表面上并且邻近具有围绕器件区域的场氧化物的表面，至约0.6-1.4μm，然后在电容耦合到下面的半导体主体的凹陷场氧化物中形成场板。场板可以浮动，连接到电压电位，或连接到半导体器件。

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