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1. 发明申请

US20050018504A1 Array of non volatile split-gate memory cells for avoiding parasitic programming and programming method thereof 审中-公开
标题翻译：用于避免寄生编程及其编程方法的非易失性分闸存储器单元阵列
公开(公告)号：US20050018504A1
公开(公告)日：2005-01-27
申请号：US10896911
申请日：2004-07-23
申请人： Filippo Marinelli , Nadia Narabech
发明人： Filippo Marinelli , Nadia Narabech
IPC分类号： G11C11/34 , G11C16/04 , G11C16/10 , G11C16/34
CPC分类号： G11C16/0425 , G11C16/10 , G11C16/3418
摘要： There is disclosed an array (10) of split-gate non-volatile memory cells (24) supplied with power at a low voltage (VDD) by a power supply (30), said cells being arranged in one or more rows and columns and electrically interconnected in groups to form one or more pages (12). The array comprises control logic (32) delivering a defined programming voltage (VPROG) that is close or or substantially equal to the low power supply voltage that is applied to a control gate (245) of at least one cell (24A) that is to be programmed via a word control line (18) corresponding to that cell and blocking logic (36) delivering a first blocking voltage (VBLOC1) that is greater than said low power supply voltage and is applied to the first regions (241) of the cells (24B) sharing the same word control line (18) as said cell that is to be programmed via a bit control line (22) corresponding to those cells.
摘要翻译：公开了一种通过电源（30）以低电压（VDD）供电的分离栅极非易失性存储单元（24）的阵列（10），所述单元被布置成一行或多行和列，并且以组形式电互连以形成一个或多个页面（12）。所述阵列包括控制逻辑（32），其输送接近或或基本上等于施加到至少一个单元（24A）的控制栅极（245）的所述低电源电压的定义编程电压（VPROG），所述至少一个单元通过与该单元相对应的字控制线（18）来编程，并且阻塞逻辑（36）传送大于所述低电源电压的第一阻断电压（VBLOC1），并被施加到单元的第一区（241）（24B）与通过与这些单元相对应的位控制线（22）编程的所述单元共享相同的字控制线（18）。

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