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1. 发明授权

US06522357B2 Method and apparatus for increasing retention time in image sensors having an electronic shutter 失效
标题翻译：用于增加具有电子快门的图像传感器中的保留时间的方法和装置
公开(公告)号：US06522357B2
公开(公告)日：2003-02-18
申请号：US08939808
申请日：1997-09-30
申请人： Mark A. Beiley , Eric J. Hoffman , Lawrence T. Clark
发明人： Mark A. Beiley , Eric J. Hoffman , Lawrence T. Clark
IPC分类号： H04N314
CPC分类号： H04N5/3595 , H04N5/353
摘要： In a pixel having an electronic shutter, a method of increasing the retention time of the electronic shutter is disclosed. A reset signal is employed to drive a diode node to a predetermined voltage immediately after integration is completed. A sample signal is employed to control a pass gate. The sample signal includes a state where the sample signal is a negative voltage.
摘要翻译：在具有电子快门的像素中，公开了增加电子快门的保持时间的方法。采用复位信号，在集成完成后立即将二极管节点驱动到预定电压。采样信号用于控制通过门。采样信号包括采样信号为负电压的状态。

2. 再颁专利

USRE43326E1 Tap connections for circuits with leakage suppression capability 有权
标题翻译：点击具有泄漏抑制能力的电路的连接
公开(公告)号：USRE43326E1
公开(公告)日：2012-04-24
申请号：US11802763
申请日：2007-05-24
申请人： Lawrence T. Clark , Vikas R. Amrelia , Raphael A. Soetan , Eric J. Hoffman , Tuan X. Do
发明人： Lawrence T. Clark , Vikas R. Amrelia , Raphael A. Soetan , Eric J. Hoffman , Tuan X. Do
IPC分类号： H01L21/20
CPC分类号： H01L23/5286 , H01L27/0203 , H01L27/118 , H01L2924/0002 , Y10T307/582 , H01L2924/00
摘要： An integrated circuit biases the substrate and well using voltages other than those used for power and ground. Tap cells inside the standard cell circuits are removed. New tap cells used to bias the substrate and well reside outside the standard cell circuits. The location of the new voltage power rails is designated prior to placement of the tap cells in the integrated circuit. The tap cells are then strategically placed near the power rails such that metal connections are minimized. Circuit density is thus not adversely impacted by the addition of the new power rails. Transistors are also placed inside the tap cells to address electrostatic discharge issues during fabrication.
摘要翻译：集成电路使用不同于用于电源和接地的电压来偏置衬底和阱。拆除标准电池电路内的电池。用于偏置衬底的新的抽头电池很好地驻留在标准电池电路之外。在将分接电池放置在集成电路中之前，指定新电压电源轨的位置。然后将龙头电池策略性地放置在电源轨附近，使金属连接最小化。因此，电路密度不会因添加新的电源轨而受到不利影响。晶体管也放置在抽头单元内，以解决制造过程中的静电放电问题。

3. 再颁专利

USRE42776E1 Tap connections for circuits with leakage suppression capability 有权
标题翻译：点击具有泄漏抑制能力的电路的连接
公开(公告)号：USRE42776E1
公开(公告)日：2011-10-04
申请号：US11802556
申请日：2007-05-23
申请人： Lawrence T. Clark , Vikas R. Amrelia , Raphael A. Soetan , Eric J. Hoffman , Tuan X. Do
发明人： Lawrence T. Clark , Vikas R. Amrelia , Raphael A. Soetan , Eric J. Hoffman , Tuan X. Do
IPC分类号： H01L23/52
CPC分类号： H01L23/5286 , H01L27/0203 , H01L27/118 , H01L2924/0002 , Y10T307/582 , H01L2924/00
摘要： An integrated circuit biases the substrate and well using voltages other than those used for power and ground. Tap cells inside the standard cell circuits are removed. New tap cells used to bias the substrate and well reside outside the standard cell circuits. The location of the new voltage power rails is designated prior to placement of the tap cells in the integrated circuit. The tap cells are then strategically placed near the power rails such that metal connections are minimized. Circuit density is thus not adversely impacted by the addition of the new power rails. Transistors are also placed inside the tap cells to address electrostatic discharge issues during fabrication.
摘要翻译：集成电路利用电源和接地以外的电压来偏置衬底和阱。拆除标准电池电路内的电池。用于偏置衬底的新的抽头电池很好地驻留在标准电池电路之外。在将分接电池放置在集成电路中之前，指定新电压电源轨的位置。然后将龙头电池策略性地放置在电源轨附近，使金属连接最小化。因此，电路密度不会因添加新的电源轨而受到不利影响。晶体管也放置在抽头单元内，以解决制造过程中的静电放电问题。

4. 发明授权

US06944784B2 Flip-flop having multiple clock sources and method therefore 有权
标题翻译：因此，具有多个时钟源的触发器和方法
公开(公告)号：US06944784B2
公开(公告)日：2005-09-13
申请号：US09895343
申请日：2001-06-29
申请人： Lawrence T. Clark , Eric J. Hoffman , Susan M. Graham , Dale J. Brown
发明人： Lawrence T. Clark , Eric J. Hoffman , Susan M. Graham , Dale J. Brown
IPC分类号： G01R31/3185 , G06F1/06 , H03K3/037 , G06F1/04
CPC分类号： G01R31/318541 , G06F1/06 , H03K3/0372 , H03K3/0375
摘要： Briefly, in accordance with one embodiment of the invention, a flip-flop operates as a master-slave flip flop in a test mode and operates as a pulsed latch in normal operation. Two clock signals having non-overlapping transitions are used to provide and control the flow of input data.
摘要翻译：简而言之，根据本发明的一个实施例，触发器在测试模式中作为主从触发器操作，并且在正常操作中作为脉冲锁存器操作。使用具有非重叠转换的两个时钟信号来提供和控制输入数据的流动。

5. 发明授权

US6040592A Well to substrate photodiode for use in a CMOS sensor on a salicide process 失效
标题翻译：对于在自对准硅化物工艺中的CMOS传感器中使用的衬底光电二极管
公开(公告)号：US6040592A
公开(公告)日：2000-03-21
申请号：US873987
申请日：1997-06-12
申请人： Bart McDaniel , Mark A. Beiley , Lawrence T. Clark , Eric J. Hoffman , Edward J. Bawolek
发明人： Bart McDaniel , Mark A. Beiley , Lawrence T. Clark , Eric J. Hoffman , Edward J. Bawolek
IPC分类号： H04N1/028 , C07D491/048 , H01L27/146 , H01L31/10 , H01L31/113 , H01L31/068 , H01L31/0352
CPC分类号： H01L27/14643 , H01L27/14609 , H01L31/1136
摘要： An image sensor having a well-to-substrate diode as the photodetector. In a preferred embodiment, a modern salicided (CMOS) process is utilized to manufacture the image sensor. The field oxide region above the diode junction is transparent to visible light, thus allowing the photodiode competitive quantum efficiency as compared to devices having source/drain diffusion-to-substrate photodiodes fabricated on a non-salicided process. The photodiode can be integrated as part of a sensor array with digital circuitry using a relatively unmodified digital CMOS process. Furthermore, the structure allows the optical properties of the photodiode to be engineered by modifying the well without deleterious effects, to approximate a first order, on the characteristics of a FET built in another identical well.
摘要翻译：一种具有良好对衬底二极管作为光电检测器的图像传感器。在优选实施例中，利用现代的水银（CMOS）工艺来制造图像传感器。二极管结上方的场氧化物区域对于可见光是透明的，因此与在非水银工艺上制造的源/漏扩散至衬底光电二极管的器件相比，光电二极管的竞争量子效率。光电二极管可以作为具有使用相对未修改的数字CMOS工艺的数字电路的传感器阵列的一部分进行集成。此外，该结构允许光电二极管的光学性质通过修改阱而不会对其内置于另一相同阱中的FET的特性产生有害影响，即接近于一阶。

6. 发明授权

US07010706B2 Apparatus having a first circuit supplying a power potential to a second circuit under a first operating mode otherwise decoupling the power potential 失效
标题翻译：具有第一电路的设备，其在第一操作模式下向第二电路提供功率电势，否则去耦电源电位
公开(公告)号：US07010706B2
公开(公告)日：2006-03-07
申请号：US09834408
申请日：2001-04-13
申请人： Lawrence T. Clark , Neil F. Deutscher , Eric J. Hoffman
发明人： Lawrence T. Clark , Neil F. Deutscher , Eric J. Hoffman
IPC分类号： G06F1/26
CPC分类号： G06F1/32 , G11C5/14 , G11C5/147
摘要： Briefly, in accordance with one embodiment of the invention, an integrated circuit has a voltage regulator that is used to provide a power supply potential to a memory circuit while a logic circuit is decoupled from a power supply potential.
摘要翻译：简而言之，根据本发明的一个实施例，集成电路具有电压调节器，其用于在逻辑电路与电源电位分离的同时向存储器电路提供电源电位。

7. 发明授权

US06368933B1 Tap connections for circuits with leakage suppression capability 有权
标题翻译：点击具有泄漏抑制能力的电路的连接
公开(公告)号：US06368933B1
公开(公告)日：2002-04-09
申请号：US09464023
申请日：1999-12-15
申请人： Lawrence T. Clark , Vikas R. Amrelia , Raphael A. Soetan , Eric J. Hoffman , Tuan X. Do
发明人： Lawrence T. Clark , Vikas R. Amrelia , Raphael A. Soetan , Eric J. Hoffman , Tuan X. Do
IPC分类号： H01L2120
CPC分类号： H01L23/5286 , H01L27/0203 , H01L27/118 , H01L2924/0002 , Y10T307/582 , H01L2924/00
摘要： An integrated circuit biases the substrate and well using voltages other than those used for power and ground. Tap cells inside the standard cell circuits are removed. New tap cells used to bias the substrate and well reside outside the standard cell circuits. The location of the new voltage power rails is designated prior to placement of the tap cells in the integrated circuit. The tap cells are then strategically placed near the power rails such that metal connections are minimized. Circuit density is thus not adversely impacted by the addition of the new power rails. Transistors are also placed inside the tap cells to address electrostatic discharge issues during fabrication.
摘要翻译：集成电路利用电源和接地以外的电压来偏置衬底和阱。拆除标准电池电路内的电池。用于偏置衬底的新的抽头电池很好地驻留在标准电池电路之外。在将分接电池放置在集成电路中之前，指定新电压电源轨的位置。然后将龙头电池策略性地放置在电源轨附近，使金属连接最小化。因此，电路密度不会因添加新的电源轨而受到不利影响。晶体管也放置在抽头单元内，以解决制造过程中的静电放电问题。

8. 发明授权

US6118482A Method and apparatus for electrical test of CMOS pixel sensor arrays 失效
标题翻译： CMOS像素传感器阵列的电气测试方法和装置
公开(公告)号：US6118482A
公开(公告)日：2000-09-12
申请号：US986499
申请日：1997-12-08
申请人： Lawrence T. Clark , Mark A. Beiley , Eric J. Hoffman
发明人： Lawrence T. Clark , Mark A. Beiley , Eric J. Hoffman
IPC分类号： H04N5/367 , H04N17/00 , H04N5/335
CPC分类号： H04N5/367 , H04N17/002
摘要： CMOS pixel sensors have been of interest as replacements for CCD's in imaging applications. Such devices promise lower power and simpler system level design through fewer power supply voltages and higher functional integration. It is difficult and cost ineffective to utilize images to test active pixel sensors. Here, a method and apparatus for electrical testing of CMOS pixel sensors is described which involves electrically writing a pattern into the CMOS pixel sensors for the detection of adjacent cell shorts or stuck at faults as well as verification of read-channel circuit functionality and performance. The invention provides for an electrical testing of CMOS pixel array that is simple, time efficient and cost effective for use in, for example, production.
摘要翻译：作为CCD成像应用中的替代品，CMOS像素传感器已经成为关注的焦点。这样的器件通过更少的电源电压和更高的功能集成来承诺更低的功率和更简单的系统级设计。利用图像测试有源像素传感器是困难和成本无效的。这里描述了用于CMOS像素传感器的电测试的方法和装置，其涉及将图案电学写入CMOS像素传感器，用于检测相邻单元短路或卡在故障以及读通道电路功能和性能的验证。本发明提供了CMOS像素阵列的电气测试，其简单，时间高效并且在例如生产中使用成本有效。

9. 发明授权

US06433822B1 Method and apparatus for self-calibration and fixed-pattern noise removal in imager integrated circuits 失效
标题翻译：成像仪集成电路中自校准和固定图案噪声去除的方法和装置
公开(公告)号：US06433822B1
公开(公告)日：2002-08-13
申请号：US09052749
申请日：1998-03-31
申请人： Lawrence T. Clark , Mark A. Beiley , Eric J. Hoffman
发明人： Lawrence T. Clark , Mark A. Beiley , Eric J. Hoffman
IPC分类号： H04N5217
CPC分类号： H04N5/361 , H04N5/2176 , H04N5/3658 , H04N5/378 , H04N17/002
摘要： An architecture for self-calibration and fixed-pattern noise removal in imager chips. The column-to-column fixed pattern noise and/or pixel-to-pixel fixed pattern noise is determined through a self-calibration operation. During operation of the imager chip, when a value of a pixel is read, the read value is compensated with the fixed-pattern noise corresponding to either the column fixed pattern noise corresponding to the column having the pixel from which the value was read or to the pixel fixed pattern noise corresponding to the pixel from which the value was read.
摘要翻译：在成像器芯片中进行自校准和固定图案噪声去除的架构。通过自校准操作来确定柱对列固定图案噪声和/或像素到像素的固定图案噪声。在成像器芯片的操作期间，当读取像素的值时，读取值被对应于与具有读取该值的像素的列相对应的列固定图案噪声的固定图案噪声补偿，或者对应于读取该值的像素的像素固定模式噪声。

10. 发明授权

US06388315B1 Tap connections for circuits with leakage suppression capability 有权
公开(公告)号：US06388315B1
公开(公告)日：2002-05-14
申请号：US09941829
申请日：2001-08-29
申请人： Lawrence T. Clark , Vikas R. Amrelia , Raphael A. Soetan , Eric J. Hoffman , Tuan X. Do
发明人： Lawrence T. Clark , Vikas R. Amrelia , Raphael A. Soetan , Eric J. Hoffman , Tuan X. Do
IPC分类号： H01L2352
CPC分类号： H01L23/5286 , H01L27/0203 , H01L27/118 , H01L2924/0002 , Y10T307/582 , H01L2924/00
摘要： An integrated circuit biases the substrate and well using voltages other than those used for power and ground. Tap cells inside the standard cell circuits are removed. New tap cells used to bias the substrate and well reside outside the standard cell circuits. The location of the new voltage power rails is designated prior to placement of the tap cells in the integrated circuit. The tap cells are then strategically placed near the power rails such that metal connections are minimized. Circuit density is thus not adversely impacted by the addition of the new power rails. Transistors are also placed inside the tap cells to address electrostatic discharge issues during fabrication.

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