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1. 发明授权

US07750648B2 Method to quickly estimate inductance for timing models 有权
标题翻译：快速估计定时模型电感的方法
公开(公告)号：US07750648B2
公开(公告)日：2010-07-06
申请号：US12059275
申请日：2008-03-31
申请人： Eric A. Foreman , Peter A. Habitz , Mark R. Lasher , William J. Livingstone , Gregory M. Schaeffer
发明人： Eric A. Foreman , Peter A. Habitz , Mark R. Lasher , William J. Livingstone , Gregory M. Schaeffer
IPC分类号： G01R27/00
CPC分类号： G01R27/2611 , G01R27/28 , G06F17/5036 , G06F2217/84
摘要： A method of estimating an inductance delay includes determining a resistance-capacitance (RC) delay with resistances and capacitances of a network and estimating an inductance delay of the network by determining a propagation delay of an electromagnetic (EM) field across wires of the network. Additionally, the method includes determining if the RC delay is below a specified threshold and adding the estimated inductance delay to the RC delay to determine a total time to propagate voltage swings through the network if the RC delay is below the specified threshold.
摘要翻译：估计电感延迟的方法包括通过确定网络的电线（EM）场的传播延迟来确定网络的电阻和电容的电阻 - 电容（RC）延迟并估计网络的电感延迟。此外，该方法包括确定RC延迟是否低于指定的阈值，并将估计的电感延迟与RC延迟相加，以确定如果RC延迟低于指定阈值，则传播通过网络的电压摆幅的总时间。

2. 发明申请

US20090243630A1 METHOD TO QUICKLY ESTIMATE INDUCTANCE FOR TIMING MODELS 有权
标题翻译：快速估计时序模型电感的方法
公开(公告)号：US20090243630A1
公开(公告)日：2009-10-01
申请号：US12059275
申请日：2008-03-31
申请人： Eric A. Foreman , Peter A. Habitz , Mark R. Lasher , William J. Livingstone , Gregory M. Schaeffer
发明人： Eric A. Foreman , Peter A. Habitz , Mark R. Lasher , William J. Livingstone , Gregory M. Schaeffer
IPC分类号： G01R27/28
CPC分类号： G01R27/2611 , G01R27/28 , G06F17/5036 , G06F2217/84
摘要： A method of estimating an inductance delay includes determining a resistance-capacitance (RC) delay with resistances and capacitances of a network and estimating an inductance delay of the network by determining a propagation delay of an electromagnetic (EM) field across wires of the network. Additionally, the method includes determining if the RC delay is below a specified threshold and adding the estimated inductance delay to the RC delay to determine a total time to propagate voltage swings through the network if the RC delay is below the specified threshold.
摘要翻译：估计电感延迟的方法包括通过确定网络的电线（EM）场的传播延迟来确定网络的电阻和电容的电阻 - 电容（RC）延迟并估计网络的电感延迟。此外，该方法包括确定RC延迟是否低于指定的阈值，并将估计的电感延迟与RC延迟相加，以确定如果RC延迟低于指定阈值，则传播通过网络的电压摆幅的总时间。

3. 发明授权

US07684969B2 Forming statistical model of independently variable parameters for timing analysis 有权
标题翻译：形成时间分析独立变量参数的统计模型
公开(公告)号：US07684969B2
公开(公告)日：2010-03-23
申请号：US11219205
申请日：2005-09-02
申请人： Peter A. Habitz , Mark R. Lasher , William J. Livingstone
发明人： Peter A. Habitz , Mark R. Lasher , William J. Livingstone
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5022
摘要： Forming of a statistical model for a set of independently variable parameters for analysis of a circuit design is disclosed. In one embodiment, a method includes establishing a timing model including delay and delay changes due to process parameter variations (Pi) that impact timing; selecting an element of the circuit design that dominates circuit delay in the timing model; determining a delay sensitivity of each of a set of derived process parameters (Vj) for the element that are linear combinations of the process parameter variations (Pi); and selecting only those derived process parameters with a high sensitivity for use in the statistical model. The invention simplifies the statistical model and reduces the number of calculations require for timing analysis. A method of performing a timing analysis using the simplified statistical model is also disclosed.
摘要翻译：公开了一组用于电路设计分析的独立可变参数的统计模型的形成。在一个实施例中，一种方法包括建立包括由于影响定时的过程参数变化（Pi）引起的延迟和延迟变化的定时模型; 选择在时序模型中支配电路延迟的电路设计元素; 确定作为所述过程参数变化（Pi）的线性组合的所述元素的一组导出过程参数（Vj）中的每一个的延迟灵敏度; 并仅选择具有高灵敏度的衍生过程参数用于统计模型。本发明简化了统计模型，并减少了时序分析所需的计算次数。还公开了使用简化统计模型执行定时分析的方法。

4. 发明授权

US07181711B2 Prioritizing of nets for coupled noise analysis 失效
标题翻译：耦合噪声分析网优先级
公开(公告)号：US07181711B2
公开(公告)日：2007-02-20
申请号：US10908101
申请日：2005-04-27
申请人： Eric A. Foreman , Peter A. Habitz , Gregory M. Schaeffer
发明人： Eric A. Foreman , Peter A. Habitz , Gregory M. Schaeffer
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A system and method of performing microelectronic chip timing analysis, wherein the method comprises identifying failing timing paths in a chip; prioritizing the failing timing paths in the chip according to a size of random noise events occurring in each timing path; attributing a slack credit statistic for all but highest order random noise events occurring in each timing path; and calculating a worst case timing path scenario based on the prioritized failing timing paths and the slack credit statistic. Preferably, the random noise events comprise non-clock events. Moreover, the random noise events may comprise victim/aggressor net groups belonging to different regularity groups. Preferably, the size of random noise events comprises coupled noise delta delays due to the random noise events occurring in the chip.
摘要翻译：一种执行微电子芯片定时分析的系统和方法，其中所述方法包括识别芯片中的故障定时路径; 根据每个定时路径中发生的随机噪声事件的大小对芯片中的故障定时路径进行优先级排序; 归因于每个定时路径中发生的所有但最高阶随机噪声事件的松弛信用统计; 以及基于优先顺序的故障定时路径和松弛信用统计量来计算最坏情况的定时路径情景。优选地，随机噪声事件包括非时钟事件。此外，随机噪声事件可以包括属于不同规则组的受害者/侵略者网络组。优选地，由于芯片中发生的随机噪声事件，随机噪声事件的大小包括耦合的噪声增量延迟。

5. 发明授权

US08056035B2 Method and system for analyzing cross-talk coupling noise events in block-based statistical static timing 有权
标题翻译：在基于块的统计静态时序中分析串扰耦合噪声事件的方法和系统
公开(公告)号：US08056035B2
公开(公告)日：2011-11-08
申请号：US12132636
申请日：2008-06-04
申请人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Gregory M. Schaeffer , Chandramouli Visweswariah
发明人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Gregory M. Schaeffer , Chandramouli Visweswariah
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/82
摘要： A method of performing statistical timing analysis of a logic design, including effects of signal coupling, includes performing a deterministic analysis to determine deterministic coupling information for at least one aggressor/victim net pair of the logic design. Additionally, the method includes performing a statistical timing analysis in which the deterministic coupling information for the at least one aggressor/victim net pair is combined with statistical values of the statistical timing analysis to determine a statistical effective capacitance of a victim of the aggressor/victim net pair. Furthermore, the method includes using the statistical effective capacitance to determine timing data used in the statistical timing analysis.
摘要翻译：执行包括信号耦合效应的逻辑设计的统计定时分析的方法包括执行确定性分析以确定逻辑设计的至少一个攻击者/受害者网对的确定性耦合信息。另外，该方法包括执行统计时序分析，其中至少一个攻击者/受害者网络对的确定性耦合信息与统计时间分析的统计值相结合，以确定攻击者/受害者的受害者的统计有效电容净对。此外，该方法包括使用统计有效电容来确定在统计时序分析中使用的定时数据。

6. 发明申请

US20090307645A1 METHOD AND SYSTEM FOR ANALYZING CROSS-TALK COUPLING NOISE EVENTS IN BLOCK-BASED STATISTICAL STATIC TIMING 有权
标题翻译：基于块状统计静态时序分析交叉口耦合噪声事件的方法与系统
公开(公告)号：US20090307645A1
公开(公告)日：2009-12-10
申请号：US12132636
申请日：2008-06-04
申请人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Gregory M. Schaeffer , Chandramouli Visweswariah
发明人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Gregory M. Schaeffer , Chandramouli Visweswariah
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/82
摘要： A method of performing statistical timing analysis of a logic design, including effects of signal coupling, includes performing a deterministic analysis to determine deterministic coupling information for at least one aggressor/victim net pair of the logic design. Additionally, the method includes performing a statistical timing analysis in which the deterministic coupling information for the at least one aggressor/victim net pair is combined with statistical values of the statistical timing analysis to determine a statistical effective capacitance of a victim of the aggressor/victim net pair. Furthermore, the method includes using the statistical effective capacitance to determine timing data used in the statistical timing analysis.
摘要翻译：执行包括信号耦合效应的逻辑设计的统计定时分析的方法包括执行确定性分析以确定逻辑设计的至少一个攻击者/受害者网对的确定性耦合信息。另外，该方法包括执行统计时序分析，其中至少一个攻击者/受害者网络对的确定性耦合信息与统计时间分析的统计值相结合，以确定攻击者/受害者的受害者的统计有效电容净对。此外，该方法包括使用统计有效电容来确定在统计时序分析中使用的定时数据。

7. 发明申请

US20090210839A1 TIMING CLOSURE USING MULTIPLE TIMING RUNS WHICH DISTRIBUTE THE FREQUENCY OF IDENTIFIED FAILS PER TIMING CORNER 审中-公开
标题翻译：使用多个时序的时序关闭，分配每个时间角的识别失败的频率
公开(公告)号：US20090210839A1
公开(公告)日：2009-08-20
申请号：US12031106
申请日：2008-02-14
申请人： Nathan C. Buck , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Kerim Kalafala , Gregory M. Schaeffer , Chandramouli Visweswariah
发明人： Nathan C. Buck , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Kerim Kalafala , Gregory M. Schaeffer , Chandramouli Visweswariah
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： A method of timing closure for integrated circuit designs uses multiple timing runs which distribute the frequency of identified fails per timing corner (between starting timing corners and remaining timing corners) to maximize efficiency in timing analysis. More specifically, the method closes timing for a chosen set of starting timing corners, verifies the remaining timing corners are orthogonal to the starting timing corners, closes timing for the remaining timing corners using multi-corner analysis, and verifies that all timing corners have positive slack margin.
摘要翻译：用于集成电路设计的定时闭合方法使用多个定时运行，其分配每个定时角点（在起始时间角和剩余时间角之间）识别的故障的频率，以最大化定时分析的效率。更具体地，该方法关闭所选择的一组起始定时角的定时，验证剩余的定时角与起始正时角正交，关闭使用多角分析的剩余定时角的定时，并且验证所有定时角均为正松弛边缘

8. 发明授权

US09858368B2 Integrating manufacturing feedback into integrated circuit structure design 有权
公开(公告)号：US09858368B2
公开(公告)日：2018-01-02
申请号：US13182108
申请日：2011-07-13
申请人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Jeffrey G. Hemmett , Natesan Venkateswaran , Chandramouli Visweswariah , Xiaoyue Wang , Vladmimir Zolotov
发明人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Jeffrey G. Hemmett , Natesan Venkateswaran , Chandramouli Visweswariah , Xiaoyue Wang , Vladmimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/84
摘要： Solutions for integrating manufacturing feedback into an integrated circuit design are disclosed. In one embodiment, a computer-implemented method is disclosed including: defining an acceptable yield requirement for a first integrated circuit product; obtaining manufacturing data about the first integrated circuit product; performing a regression analysis on data representing paths in the first integrated circuit product to define a plurality of parameter settings based upon the acceptable yield requirement and the manufacturing data; determining a projection corner associated with the parameter settings for satisfying the acceptable yield requirement; and modifying a design of a second integrated circuit product based upon the projection corner and the plurality of parameter settings.

9. 发明授权

US09157956B2 Adaptive power control using timing canonicals 有权
标题翻译：使用定时规范的自适应功率控制
公开(公告)号：US09157956B2
公开(公告)日：2015-10-13
申请号：US13614564
申请日：2012-09-13
申请人： Jeanne P. Bickford , Eric A. Foreman , Peter A. Habitz , Jeffrey G. Hemmett , Clarence R. Ogilvie , Tad J. Wilder , Vladimir Zolotov
发明人： Jeanne P. Bickford , Eric A. Foreman , Peter A. Habitz , Jeffrey G. Hemmett , Clarence R. Ogilvie , Tad J. Wilder , Vladimir Zolotov
IPC分类号： G06F17/50 , G01R31/317 , G01R31/30
CPC分类号： G01R31/31718 , G01R31/3008
摘要： A plurality of digital circuits are manufactured from an identical circuit design. A power controller is operatively connected to the digital circuits, and a non-transitory storage medium is operatively connected to the power controller. The digital circuits are classified into different voltage bins, and each of the voltage bins has a current leakage limit. Each of the digital circuits has been previously tested to operate within a corresponding current leakage limit of a corresponding voltage bin into which each of the digital circuits has been classified. The non-transitory storage medium stores boundaries of the voltage bins as speed-binning test data. The power controller controls power-supply signals applied differently for each of the digital circuits based on which bin each of the digital circuit has been classified and the speed-binning test data.
摘要翻译：由相同的电路设计制造多个数字电路。功率控制器可操作地连接到数字电路，并且非瞬时存储介质可操作地连接到功率控制器。数字电路分为不同的电压箱，每个电压箱都有漏电极限。已经对每个数字电路进行了测试，以在对应的电压仓的相应的电流泄漏极限内运行，每个数字电路已被分类到该对应的电压仓。非瞬时存储介质存储电压仓的边界作为速度分组测试数据。功率控制器控制基于每个数字电路已被分类的每个数字电路不同地施加的电源信号和速度合并测试数据。

10. 发明申请

US20130036395A1 EFFICIENT SLACK PROJECTION FOR TRUNCATED DISTRIBUTIONS 失效
标题翻译：截断分布的有效插值投影
公开(公告)号：US20130036395A1
公开(公告)日：2013-02-07
申请号：US13197320
申请日：2011-08-03
申请人： Eric A. Foreman , James C. Gregerson , Peter A. Habitz , Jeffrey G. Hemmett , Debjit Sinha , Natesan Venkateswaran , Chandramouli Visweswariah , Xiaoyue Wang , Vladmimir Zolotov
发明人： Eric A. Foreman , James C. Gregerson , Peter A. Habitz , Jeffrey G. Hemmett , Debjit Sinha , Natesan Venkateswaran , Chandramouli Visweswariah , Xiaoyue Wang , Vladmimir Zolotov
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5031
摘要： Aspects of the present invention provide solutions for projecting slack in an integrated circuit. A statistical static timing analysis (SSTA) is computed to get a set of Gaussian distributions over a plurality of variation sources in the integrated circuit. Based on the Gaussian distributions, a truncated subset and a remainder subset of the Gaussian distributions are identified. Then data factors that represent a ratio between the remainder subset and the truncated subset are obtained. These data factors are applied to the SSTA to root sum square (RSS) project the slack for the integrated circuit that takes into account the absence of the truncated subset.
摘要翻译：本发明的方面提供了用于在集成电路中突出松弛的解决方案。计算统计静态时序分析（SSTA）以在集成电路中的多个变化源上获得一组高斯分布。基于高斯分布，识别高斯分布的截断子集和余数子集。然后获得表示余数子集和截断子集之间的比率的数据因子。这些数据因子被应用于SSTA到根平方（RSS）项目，考虑到缺少截断子集的集成电路的松弛。

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