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1. 发明授权

US4450620A Fabrication of MOS integrated circuit devices 失效
标题翻译： MOS集成电路器件的制造
公开(公告)号：US4450620A
公开(公告)日：1984-05-29
申请号：US468032
申请日：1983-02-18
申请人： Ellis N. Fuls , Nadia Lifshitz , Sheila Vaidya
发明人： Ellis N. Fuls , Nadia Lifshitz , Sheila Vaidya
IPC分类号： H01L29/78 , H01L21/225 , H01L21/285 , H01L21/3215 , H01L21/336 , H01L21/768 , H01L21/8234 , H01L27/088 , H01L29/43 , H01L21/74 , H01L21/265
CPC分类号： H01L21/32155 , H01L21/2257 , H01L21/28518 , H01L21/76889
摘要： In an MOS integrated circuit device, a multilayer polysilicon/metallic-silicide gate-level metallization structure is patterned to form gates and associated interconnects. Some of the interconnects are designed to make contact with ohmic regions in the single-crystalline body of the device. In accordance with a simplified fabrication procedure, a single implantation step is utilized to dope the metallic silicide while doping selected portions of the body. During a subsequent heating step, source, drain and ohmic contact regions are formed in the body. During the same step, the dopant in the metallic silicide diffuses into underlying layers of polysilicon and into body portions directly underlying polysilicon in amounts sufficient to render the polysilicon conductive and to form additional ohmic contact regions in the body.
摘要翻译：在MOS集成电路器件中，多层多晶硅/金属硅化物栅极级金属化结构被图案化以形成栅极和相关联的互连。一些互连件被设计成与装置的单晶体体中的欧姆区域接触。根据简化的制造过程，使用单个注入步骤来掺杂金属硅化物，同时掺杂身体的选定部分。在随后的加热步骤期间，在体内形成源极，漏极和欧姆接触区域。在相同的步骤中，金属硅化物中的掺杂剂扩散到多晶硅的下面的层中，并且以足以使多晶硅导电并在体内形成额外的欧姆接触区域的量直接在多晶硅下面的主体部分中扩散。

2. 发明授权

US07880505B2 Low power reconfigurable circuits with delay compensation 有权
标题翻译：具有延迟补偿功能的低功率可重构电路
公开(公告)号：US07880505B2
公开(公告)日：2011-02-01
申请号：US12709227
申请日：2010-02-19
申请人： Sunil Papanchand Khatri , Sheila Vaidya , Timothy Kevin Griffin , Nikhil Jayakumar
发明人： Sunil Papanchand Khatri , Sheila Vaidya , Timothy Kevin Griffin , Nikhil Jayakumar
IPC分类号： H03K19/00
CPC分类号： H03K19/17736 , H03K19/17784
摘要： According to one aspect of the present disclosure, a circuit includes a semiconductor device including a plurality of logic blocks and a plurality of programmable interconnects. A delay detector generates a delay signal responsive to a measured delay of an output signal, wherein the output signal is from at least one of the plurality of logic blocks. A biasing circuit responsive to the delay signal to adjust subsequent measured delays toward a predetermined value.
摘要翻译：根据本公开的一个方面，电路包括包括多个逻辑块和多个可编程互连的半导体器件。响应于测量的输出信号的延迟，延迟检测器产生延迟信号，其中输出信号来自多个逻辑块中的至少一个。响应于延迟信号的偏置电路将随后的测量延迟调整到预定值。

3. 发明授权

US5153083A Method of making phase-shifting lithographic masks 失效
标题翻译：制造相移立体掩模的方法
公开(公告)号：US5153083A
公开(公告)日：1992-10-06
申请号：US622687
申请日：1990-12-05
申请人： Joseph G. Garofalo , Robert L. Kostelak, Jr. , Sheila Vaidya
发明人： Joseph G. Garofalo , Robert L. Kostelak, Jr. , Sheila Vaidya
IPC分类号： G03F1/29 , H01L21/027 , H01L21/306
CPC分类号： G03F1/29
摘要： Phase-shifting (two-optical-level) masks are manufactured by a self-aligned technique in which after first-level trenches in the mask have been formed, second-level trenches therein are formed by patterning an electron resist overlying the mask in such a manner that the edges of the patterned resist can be located anywhere within the first-level trenches, whereby the need for precise alignment of the resist patterning for the second-level trenches is avoided.

4. 再颁专利

USRE35753E Optical lithographical imaging system including optical transmission diffraction devices 失效
$Optical lithographical imaging system including optical transmission diffraction devices$
标题翻译：光学光学成像系统包括光学透射衍射装置
公开(公告)号：USRE35753E
公开(公告)日：1998-03-24
申请号：US648796
申请日：1996-05-16
申请人： Eric L. Raab , Sheila Vaidya , Donald L. White
发明人： Eric L. Raab , Sheila Vaidya , Donald L. White
IPC分类号： G03F7/20 , H01L21/027 , G03F9/00
CPC分类号： G03F7/70241 , G03F7/70108 , G03F7/70125 , G03F7/70158
摘要： In an optical lithographical system (e.g., 100) for printing features of a patterned mask (e.g., 103) into a workpiece (e.g., 120), such as in a semiconductor device, a one- or two-dimensional (depending on the features of the mask) optical transmission phase-shift diffracting device (e.g., 107) is inserted between an optical condensor (e.g., 105) and the patterned mask whose features are to be printed into the workpiece. The diffracting device is designed so as to enable an imaging lens system (e.g., 102) to collect more than merely a single order of the resulting diffraction patterns of the features of the mask and, by varying the spatial periodicity of the diffracting device, to tailor the illumination incident on the mask in accordance with the features (e.g., 114, 115) of the mask.
摘要翻译：在用于将图案化掩模（例如，103）的特征打印到工件（例如，120）中的光学系统（例如，100）中，例如在半导体器件中，一维或二维（取决于特征的光传输相移衍射装置（例如，107）被插入在光学聚光器（例如，105）和其特征被打印到工件中的图案化掩模之间。衍射装置被设计成使得成像透镜系统（例如，102）能够收集不仅仅是掩模的特征的所得到的衍射图案的单个顺序，并且通过将衍射装置的空间周期性改变为根据掩模的特征（例如，114,115）调整入射在掩模上的照明。

5. 发明授权

US5358827A Phase-shifting lithographic masks with improved resolution 失效
标题翻译：相移光刻胶片具有改进的分辨率
公开(公告)号：US5358827A
公开(公告)日：1994-10-25
申请号：US19973
申请日：1993-02-19
申请人： Joseph G. Garofalo , Robert L. Kostelak, Jr. , Sheila Vaidya
发明人： Joseph G. Garofalo , Robert L. Kostelak, Jr. , Sheila Vaidya
IPC分类号： G03F1/29 , G03F7/20 , H01L21/027 , G03F7/00
CPC分类号： G03F1/29 , G03F7/2002 , G03F7/70283
摘要： In order to print an isolated feature having a width W in a photoresist layer using an optical radiation imaging system whose lateral magnification is equal to m, a phase-shifting mask is used having a corresponding isolated feature. In one embodiment this corresponding isolated feature has a central square portion having a refractive index n.sub.1 and a thickness t.sub.1, and a peripheral (rim) square-ring phase-shifting portion having a width B, as well as a refractive index n.sub.2 and a thickness t.sub.2, such that the phase-shift .phi.=2.pi.(n.sub.2 t.sub.2 -n.sub.1 t.sub.1)/.lambda. of the central portion relative to the peripheral portion is equal to .pi. radian or odd multiple integral thereof. The width C of the central portion advantageously is selected such that mC/W is equal to at least 1.2, and preferably greater than 1.5, rather than unity. In another embodiment, the isolated feature has an opaque central portion, also of width C, and a peripheral square-ring phase-shifting portion having a width B and having a phase-shift of .pi. radian relative to a surrounding transparent wide area ("bright field")--in which case, advantageously the value of m(C+2B)/W is equal to less than 1/(1.2), and preferably less than 1/(1.5).
摘要翻译：为了使用其横向放大倍率等于m的光辐射成像系统在光致抗蚀剂层中印刷具有宽度W的孤立特征，使用具有相应隔离特征的相移掩模。在一个实施例中，该对应的隔离特征具有折射率n1和厚度t1的中心正方形部分和具有宽度B的外围（边缘）方形相移部分以及折射率n2和厚度 t2，使得相对于周边部分的中心部分的相移phi =2π（n2t2-n1t1）/λ等于pi弧度或奇数倍积分。有利地选择中心部分的宽度C使得mC / W等于至少1.2，优选大于1.5而不是一致。在另一个实施例中，隔离特征具有也具有宽度C的不透明中心部分和具有宽度B并且具有相对于周围透明宽区域（“弧度”）的相位偏移的周边方形环相移部分“ 亮场“） - 在这种情况下，有利地，m（C + 2B）/ W的值等于小于1 /（1.2），优选小于1 /（1.5）。

6. 发明授权

US4438450A Solid state device with conductors having chain-shaped grain structure 失效
标题翻译：固态器件，导体具有链状晶粒结构
公开(公告)号：US4438450A
公开(公告)日：1984-03-20
申请号：US328149
申请日：1981-12-07
申请人： Tan T. Sheng , Ashok K. Sinha , Sheila Vaidya
发明人： Tan T. Sheng , Ashok K. Sinha , Sheila Vaidya
IPC分类号： H01L21/3205 , H01L23/532 , H01L23/48 , H01L29/44 , H01L29/46 , H01L29/62
CPC分类号： H01L23/532 , H01L21/32051 , H01L2924/0002
摘要： Aluminum electrically conducting patterns for integrated circuits are achieved with narrow lines and unexpectedly-high electromigration characteristics by making the crystal grains of the pattern into a chain-shaped structure with {111} orientation. A process for achieving the structure is also described.
摘要翻译：用于集成电路的铝导电图案通过使图案的晶粒成为具有{111}取向的链状结构而实现具有窄线和意想不到的高电迁移特性。还描述了用于实现该结构的过程。

7. 发明授权

US5275896A Single-alignment-level lithographic technique for achieving self-aligned features 失效
标题翻译：用于实现自对准特征的单对准级光刻技术
公开(公告)号：US5275896A
公开(公告)日：1994-01-04
申请号：US943980
申请日：1992-09-11
申请人： Joseph G. Garofalo , Robert L. Kostelak, Jr. , Christophe Pierrat , Sheila Vaidya
发明人： Joseph G. Garofalo , Robert L. Kostelak, Jr. , Christophe Pierrat , Sheila Vaidya
IPC分类号： G03F1/00 , H01L21/027 , H01L21/30 , G03F7/20 , G03F9/00
CPC分类号： G03F1/29 , G03F1/30 , Y10S430/143
摘要： A phase-shifting lithographic mask is made by a procedure involving only a single patterned electron, ion, or photon beam bombardment of a resist layer. The bombardment is arranged to produce three kinds of regions in the resist: no dosage, low dosage, and high dosage. These three regions in the resist are then utilized--in conjunction with an ordinary wet development step followed by either a silylation or an optical flooding technique, and thereafter by another ordinary wet development step--to pattern the resist layer and thereby to enable forming, by dry or wet etching, an underlying double layer consisting of a patterned opaque layer and a patterned transparent phase-shifting layer, the phase-shifting layer being located on, or being part of, a transparent substrate.
摘要翻译：通过仅涉及抗蚀剂层的单一图案化电子，离子或光子束轰击的过程来制造相移光刻掩模。这种轰炸安排在抗蚀剂中生产三种区域：无剂量，低剂量，高剂量。然后将抗蚀剂中的这三个区域与普通的湿式显影步骤一起使用，然后进行甲硅烷基化或光驱技术，然后通过另一个普通的湿式显影步骤 - 对抗蚀剂层进行图案化，从而能够通过干或湿蚀刻，由图案化的不透明层和图案化的透明移相层组成的底层双层，所述移相层位于透明衬底上，或者是透明衬底的一部分。

8. 发明授权

US4992394A Self aligned registration marks for integrated circuit fabrication 失效
标题翻译：用于集成电路制造的自对准对准标记
公开(公告)号：US4992394A
公开(公告)日：1991-02-12
申请号：US387721
申请日：1989-07-31
申请人： Robert L. Kostelak, Jr. , William T. Lynch , Sheila Vaidya
发明人： Robert L. Kostelak, Jr. , William T. Lynch , Sheila Vaidya
IPC分类号： H01L29/73 , H01L21/027 , H01L21/30 , H01L21/331 , H01L21/8249 , H01L23/544 , H01L27/06 , H01L29/732
CPC分类号： H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , Y10S438/975
摘要： In order to reduce alignment errors arising in the fabrication of semiconductor integrated circuits using electron beam lithography, enhanced registration marks--(i.e., registration marks that are more easily and accurately detectable by the electron beam)--are formed at the edges of oxide layers, located at the surface of a silicon body, by means of forming metal silicide layers having edges coincident with the edges of the oxide layers. Advantageously, the enhancing of the registgration marks by forming the metal silicide is performed subsequent to any high temperature processing steps, whereby the integrity of the marks is maintained.
摘要翻译：为了减少在使用电子束光刻的半导体集成电路的制造中产生的对准误差，在氧化物层的边缘处形成增强的对准标记（即，由电子束更容易和精确地检测的对准标记）通过形成具有与氧化物层的边缘重合的边缘的金属硅化物层，位于硅体的表面。有利的是，在任何高温处理步骤之后执行通过形成金属硅化物来增强注册标记，从而保持标记的完整性。

9. 发明授权

US4555842A Method of fabricating VLSI CMOS devices having complementary threshold voltages 失效
标题翻译：制造具有互补阈值电压的VLSI CMOS器件的方法
公开(公告)号：US4555842A
公开(公告)日：1985-12-03
申请号：US591274
申请日：1984-03-19
申请人： Hyman J. Levinstein , Sheila Vaidya
发明人： Hyman J. Levinstein , Sheila Vaidya
IPC分类号： H01L29/78 , H01L21/28 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L27/092 , H01L29/49 , H01L21/265 , H01L21/22
CPC分类号： H01L21/823842 , H01L29/4916 , H01L29/4933 , H01L27/0928 , Y10S148/082
摘要： For optimal performance, the threshold voltages V.sub.TP and V.sub.TN of the p- and n-channel transistors in a CMOS device should be the respective complements of each other. In polysilicon-gate devices, this can be achieved by adjusting the corresponding gate-metal work function utilizing p.sup.+ and n.sup.+ polysilicon for the respective gates of the p- and n-channel transistors. However, when a refractory metal silicide-over-polysilicon gate structure is employed in a VLSI CMOS device in which the gates of a pair of adjacent complementary transistors are connected together, an anomalously large negative V.sub.TP is measured.The invention is a unique process sequence that achieves substantially complementary p- and n-channel transistor thresholds in a high-speed VLSI CMOS device that includes silicide-over-polysilicon gates.
摘要翻译：为了获得最佳性能，CMOS器件中p沟道晶体管和n沟道晶体管的阈值电压VTP和VTN应相互补充。在多晶硅栅极器件中，这可以通过利用p +和n +多晶硅来调整p型和n型多晶硅的相应栅极金属功函数来实现，用于p沟道晶体管和n沟道晶体管的各个栅极。然而，当在一对相邻互补晶体管的栅极连接在一起的VLSI CMOS器件中采用难熔金属硅化物多晶硅栅极结构时，测量异常大的负VTP。本发明是在包括硅化物多晶硅栅极的高速VLSI CMOS器件中实现基本上互补的p沟道和n沟道晶体管阈值的独特工艺序列。

10. 发明申请

US20100213978A1 LOW POWER RECONFIGURABLE CIRCUITS WITH DELAY COMPENSATION 有权
标题翻译：具有延迟补偿功能的低功率可重新连接电路
公开(公告)号：US20100213978A1
公开(公告)日：2010-08-26
申请号：US12709227
申请日：2010-02-19
申请人： Sunil Papanchand Khatri , Sheila Vaidya , Timothy Kevin Griffin , Nikhil Jayakumar
发明人： Sunil Papanchand Khatri , Sheila Vaidya , Timothy Kevin Griffin , Nikhil Jayakumar
IPC分类号： H03K19/177 , H03H11/26
CPC分类号： H03K19/17736 , H03K19/17784
摘要： According to one aspect of the present disclosure, a circuit includes a semiconductor device including a plurality of logic blocks and a plurality of programmable interconnects. A delay detector generates a delay signal responsive to a measured delay of an output signal, wherein the output signal is from at least one of the plurality of logic blocks. A biasing circuit responsive to the delay signal to adjust subsequent measured delays toward a predetermined value.
摘要翻译：根据本公开的一个方面，电路包括包括多个逻辑块和多个可编程互连的半导体器件。响应于测量的输出信号的延迟，延迟检测器产生延迟信号，其中输出信号来自多个逻辑块中的至少一个。响应于延迟信号的偏置电路将随后的测量延迟调整到预定值。

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