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    • 2. 发明申请
    • Magnetic Relaxometry using Brownian Randomization, Neel Relaxation, or Combinations Thereof
    • 使用布朗随机化,神经松弛或其组合的磁放松测量
    • US20130289383A1
    • 2013-10-31
    • US13871683
    • 2013-04-26
    • Edward R. FlynnVictor Gerald Grafe
    • Edward R. FlynnVictor Gerald Grafe
    • A61B5/05
    • A61B5/05A61B5/0515
    • The present invention can provide a method of determining the communication of substances between a first region and a second region of a patient's body. An example method according to the present invention can comprise: (a) introducing into the first region a plurality of superparamagnetic nanoparticles, having properties such that they undergo Brownian motion that randomizes the orientation of the nanoparticles according to a predetermined characteristic time; (b) after a time sufficient to allow transport of nanoparticles from the first region to the second region, subjecting the second region to an applied magnetic field of sufficient strength to induce magnetization of individual nanoparticles, and having a substantially uniform direction throughout the second region; (c) measuring the magnetic field of the second region at a plurality of times after ceasing application of the magnetic field; (d) analyzing the measured magnetic field to detect signals that correspond to decay of the magnetic field due to randomization of the nanoparticles' orientation by Brownian motion; (e) determining the presence of nanoparticles in the second region from the signals detected in step (d).
    • 本发明可以提供一种确定患者身体的第一区域和第二区域之间的物质的通信的方法。 根据本发明的示例性方法可以包括:(a)将多个超顺磁性纳米颗粒引入第一区域,其具有使得它们经历布朗运动的性质,使得根据预定特征时间随机化纳米颗粒的取向; (b)在足以允许纳米颗粒从第一区域运输到第二区域的时间之后,使第二区域经受足够强度的施加磁场,以引起单个纳米颗粒的磁化,并且在整个第二区域具有基本均匀的方向 ; (c)在停止施加磁场之后多次测量第二区域的磁场; (d)分析测量的磁场以检测由于通过布朗运动随机化纳米颗粒取向而对应于磁场衰减的信号; (e)从步骤(d)中检测到的信号确定第二区域中纳米颗粒的存在。
    • 6. 发明授权
    • Direct match data flow memory for data driven computing
    • 直接匹配用于数据驱动计算的数据流存储器
    • US5675757A
    • 1997-10-07
    • US403612
    • 1995-03-14
    • George S. DavidsonVictor Gerald Grafe
    • George S. DavidsonVictor Gerald Grafe
    • G06F15/82G06F9/44G06F13/00
    • G06F9/4436
    • A data flow computer and method of computing is disclosed which utilizes a data driven processor node architecture. The apparatus in a preferred embodiment includes a plurality of First-In-First-Out (FIFO) registers, a plurality of related data flow memories, and a processor. The processor makes the necessary calculations and includes a control unit to generate signals to enable the appropriate FIFO register receiving the result. In a particular embodiment, there are three FIFO registers per node: an input FIFO register to receive input information form an outside source and provide it to the data flow memories; an output FIFO register to provide output information from the processor to an outside recipient; and an internal FIFO register to provide information from the processor back to the data flow memories. The data flow memories are comprised of four commonly addressed memories. A parameter memory holds the A and B parameters used in the calculations; an opcode memory holds the instruction; a target memory holds the output address; and a tag memory contains status bits for each parameter. One status bit indicates whether the corresponding parameter is in the parameter memory and one status bit to indicate whether the stored information in the corresponding data parameter is to be reused. The tag memory outputs a "fire" signal (signal R VALID) when all of the necessary information has been stored in the data flow memories, and thus when the instruction is ready to be fired to the processor.
    • 公开了一种利用数据驱动的处理器节点架构的数据流计算机和计算方法。 优选实施例中的装置包括多个先进先出(FIFO)寄存器,多个相关数据流存储器和处理器。 处理器进行必要的计算,并包括一个控制单元来产生信号,使相应的FIFO寄存器能够接收结果。 在特定实施例中,每个节点有三个FIFO寄存器:输入FIFO寄存器,用于从外部源接收输入信息并将其提供给数据流存储器; 输出FIFO寄存器,用于从处理器向外部接收者提供输出信息; 以及内部FIFO寄存器,用于将来自处理器的信息提供回数据流存储器。 数据流存储器由四个通常被寻址的存储器组成。 参数存储器保存计算中使用的A和B参数; 操作码存储器保存指令; 目标存储器保存输出地址; 标签存储器包含每个参数的状态位。 一个状态位指示相应的参数是否在参数存储器中,一个状态位指示是否重新使用相应数据参数中存储的信息。 当所有必要信息已经存储在数据流存储器中时,标签存储器输出“火”信号(信号R VALID),并且因此当指令准备被触发到处理器时。
    • 7. 发明授权
    • Direct match data flow machine apparatus and process for data driven
computing
    • 直接匹配数据流机器和数据驱动计算过程
    • US5657465A
    • 1997-08-12
    • US403603
    • 1995-03-14
    • George S. DavidsonVictor Gerald Grafe
    • George S. DavidsonVictor Gerald Grafe
    • G06F15/82G06F9/44G06F13/00
    • G06F9/4436
    • A data flow computer and method of computing is disclosed which utilizes a data driven processor node architecture. The apparatus in a preferred embodiment includes a plurality of First-In-First-Out (FIFO) registers, a plurality of related data flow memories, and a processor. The processor makes the necessary calculations and includes a control unit to generate signals to enable the appropriate FIFO register receiving the result. In a particular embodiment, there are three FIFO registers per node: an input FIFO register to receive input information form an outside source and provide it to the data flow memories; an output FIFO register to provide output information from the processor to an outside recipient; and an internal FIFO register to provide information from the processor back to the data flow memories. The data flow memories are comprised of four commonly addressed memories. A parameter memory holds the A and B parameters used in the calculations; an opcode memory holds the instruction; a target memory holds the output address; and a tag memory contains status bits for each parameter. One status bit indicates whether the corresponding parameter is in the parameter memory and one status but to indicate whether the stored information in the corresponding data parameter is to be reused. The tag memory outputs a "fire" signal (signal R VALID) when all of the necessary information has been stored in the data flow memories, and thus when the instruction is ready to be fired to the processor.
    • 公开了一种利用数据驱动的处理器节点架构的数据流计算机和计算方法。 优选实施例中的装置包括多个先进先出(FIFO)寄存器,多个相关数据流存储器和处理器。 处理器进行必要的计算,并包括一个控制单元来产生信号,使相应的FIFO寄存器能够接收结果。 在特定实施例中,每个节点有三个FIFO寄存器:输入FIFO寄存器,用于从外部源接收输入信息并将其提供给数据流存储器; 输出FIFO寄存器,用于从处理器向外部接收者提供输出信息; 以及内部FIFO寄存器,用于将来自处理器的信息提供回数据流存储器。 数据流存储器由四个通常被寻址的存储器组成。 参数存储器保存计算中使用的A和B参数; 操作码存储器保存指令; 目标存储器保存输出地址; 标签存储器包含每个参数的状态位。 一个状态位指示相应的参数是否在参数存储器中,并且一个状态,而是指示是否重新使用相应数据参数中存储的信息。 当所有必要信息已经存储在数据流存储器中时,标签存储器输出“火”信号(信号R VALID),并且因此当指令准备被触发到处理器时。