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2. 发明授权

US06603829B1 Programmable phase matching 失效
标题翻译：可编程相位匹配
公开(公告)号：US06603829B1
公开(公告)日：2003-08-05
申请号：US09403513
申请日：1999-10-22
申请人： Winfried Gläser , Rudi Müller
发明人： Winfried Gläser , Rudi Müller
IPC分类号： H04L7033
CPC分类号： H04L7/0338 , H03L7/0814 , H04L7/0083
摘要： In a phase matching circuit for generating a system clock signal for an incoming data signal from a locally existing clock signal, a delay signal is calculated from the detected phase position of the data signal in that a memory addressed with the detected phase position outputs an allocated delay signal. In a specific embodiment, the memory is supplied with an address that is compensated by the most recently identified delay. In a further development, a control comprising the memory shares circuits for a number of data signals. The phase matching, which automatically recognizes a jitter compatibility more suitable for the clocking than the jitter compatibility employed at the moment, can be completely integrated and avoids circuit areas that are operated with a higher bit repetition rate than that of the clock signal.
摘要翻译：在用于从本地存在的时钟信号产生用于输入数据信号的系统时钟信号的相位匹配电路中，根据检测到的数据信号的相位位置计算延迟信号，因为用检测到的相位位置寻址的存储器输出分配延迟信号。在具体实施例中，向存储器提供由最近识别的延迟补偿的地址。在进一步的发展中，包括用于多个数据信号的存储器共享电路的控制。可以完全集成相位匹配，其自动识别比当前使用的抖动兼容性更适合于时钟的抖动兼容性，并避免以比时钟信号更高的比特重复率操作的电路区域。

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