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1. 发明授权

US08208335B2 Semiconductor memory device and system including the same 有权
标题翻译：半导体存储器件及其系统
公开(公告)号：US08208335B2
公开(公告)日：2012-06-26
申请号：US12821515
申请日：2010-06-23
申请人： Dong-Hyuk Lee , Jung-Bae Lee , Doo-Gon Kim , Cheol Kim
发明人： Dong-Hyuk Lee , Jung-Bae Lee , Doo-Gon Kim , Cheol Kim
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C11/401 , G11C11/406 , G11C11/40618 , G11C11/40622 , G11C29/24 , G11C29/50016 , G11C2211/4061
摘要： A semiconductor memory device includes a cell array unit having a plurality of banks each having a plurality of blocks, and a refresh controller configured to set at least one of the blocks as a test block, perform a refresh operation on the blocks except for the test block in a self-refresh operation period, determine a refresh period of the test block, and then set another one of the blocks as the test block.
摘要翻译：半导体存储器件包括具有多个块的单元阵列单元，每个单元具有多个块，以及刷新控制器，被配置为将至少一个块设置为测试块，对除了测试之外的块执行刷新操作在自刷新操作期间块，确定测试块的刷新周期，然后将另一个块设置为测试块。

2. 发明申请

US20110116335A1 SEMICONDUCTOR MEMORY DEVICE AND SYSTEM INCLUDING THE SAME 有权
标题翻译：半导体存储器件和系统，包括它们
公开(公告)号：US20110116335A1
公开(公告)日：2011-05-19
申请号：US12821515
申请日：2010-06-23
申请人： Dong Hyuk LEE , Jung-Bae Lee , Doo-Gon Kim , Cheol Kim
发明人： Dong Hyuk LEE , Jung-Bae Lee , Doo-Gon Kim , Cheol Kim
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C29/50 , G11C11/401 , G11C11/406 , G11C11/40618 , G11C11/40622 , G11C29/24 , G11C29/50016 , G11C2211/4061
摘要： A semiconductor memory device includes a cell array unit having a plurality of banks each having a plurality of blocks, and a refresh controller configured to set at least one of the blocks as a test block, perform a refresh operation on the blocks except for the test block in a self-refresh operation period, determine a refresh period of the test block, and then set another one of the blocks as the test block.
摘要翻译：半导体存储器件包括具有多个块的单元阵列单元，每个单元具有多个块，以及刷新控制器，被配置为将至少一个块设置为测试块，对除了测试之外的块执行刷新操作在自刷新操作期间块，确定测试块的刷新周期，然后将另一个块设置为测试块。

3. 发明授权

US08379477B2 Sub-word-line driving circuit, semiconductor memory device having the same, and method of controlling the same 有权
标题翻译：子字线驱动电路，具有其的半导体存储器件及其控制方法
公开(公告)号：US08379477B2
公开(公告)日：2013-02-19
申请号：US13019858
申请日：2011-02-02
申请人： Cheol Kim , Sang-Kyun Park , Jung-Bae Lee , Jun-Phyo Lee
发明人： Cheol Kim , Sang-Kyun Park , Jung-Bae Lee , Jun-Phyo Lee
IPC分类号： G11C8/10
CPC分类号： G11C8/14 , G11C8/08
摘要： Provided is a semiconductor memory device including a sub-word-line driving circuit capable of reducing an amount of leakage current due to coupling. The semiconductor memory device includes a word-line enable signal generating circuit and a sub-word-line driving circuit. The sub-word-line driving circuit provides a pull-down current path between a selected word line and ground for a pulse type period of time in a precharge mode following an active mode for the selected word line, generates a word line driving signal on the basis of a main word line driving signal, a first sub-word-line control signal, and a second sub-word-line control signal, and provides the word line driving signal to a memory cell array. The semiconductor memory device may reduce an amount of leakage current flowing to a ground through the sub-word-line driving circuit.
摘要翻译：提供了一种半导体存储器件，其包括能够减少由耦合引起的漏电流量的子字线驱动电路。半导体存储器件包括字线使能信号发生电路和子字线驱动电路。子字线驱动电路在所选字线的有效模式之后的预充电模式中的脉冲类型时段期间，在所选字线和地之间提供下拉电流路径，生成字线驱动信号主字线驱动信号的基础，第一子字线控制信号和第二子字线控制信号，并将字线驱动信号提供给存储单元阵列。半导体存储器件可以减少通过子字线驱动电路流向地的漏电流量。

4. 发明申请

US20130016574A1 SEMICONDUCTOR MEMORY DEVICE HAVING IMPROVED REFRESH CHARACTERISTICS 有权
标题翻译：具有改进的刷新特性的半导体存储器件
公开(公告)号：US20130016574A1
公开(公告)日：2013-01-17
申请号：US13548484
申请日：2012-07-13
申请人： Jung-sik Kim , Cheol Kim , Sang-ho Shin , Jung-bae Lee , Chan-yong Lee , Sung-min Yim , Tae-seong Jang , Joo-sun Choi
发明人： Jung-sik Kim , Cheol Kim , Sang-ho Shin , Jung-bae Lee , Chan-yong Lee , Sung-min Yim , Tae-seong Jang , Joo-sun Choi
IPC分类号： G11C29/08 , G11C7/00
CPC分类号： G11C29/50016 , G11C5/04 , G11C11/40 , G11C11/406 , G11C11/40615 , G11C11/40622 , G11C2211/4061 , G11C2211/4065
摘要： A semiconductor memory device having improved refresh characteristics includes a memory array including a plurality of memory cells; a test unit configured to test refresh characteristics of the memory array and generate a first fail address signal; a storage unit configured to store the first fail address signal; and a refresh unit configured to perform a refresh operation on the memory array, wherein the refresh unit is configured to receive the first fail address signal from the storage unit, perform the refresh operation on a first memory cell that does not correspond to the first fail address signal according to a first period, and perform the refresh operation on a second memory cell that corresponds to the first fail address signal according to a second period that is shorter than the first period.
摘要翻译：具有改进的刷新特性的半导体存储器件包括包括多个存储器单元的存储器阵列; 测试单元，被配置为测试所述存储器阵列的刷新特性并产生第一故障地址信号; 存储单元，被配置为存储所述第一失败地址信号; 以及刷新单元，被配置为对所述存储器阵列执行刷新操作，其中所述刷新单元被配置为从所述存储单元接收所述第一故障地址信号，对与所述第一故障不对应的第一存储器单元执行刷新操作根据第一期间的地址信号，根据比第一期间短的第二期间对与第一失败地址信号对应的第二存储单元进行刷新动作。

5. 发明申请

US20110228624A1 SUB-WORD-LINE DRIVING CIRCUIT, SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME, AND METHOD OF CONTROLLING THE SAME 有权
标题翻译：副线驱动电路，具有它们的半导体存储器件及其控制方法
公开(公告)号：US20110228624A1
公开(公告)日：2011-09-22
申请号：US13019858
申请日：2011-02-02
申请人： Cheol Kim , Sang-Kyun Park , Jung-Bae Lee , Jun-Phyo Lee
发明人： Cheol Kim , Sang-Kyun Park , Jung-Bae Lee , Jun-Phyo Lee
IPC分类号： G11C8/08
CPC分类号： G11C8/14 , G11C8/08
摘要： Provided is a semiconductor memory device including a sub-word-line driving circuit capable of reducing an amount of leakage current due to coupling. The semiconductor memory device includes a word-line enable signal generating circuit and a sub-word-line driving circuit. The sub-word-line driving circuit provides a pull-down current path between a selected word line and ground for a pulse type period of time in a precharge mode following an active mode for the selected word line, generates a word line driving signal on the basis of a main word line driving signal, a first sub-word-line control signal, and a second sub-word-line control signal, and provides the word line driving signal to a memory cell array. The semiconductor memory device may reduce an amount of leakage current flowing to a ground through the sub-word-line driving circuit.
摘要翻译：提供了一种半导体存储器件，其包括能够减少由耦合引起的漏电流量的子字线驱动电路。半导体存储器件包括字线使能信号产生电路和子字线驱动电路。子字线驱动电路在所选字线的有效模式之后的预充电模式中的脉冲类型时段期间，在所选字线和地之间提供下拉电流路径，生成字线驱动信号主字线驱动信号的基础，第一子字线控制信号和第二子字线控制信号，并将字线驱动信号提供给存储单元阵列。半导体存储器件可以减少通过子字线驱动电路流向地的漏电流量。

6. 发明授权

US09036439B2 Semiconductor memory device having improved refresh characteristics 有权
标题翻译：具有改善的刷新特性的半导体存储器件
公开(公告)号：US09036439B2
公开(公告)日：2015-05-19
申请号：US13548484
申请日：2012-07-13
申请人： Jung-sik Kim , Cheol Kim , Sang-ho Shin , Jung-bae Lee , Chan-yong Lee , Sung-min Yim , Tae-seong Jang , Joo-sun Choi
发明人： Jung-sik Kim , Cheol Kim , Sang-ho Shin , Jung-bae Lee , Chan-yong Lee , Sung-min Yim , Tae-seong Jang , Joo-sun Choi
IPC分类号： G11C29/08 , G11C7/00 , G11C29/50 , G11C11/406 , G11C5/04 , G11C11/40
CPC分类号： G11C29/50016 , G11C5/04 , G11C11/40 , G11C11/406 , G11C11/40615 , G11C11/40622 , G11C2211/4061 , G11C2211/4065
摘要： A semiconductor memory device having improved refresh characteristics includes a memory array including a plurality of memory cells; a test unit configured to test refresh characteristics of the memory array and generate a first fail address signal; a storage unit configured to store the first fail address signal; and a refresh unit configured to perform a refresh operation on the memory array, wherein the refresh unit is configured to receive the first fail address signal from the storage unit, perform the refresh operation on a first memory cell that does not correspond to the first fail address signal according to a first period, and perform the refresh operation on a second memory cell that corresponds to the first fail address signal according to a second period that is shorter than the first period.
摘要翻译：具有改进的刷新特性的半导体存储器件包括包括多个存储器单元的存储器阵列; 测试单元，被配置为测试所述存储器阵列的刷新特性并产生第一故障地址信号; 存储单元，被配置为存储所述第一失败地址信号; 以及刷新单元，被配置为对所述存储器阵列执行刷新操作，其中所述刷新单元被配置为从所述存储单元接收所述第一故障地址信号，对与所述第一故障不对应的第一存储器单元执行刷新操作根据第一期间的地址信号，根据比第一期间短的第二期间对与第一失败地址信号对应的第二存储单元进行刷新动作。

7. 发明申请

US20110199836A1 BIT-LINE SENSE AMPLIFIER, SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME, AND METHOD OF TESTING BIT-LINE MICRO-BRIDGE DEFECT 有权
标题翻译：双线感测放大器，具有相同功能的半导体存储器件以及测试位线微桥缺陷的方法
公开(公告)号：US20110199836A1
公开(公告)日：2011-08-18
申请号：US12958726
申请日：2010-12-02
申请人： Cheol Kim , Sang-Kyun Park , Jung-Bae Lee , Jun-Phyo Lee
发明人： Cheol Kim , Sang-Kyun Park , Jung-Bae Lee , Jun-Phyo Lee
IPC分类号： G11C29/12 , G11C7/10
CPC分类号： G11C11/4091 , G11C29/025 , G11C29/12005 , G11C29/1201 , G11C2029/1204
摘要： The bit-line sense amplifier includes a driving-voltage control circuit and an amplifier. The driving-voltage control circuit generates a first test driving voltage having a voltage level of a pre-charge voltage, a second test driving voltage having a voltage level of a pre-charge voltage added by a voltage difference between a bit-line and a complementary bit-line, and a third test driving voltage having a voltage level of a pre-charge voltage subtracted by the voltage difference in a test mode. The amplifier senses and amplifies a voltage difference between the bit-line and the complementary bit-line.
摘要翻译：位线读出放大器包括驱动电压控制电路和放大器。驱动电压控制电路产生具有预充电电压的电压电平的第一测试驱动电压，具有由位线和位线之间的电压差相加的预充电电压的电压电平的第二测试驱动电压以及第三测试驱动电压，其具有在测试模式下被电压差减去的预充电电压的电压电平。放大器感测并放大位线和互补位线之间的电压差。

8. 发明授权

US08395953B2 Bit-line sense amplifier, semiconductor memory device having the same, and method of testing bit-line micro-bridge defect 有权
标题翻译：位线读出放大器，具有相同的半导体存储器件以及测试位线微桥缺陷的方法
公开(公告)号：US08395953B2
公开(公告)日：2013-03-12
申请号：US12958726
申请日：2010-12-02
申请人： Cheol Kim , Sang-Kyun Park , Jung-Bae Lee , Jun-Phyo Lee
发明人： Cheol Kim , Sang-Kyun Park , Jung-Bae Lee , Jun-Phyo Lee
IPC分类号： G11C7/00
CPC分类号： G11C11/4091 , G11C29/025 , G11C29/12005 , G11C29/1201 , G11C2029/1204
摘要： The bit-line sense amplifier includes a driving-voltage control circuit and an amplifier. The driving-voltage control circuit generates a first test driving voltage having a voltage level of a pre-charge voltage, a second test driving voltage having a voltage level of a pre-charge voltage added by a voltage difference between a bit-line and a complementary bit-line, and a third test driving voltage having a voltage level of a pre-charge voltage subtracted by the voltage difference in a test mode. The amplifier senses and amplifies a voltage difference between the bit-line and the complementary bit-line.
摘要翻译：位线读出放大器包括驱动电压控制电路和放大器。驱动电压控制电路产生具有预充电电压的电压电平的第一测试驱动电压，具有由位线和位线之间的电压差相加的预充电电压的电压电平的第二测试驱动电压以及第三测试驱动电压，其具有在测试模式下被电压差减去的预充电电压的电压电平。放大器感测并放大位线和互补位线之间的电压差。

9. 发明授权

US09190407B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09190407B2
公开(公告)日：2015-11-17
申请号：US14569597
申请日：2014-12-12
申请人： Byoung-Ho Kwon , Cheol Kim , Ho-Young Kim , Se-Jung Park , Myeong-Cheol Kim , Bo-Kyeong Kang , Bo-Un Yoon , Jae-Kwang Choi , Si-Young Choi , Suk-Hoon Jeong , Geum-Jung Seong , Hee-Don Jeong , Yong-Joon Choi , Ji-Eun Han
发明人： Byoung-Ho Kwon , Cheol Kim , Ho-Young Kim , Se-Jung Park , Myeong-Cheol Kim , Bo-Kyeong Kang , Bo-Un Yoon , Jae-Kwang Choi , Si-Young Choi , Suk-Hoon Jeong , Geum-Jung Seong , Hee-Don Jeong , Yong-Joon Choi , Ji-Eun Han
IPC分类号： H01L27/088 , H01L29/78 , H01L29/66 , H01L21/8238 , H01L21/8234 , H01L29/49
CPC分类号： H01L29/7853 , H01L21/30604 , H01L21/3065 , H01L21/3085 , H01L21/823431 , H01L21/823437 , H01L21/823481 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/845 , H01L27/0886 , H01L27/1211 , H01L29/0673 , H01L29/42364 , H01L29/4238 , H01L29/49 , H01L29/66545 , H01L29/6656 , H01L29/66795 , H01L29/78 , H01L29/785
摘要： Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.
摘要翻译：半导体器件可以包括具有第一半导体鳍片的半导体衬底，第一半导体鳍片端对端与第二半导体对准，第二半导体在第一和第二半导体鳍片的相对端之间具有凹陷。第一绝缘体图案形成在第一和第二半导体鳍片的相邻侧壁附近，并且在第一凹部内形成第二绝缘体图案。第二绝缘体图案可以具有高于第一绝缘体图案的顶表面的顶表面，例如高于鳍片（或更高或更低）的顶表面的高度。第一和第二栅极沿第一半导体鳍片的侧壁和顶表面延伸。可以在第二绝缘体的顶表面上形成伪栅电极。还公开了其制造方法和修改方案。

10. 发明授权

US08916460B1 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08916460B1
公开(公告)日：2014-12-23
申请号：US14270315
申请日：2014-05-05
申请人： Byoung-Ho Kwon , Cheol Kim , Ho-Young Kim , Se-Jung Park , Myeong-Cheol Kim , Bo-Kyeong Kang , Bo-Un Yoon , Jae-Kwang Choi , Si-Young Choi , Suk-Hoon Jeong , Geum-Jung Seong , Hee-Don Jeong , Yong-Joon Choi , Ji-Eun Han
发明人： Byoung-Ho Kwon , Cheol Kim , Ho-Young Kim , Se-Jung Park , Myeong-Cheol Kim , Bo-Kyeong Kang , Bo-Un Yoon , Jae-Kwang Choi , Si-Young Choi , Suk-Hoon Jeong , Geum-Jung Seong , Hee-Don Jeong , Yong-Joon Choi , Ji-Eun Han
IPC分类号： H01L29/49 , H01L29/78 , H01L21/336 , H01L29/66 , H01L21/8238
CPC分类号： H01L29/7853 , H01L21/30604 , H01L21/3065 , H01L21/3085 , H01L21/823431 , H01L21/823437 , H01L21/823481 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/845 , H01L27/0886 , H01L27/1211 , H01L29/0673 , H01L29/42364 , H01L29/4238 , H01L29/49 , H01L29/66545 , H01L29/6656 , H01L29/66795 , H01L29/78 , H01L29/785
摘要： Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.
摘要翻译：半导体器件可以包括具有第一半导体鳍片的半导体衬底，第一半导体鳍片端对端与第二半导体对准，第二半导体在第一和第二半导体鳍片的相对端之间具有凹陷。第一绝缘体图案形成在第一和第二半导体鳍片的相邻侧壁附近，并且在第一凹部内形成第二绝缘体图案。第二绝缘体图案可以具有高于第一绝缘体图案的顶表面的顶表面，例如高于鳍片（或更高或更低）的顶表面的高度。第一和第二栅极沿第一半导体鳍片的侧壁和顶表面延伸。可以在第二绝缘体的顶表面上形成伪栅电极。还公开了其制造方法和修改方案。

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