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1. 发明授权

US06295584B1 Multiprocessor computer system with memory map translation 失效
标题翻译：具有内存映射转换的多处理器计算机系统
公开(公告)号：US06295584B1
公开(公告)日：2001-09-25
申请号：US08920673
申请日：1997-08-29
申请人： Donald R. DeSota , Bruce M. Gilbert , Thomas D. Lovett , Robert J. Safranek , Kenneth Frank Dove
发明人： Donald R. DeSota , Bruce M. Gilbert , Thomas D. Lovett , Robert J. Safranek , Kenneth Frank Dove
IPC分类号： G06F1200
CPC分类号： G06F12/0813 , G06F12/0284
摘要： An apparatus and method is disclosed for allowing a multiprocessor computer system with shared memory distributed among multiple nodes to appear like a single-node environment. The single-node environment is implemented with a memory map that has a unique address for every memory location in the system. Overlapping address spaces in the multinode environment are also assigned unique representative addresses that are translated to actual addresses in conformance with the multinode environment. The apparatus and method allows a wide variety of operating systems to be run on the multinode environment. Additionally, industry standard BIOS and chip sets can be used.
摘要翻译：公开了一种用于允许具有分布在多个节点之间的共享存储器的多处理器计算机系统看起来像单节点环境的装置和方法。单节点环境使用具有系统中每个存储单元的唯一地址的存储器映射来实现。多重节点环境中的重叠地址空间也被分配为唯一的代表地址，这些地址空间被转换为符合多节点环境的实际地址。该装置和方法允许在多节点环境中运行各种各样的操作系统。另外，可以使用行业标准的BIOS和芯片组。

2. 发明授权

US5900020A Method and apparatus for maintaining an order of write operations by processors in a multiprocessor computer to maintain memory consistency 失效
标题翻译：用于维护多处理器计算机中的处理器的写入操作顺序以维持存储器一致性的方法和装置
公开(公告)号：US5900020A
公开(公告)日：1999-05-04
申请号：US678372
申请日：1996-06-27
申请人： Robert J. Safranek , Thomas D. Lovett , Robert T. Joersz , Bruce M. Gilbert
发明人： Robert J. Safranek , Thomas D. Lovett , Robert T. Joersz , Bruce M. Gilbert
IPC分类号： G06F12/08 , G06F13/14 , G06F13/24 , G06F13/42
CPC分类号： G06F12/0828 , G06F12/0813 , G06F2212/2542
摘要： A method and apparatus for maintaining processor consistency in a multiprocessor computer such as a multinode computer system are disclosed. A processor proceeds with write operations before its previous write operations complete, while processor consistency is maintained. A write operation begins with a request by the processor to invalidate copies of the data stored in other nodes. This current invalidate request is queued while acknowledging to the processor that the request is complete even though it has not actually completed. The processor proceeds to complete the write operation by changing the data. It can then execute subsequent operations, including other write operations. The queued request, however, is not transmitted to other nodes in the computer until all previous invalidate requests by the processor are complete. This ensures that the current invalidate request will not pass a previous invalidate request. The invalidate requests are added and removed from a processor's outstanding invalidate list as they arise and are completed. An invalidate request is completed by notifying the nodes in a linked list related to the current invalidate request that data shared by the node is now invalid.
摘要翻译：公开了一种在诸如多节点计算机系统的多处理器计算机中维持处理器一致性的方法和装置。处理器在其先前的写入操作完成之前进行写入操作，同时保持处理器的一致性。写入操作从处理器的请求开始，使存储在其他节点中的数据的副本无效。该当前无效请求被排队，同时向处理器确认请求完成，即使它尚未实际完成。处理器继续通过更改数据来完成写入操作。然后，它可以执行后续操作，包括其他写入操作。然而，排队的请求不会传输到计算机中的其他节点，直到处理器的所有先前的无效请求都完成为止。这确保当前的无效请求不会通过先前的无效请求。无效请求在处理器未完成的无效列表出现并被完成时被添加和删除。通过通知与当前无效请求相关的链接列表中的节点，节点共享的数据现在无效，则完成无效请求。

3. 发明授权

US06493809B1 Maintaining order of write operations in a multiprocessor for memory consistency 失效
标题翻译：维护多处理器中写入操作的顺序，以保持内存一致性
公开(公告)号：US06493809B1
公开(公告)日：2002-12-10
申请号：US09493782
申请日：2000-01-28
申请人： Robert J. Safranek , Thomas D. Lovett
发明人： Robert J. Safranek , Thomas D. Lovett
IPC分类号： G06F1300
CPC分类号： G06F13/4243
摘要： A method of invalidating shared cache lines such as on a sharing list by issuing an invalidate acknowledgement before actually invalidating a cache line. The method is useful in multiprocessor systems such as a distributed shared memory (DSM) or non-uniform memory access (NUMA) machines that include a number of interconnected processor nodes each having local memory and caches that store copies of the same data. In such a multiprocessor system using the Scalable Content Interface (SCI) protocol, an invalidate request is sent from the head node on the sharing list to a succeeding node on the list. In response to the invalidate request, the succeeding node issues an invalidate acknowledgement before the cache line is actually invalidated. After issuing the invalidate acknowledgement, the succeeding node initiates invalidation of the cache line. The invalidate acknowledgement can take the form of a response to the head node or a forwarding of the invalidate request to the next succeeding node on the list. To maintain processor consistency, a flag is set each time an invalidate acknowledgement is sent. The flag is cleared after the invalidation of the cache line is completed. Cacheable transactions received at the succeeding node while a flag is set are delayed until the flag is cleared.
摘要翻译：一种使共享高速缓存行无效化的方法，例如在共享列表上通过在实际使高速缓存行无效之前发出无效确认。该方法在诸如分布式共享存储器（DSM）或非均匀存储器访问（NUMA）机器的多处理器系统中是有用的，其包括多个互连的处理器节点，每个互连处理器节点具有存储相同数据的副本的本地存储器和高速缓存。在使用可伸缩内容接口（SCI）协议的这种多处理器系统中，将无效请求从共享列表上的头节点发送到列表上的后续节点。响应于无效请求，后续节点在高速缓存行实际无效之前发出无效确认。发出无效确认后，后续节点启动高速缓存行的无效。无效确认可以采取对头节点的响应的形式或将无效请求转发到列表上的下一个后续节点。为了保持处理器的一致性，每次发送无效确认时都会设置一个标志。标志在高速缓存行无效完成后被清除。在设置标志时在后续节点处接收的可缓存事务被延迟直到该标志被清除。

4. 发明授权

US06041376A Distributed shared memory system having a first node that prevents other nodes from accessing requested data until a processor on the first node controls the requested data 失效
标题翻译：具有第一节点的分布式共享存储器系统，其防止其他节点访问所请求的数据，直到第一节点上的处理器控制所请求的数据
公开(公告)号：US06041376A
公开(公告)日：2000-03-21
申请号：US850736
申请日：1997-04-24
申请人： Bruce Michael Gilbert , Robert T. Joersz , Thomas D. Lovett , Robert J. Safranek
发明人： Bruce Michael Gilbert , Robert T. Joersz , Thomas D. Lovett , Robert J. Safranek
IPC分类号： G06F12/08 , G06F13/16 , G06F13/364
CPC分类号： G06F12/0815 , G06F13/1663 , G06F12/0813
摘要： A multiprocessor system that assures forward progress of local processor requests for data by preventing other nodes from accessing the data until the processor request is satisfied. In one aspect of the invention, the local processor requests data through a remote cache interconnect. The remote cache interconnect tells the local processor to retry its request for data at a later time, so that the remote cache interconnect has sufficient time to obtain the data from the system interconnect. When the remote cache interconnect receives the data from the system interconnect, a hold flag is set. Any requests from other nodes for the data are rejected while the hold flag is set. When the local processor issues a retry request, the data is delivered to the processor and the hold flag is cleared. Other nodes may then obtain control of the data.
摘要翻译：一种多处理器系统，通过防止其他节点访问数据直到满足处理器请求，确保本地处理器对数据的请求的正向进展。在本发明的一个方面，本地处理器通过远程高速缓存互连来请求数据。远程缓存互连告诉本地处理器稍后重试其对数据的请求，使得远程高速缓存互连具有足够的时间从系统互连获取数据。当远程缓存互连从系统互连接收数据时，设置保持标志。来自其他节点的任何数据请求将在保持标志置1时被拒绝。当本地处理器发出重试请求时，数据被传递给处理器，并且保持标志被清除。其他节点可以获得数据的控制。

5. 发明授权

US09442879B2 Multiple transaction data flow control unit for high-speed interconnect 有权
标题翻译：用于高速互连的多事务数据流控制单元
公开(公告)号：US09442879B2
公开(公告)日：2016-09-13
申请号：US13994128
申请日：2011-12-07
申请人： Robert J. Safranek , Robert G. Blankenship , Debendra Das Sharma
发明人： Robert J. Safranek , Robert G. Blankenship , Debendra Das Sharma
IPC分类号： G06F13/42 , G06F13/14 , G06F13/38 , G06F13/00 , H04L12/00
CPC分类号： G06F13/4282 , G06F12/0831 , G06F13/00 , G06F13/14 , G06F13/38 , G06F13/4234 , G06F13/426 , G06F15/781 , G06F2212/621 , G06F2213/0008 , G06F2213/0024 , G06F2213/0026 , H04L12/00
摘要： Methods, apparatus, and systems, for transporting data units comprising multiple pieces of transaction data over high-speed interconnects. A flow control unit, called a KTI (Keizer Technology Interface) Flit, is implemented in a coherent multi-layer protocol supporting coherent memory transactions. The KTI Flit has a basic format that supports use of configurable fields to implement KTI Flits with specific formats that may be used for corresponding transactions. In one aspect, the KTI Flit may be formatted as multiple slots used to support transfer of multiple respective pieces of transaction data in a single Flit. The KTI Flit can also be configured to support various types of transactions and multiple KTI Flits may be combined into packets to support transfer of data such as cache line transfers.
摘要翻译：用于通过高速互连传输包括多条交易数据的数据单元的方法，装置和系统。称为KTI（Keizer Technology Interface）的流量控制单元以支持相干存储器事务的相干多层协议实现。 KTI Flit具有一种基本格式，支持使用可配置字段来实现可用于相应事务的特定格式的KTI Flits。在一个方面，KTI Flit可以被格式化为用于支持在单个Flit中传送多个相应交易数据的多个时隙。 KTI Flit也可以配置为支持各种类型的事务，并且可以将多个KTI Flits组合成数据包，以支持数据传输，如缓存线传输。

6. 发明授权

US08473567B2 Generating a packet including multiple operation codes 有权
标题翻译：生成包含多个操作码的数据包
公开(公告)号：US08473567B2
公开(公告)日：2013-06-25
申请号：US12748644
申请日：2010-03-29
申请人： Phanindra K. Mannava , Hari K. Nagpal , Meenakshisundaram R. Chinthamani , Robert J. Safranek
发明人： Phanindra K. Mannava , Hari K. Nagpal , Meenakshisundaram R. Chinthamani , Robert J. Safranek
IPC分类号： G06F15/167 , G06F15/16
CPC分类号： H04L67/2842 , H04L65/607
摘要： In one embodiment, the present invention includes a processor that can generate data packets for transmission to an agent, where the processor can generate a data packet having a command portion including a first operation code to encode a transaction type for the data packet and a second operation code to encode a processor-specific operation. This second operation code can encode many different features such as an indication that the data packet is of a smaller size than a standard packet, in order to reduce bandwidth. This operation code can also identify an operation to be performed by a destination agent coupled to the agent. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括处理器，其可以生成用于传输到代理的数据分组，其中处理器可以生成具有命令部分的数据分组，该命令部分包括第一操作码以对数据分组进行交易类型的编码，用于编码处理器特定操作的操作代码。该第二操作代码可以编码许多不同的特征，例如数据分组具有比标准分组更小的尺寸的指示，以便减少带宽。该操作代码还可以识别由代理耦合的目的地代理执行的操作。描述和要求保护其他实施例。

7. 发明申请

US20120317369A1 SATISFYING MEMORY ORDERING REQUIREMENTS BETWEEN PARTIAL READS AND NON-SNOOP ACCESSES 有权
标题翻译：在部分阅读和非SNOOP访问之间满足记忆订购要求
公开(公告)号：US20120317369A1
公开(公告)日：2012-12-13
申请号：US13591157
申请日：2012-08-21
申请人： Robert H. Beers , Ching- Tsun Chou , Robert J. Safranek , James Vash
发明人： Robert H. Beers , Ching- Tsun Chou , Robert J. Safranek , James Vash
IPC分类号： G06F12/08
CPC分类号： G06F12/0833 , G06F12/0806 , G06F12/0813 , G06F12/0824 , G06F12/0831 , G06F12/128 , G06F2212/2542 , G06F2212/62 , G06F2212/621 , G06F2212/69 , G06F2212/70 , H04L67/28 , H04L67/2842
摘要： A method and apparatus for preserving memory ordering in a cache coherent link based interconnect in light of partial and non-coherent memory accesses is herein described. In one embodiment, partial memory accesses, such as a partial read, is implemented utilizing a Read Invalidate and/or Snoop Invalidate message. When a peer node receives a Snoop Invalidate message referencing data from a requesting node, the peer node is to invalidate a cache line associated with the data and is not to directly forward the data to the requesting node. In one embodiment, when the peer node holds the referenced cache line in a Modified coherency state, in response to receiving the Snoop Invalidate message, the peer node is to writeback the data to a home node associated with the data.
摘要翻译：这里描述了一种基于部分和非相干存储器访问的基于高速缓存基于相干链路的互连中的存储器排序的方法和装置。在一个实施例中，使用Read Invalidate和/或Snoop Invalidate消息来实现部分存储器访问，诸如部分读取。当对等节点接收到从请求节点引用数据的Snoop Invalidate消息时，对等节点将使与数据相关联的高速缓存行无效，并且不将数据直接转发到请求节点。在一个实施例中，当对等节点保持被修改的一致性状态下的被引用高速缓存行时，响应于接收到无效无效消息，对等节点将该数据写回到与该数据相关联的家庭节点。

8. 发明申请

US20100146200A1 NON-SNOOP READ/WRITE OPERATIONS IN A SYSTEM SUPPORTING SNOOPING 有权
标题翻译：支持SNOOPING的系统中的非SNOOP读/写操作
公开(公告)号：US20100146200A1
公开(公告)日：2010-06-10
申请号：US12704284
申请日：2010-02-11
申请人： AIMEE D. WOOD , Robert J. Safranek
发明人： AIMEE D. WOOD , Robert J. Safranek
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0815 , G06F12/0828
摘要： Techniques that may utilize generic tracker structures to provide data coherency in a multi-node system that supports non-snoop read and write operations. The trackers may be organized as a two-dimensional queue structure that may be utilized to resolve conflicting read and/or write operations. Multiple queues having differing associated priorities may be utilized.
摘要翻译：可以利用通用跟踪器结构在支持非窥探读和写操作的多节点系统中提供数据一致性的技术。跟踪器可以被组织为可用于解决冲突的读取和/或写入操作的二维队列结构。可以利用具有不同相关优先级的多个队列。

9. 发明申请

US20100115312A1 TECHNIQUES FOR ENTERING A LOW-POWER LINK STATE 有权
标题翻译：输入低功率连接状态的技术
公开(公告)号：US20100115312A1
公开(公告)日：2010-05-06
申请号：US12685874
申请日：2010-01-12
申请人： Shaun M. Conrad , Robert J. Safranek , Selim Bilgin
发明人： Shaun M. Conrad , Robert J. Safranek , Selim Bilgin
IPC分类号： G06F1/32
CPC分类号： H04W52/28 , H04L1/0045 , H04L1/0057 , H04L1/0061 , H04W52/287 , H04W52/48
摘要： Techniques to cause a point-to-point link between system components to engage in a negotiation process that may lead to the link transitioning from an active state in which data may be transmitted between system components to a low power state where data may not be transmitted. The negotiation process may occur between each pair of nodes within an electronic system that are interconnected via point-to-point link. The negotiation may ensure that there are no pending transactions or transactions that may occur within an upcoming period of time. Through this negotiation each component acknowledges and agrees to transition the link to the low power state.
摘要翻译：导致系统组件之间的点对点链路参与可能导致从数据可能在系统组件之间传输到活动状态的链接到可能不被传输数据的低功率状态的协商过程的技术。协商过程可能发生在通过点对点链路互连的电子系统内的每对节点之间。谈判可以确保在即将到来的时间段内没有可能发生的待处理交易或交易。通过此协商，每个组件确认并同意将链路转换为低功率状态。

10. 发明授权

US07571294B2 NoDMA cache 有权
标题翻译： NoDMA缓存
公开(公告)号：US07571294B2
公开(公告)日：2009-08-04
申请号：US11973209
申请日：2007-10-05
申请人： Robert J. Safranek , Debendra Das Sharma
发明人： Robert J. Safranek , Debendra Das Sharma
IPC分类号： G06F12/14
CPC分类号： G06F12/1425 , G06F12/1441 , G06F12/145
摘要： A NoDMA cache including a super page field. The super page field indicates when a set of pages contain protected information. The NoDMA cache is used by a computer system to deny I/O device access to protected information in system memory.
摘要翻译：包含超级页面字段的NoDMA缓存。超级页面字段指示一组页面何时包含受保护的信息。计算机系统使用NoDMA缓存来拒绝I / O设备访问系统内存中受保护的信息。

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