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1. 发明授权

US07191426B1 Method and apparatus for performing incremental compilation on field programmable gate arrays 有权
标题翻译：用于在现场可编程门阵列上执行增量编译的方法和装置
公开(公告)号：US07191426B1
公开(公告)日：2007-03-13
申请号：US10931953
申请日：2004-09-01
申请人： Deshanand Singh , Stephen Brown , Kevin Chan
发明人： Deshanand Singh , Stephen Brown , Kevin Chan
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs) includes generating a first design for the system that includes a first netlist describing a first logical design, and placement and routing of the first logical design. A second design for the system is generated that includes a second netlist describing a second logical design. Changes made to the first design in the second design are identified. Placement is performed on the changes made to the first design on the second design.
摘要翻译：利用现场可编程门阵列（FPGA）在目标设备上设计系统的方法包括为系统生成包括描述第一逻辑设计的第一网表以及第一逻辑设计的布局和路由的系统的第一设计。生成系统的第二设计，其包括描述第二逻辑设计的第二网表。确定了第二个设计中对第一个设计所做的更改。对第二次设计上对第一个设计所做的更改执行放置。

2. 发明授权

US07401314B1 Method and apparatus for performing compound duplication of components on field programmable gate arrays 有权
标题翻译：用于在现场可编程门阵列上执行组件复合复制的方法和装置
公开(公告)号：US07401314B1
公开(公告)日：2008-07-15
申请号：US11148588
申请日：2005-06-09
申请人： Karl Schabas , Stephen Brown , Deshanand Singh , Terry Borer , Shawn Malhotra
发明人： Karl Schabas , Stephen Brown , Deshanand Singh , Terry Borer , Shawn Malhotra
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs) includes duplicating a plurality of components in response to slack values associated with connections to the components in placement locations.
摘要翻译：使用现场可编程门阵列（FPGA）在目标设备上设计系统的方法包括响应于与放置位置中的组件的连接相关联的松弛值复制多个组件。

3. 发明授权

US07257800B1 Method and apparatus for performing logic replication in field programmable gate arrays 有权
标题翻译：用于在现场可编程门阵列中执行逻辑复制的方法和装置
公开(公告)号：US07257800B1
公开(公告)日：2007-08-14
申请号：US10806617
申请日：2004-06-24
申请人： Deshanand Singh , Gabriel Quan , Terry Borer , Valavan Manohararajah , Paul McHardy , Ivan Hamer , Karl Schabas , Kevin Chan
发明人： Deshanand Singh , Gabriel Quan , Terry Borer , Valavan Manohararajah , Paul McHardy , Ivan Hamer , Karl Schabas , Kevin Chan
IPC分类号： G06F17/50 , H03K17/693
CPC分类号： G06F17/5054
摘要： A method for designing a system on a target device utilizing field programmable gate arrays is disclosed. A design is synthesized for the system. Components in the design are mapped onto resources on the target device. Placement locations are determined for the components on the target device. Components to replicate are identified in response to criticality determined from the placement locations.
摘要翻译：公开了一种使用现场可编程门阵列在目标设备上设计系统的方法。为系统合成了一个设计。设计中的组件映射到目标设备上的资源。确定目标设备上的组件的位置位置。根据从放置位置确定的关键性来识别要复制的组件。

4. 发明授权

US07509597B1 Method and apparatus for performing post-placement functional decomposition on field programmable gate arrays using binary decision diagrams 有权
标题翻译：使用二进制决策图在现场可编程门阵列上执行放置后功能分解的方法和装置
公开(公告)号：US07509597B1
公开(公告)日：2009-03-24
申请号：US11172007
申请日：2005-06-30
申请人： Valavan Manohararajah , Deshanand Singh , Stephen Brown
发明人： Valavan Manohararajah , Deshanand Singh , Stephen Brown
IPC分类号： G06G17/50
CPC分类号： G06F17/5054 , G06F17/5072
摘要： A method for designing a system on a field programmable gate array (FPGA) includes using binary decision diagrams (BDDs) to perform functional decomposition on a design for the system after placement.
摘要翻译：用于在现场可编程门阵列（FPGA）上设计系统的方法包括使用二进制决策图（BDD）对放置后的系统的设计执行功能分解。

5. 发明授权

US07797666B1 Systems and methods for mapping arbitrary logic functions into synchronous embedded memories 有权
标题翻译：将任意逻辑功能映射到同步嵌入式存储器中的系统和方法
公开(公告)号：US07797666B1
公开(公告)日：2010-09-14
申请号：US12244635
申请日：2008-10-02
申请人： Gordon Chiu , Deshanand Singh , Valavan Manohararajah , Stephen Brown
发明人： Gordon Chiu , Deshanand Singh , Valavan Manohararajah , Stephen Brown
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： Systems and methods are provided for mapping logic functions from logic elements (“LEs”) into synchronous embedded memory blocks (“EMBs”) of programmable logic devices (“PLDs”). This technique increases the amount of logic that can fit into the PLD. Where area savings are significant, smaller PLDs may be selected to implement a particular circuit. One aspect of the invention relates to methods for identifying sequential cones of logic that may be mapped into synchronous EMBs. After the sequential logic cones are identified for mapping into a synchronous EMB, the logic cone may be selected, expanded, restructured, and retimed, as necessary, to implement the mapping. Another aspect of the invention relates to techniques for handling architectural restrictions of synchronous EMBs, such as the inability to implement the asynchronous behavior of synchronous logic.
摘要翻译：提供了将逻辑元件（“LE”）的逻辑功能映射到可编程逻辑器件（“PLD”）的同步嵌入式存储器块（“EMB”）的系统和方法。这种技术增加了可以适应PLD的逻辑量。如果区域节省很大，则可以选择较小的PLD来实现特定的电路。本发明的一个方面涉及用于识别可以映射到同步EMB中的逻辑顺序锥的方法。在确定用于映射到同步EMB中的顺序逻辑锥之后，可以根据需要选择，扩展，重构和重新定时，以实现映射。本发明的另一方面涉及用于处理同步EMB的架构限制的技术，诸如不能实现同步逻辑的异步行为。

6. 发明授权

US07412677B1 Detecting reducible registers 有权
标题翻译：检测可还原寄存器
公开(公告)号：US07412677B1
公开(公告)日：2008-08-12
申请号：US11360739
申请日：2006-02-22
申请人： Valavan Manohararajah , Gordon R. Chiu , Deshanand Singh , Stephen Brown
发明人： Valavan Manohararajah , Gordon R. Chiu , Deshanand Singh , Stephen Brown
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/504 , G06F2217/84
摘要： Reducible registers are determined to optimize a sequential circuit. A screening method tests one or more sets of registers where the registers of each set are assumed to satisfy a logic condition. The tests determine if the logic condition holds. If the logic condition of a set is found to be violated, the registers may be moved to another set having a different logic condition or removed completely. The registers remaining are potentially reducible. The reducibility of the registers is verified via Boolean analysis by verifying the logic conditions of a register set for each register. If a register does not pass verification, it then may be moved to a different set having a different logic condition or removed completely. The sets that pass verification are reducible.
摘要翻译：确定可减少寄存器以优化顺序电路。一种筛选方法测试一组或多组寄存器，其中假设每个寄存器的寄存器满足逻辑条件。测试确定逻辑条件是否成立。如果发现集合的逻辑条件被违反，则可以将寄存器移动到具有不同逻辑条件的另一集合或完全移除。剩余的寄存器是可以减少的。通过布尔分析来验证寄存器的可复原性，通过验证每个寄存器的寄存器集的逻辑条件。如果寄存器不通过验证，则可以将其移动到具有不同逻辑条件的不同集合或完全移除。通过验证的集合是可以减少的。

7. 发明授权

US07360190B1 Method and apparatus for performing retiming on field programmable gate arrays 有权
标题翻译：用于在现场可编程门阵列上执行重新定时的方法和装置
公开(公告)号：US07360190B1
公开(公告)日：2008-04-15
申请号：US10876709
申请日：2004-06-25
申请人： Deshanand Singh , Gabriel Quan , Terry Borer , Ian Chesal , Valavan Manohararajah , Karl Schabas , Stephen Brown
发明人： Deshanand Singh , Gabriel Quan , Terry Borer , Ian Chesal , Valavan Manohararajah , Karl Schabas , Stephen Brown
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5072 , G06F17/5081
摘要： A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs) includes identifying registers on near-critical paths. The registers are moved to shorten lengths of one or more near-critical paths.
摘要翻译：利用现场可编程门阵列（FPGA）在目标设备上设计系统的方法包括识别近临界路径上的寄存器。移动寄存器以缩短一个或多个近临界路径的长度。

8. 发明授权

US07444613B1 Systems and methods for mapping arbitrary logic functions into synchronous embedded memories 有权
标题翻译：将任意逻辑功能映射到同步嵌入式存储器中的系统和方法
公开(公告)号：US07444613B1
公开(公告)日：2008-10-28
申请号：US11408762
申请日：2006-04-21
申请人： Gordon Chiu , Deshanand Singh , Valavan Manohararajah , Stephen Brown
发明人： Gordon Chiu , Deshanand Singh , Valavan Manohararajah , Stephen Brown
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： Systems and methods are provided for mapping logic functions from logic elements (“LEs”) into synchronous embedded memory blocks (“EMBs”) of programmable logic devices (“PLDs”). This technique increases the amount of logic that can fit into the PLD. Where area savings are significant, smaller PLDs may be selected to implement a particular circuit. One aspect of the invention relates to methods for identifying sequential cones of logic that may be mapped into synchronous EMBs. After the sequential logic cones are identified for mapping into a synchronous EMB, the logic cone may be selected, expanded, restructured, and retimed, as necessary, to implement the mapping. Another aspect of the invention relates to techniques for handling architectural restrictions of synchronous EMBs, such as the inability to implement the asynchronous behavior of synchronous logic.
摘要翻译：提供了将逻辑元件（“LE”）的逻辑功能映射到可编程逻辑器件（“PLD”）的同步嵌入式存储器块（“EMB”）的系统和方法。这种技术增加了可以适应PLD的逻辑量。如果区域节省很大，则可以选择较小的PLD来实现特定的电路。本发明的一个方面涉及用于识别可以映射到同步EMB中的逻辑顺序锥的方法。在确定用于映射到同步EMB中的顺序逻辑锥之后，可以根据需要选择，扩展，重构和重新定时，以实现映射。本发明的另一方面涉及用于处理同步EMB的架构限制的技术，诸如不能实现同步逻辑的异步行为。

9. 发明授权

US07254801B1 Synthesis aware placement: a novel approach that combines knowledge of possible resynthesis 有权
标题翻译：综合知识放置：结合可能的再合成知识的新方法
公开(公告)号：US07254801B1
公开(公告)日：2007-08-07
申请号：US11040323
申请日：2005-01-20
申请人： Terry Borer , Deshanand Singh , Stephen Brown
发明人： Terry Borer , Deshanand Singh , Stephen Brown
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A system and method improves the effectiveness of logic duplication optimizations by dynamically allocating the usage of logic duplicates. Duplicate atoms in the user design are identified. Atoms satisfying heuristics can also be duplicated and added to the user design. During placement, a duplicate-aware cost function is used to determine the location on the programmable device of atoms driven by a duplicate atom. The duplicate-aware cost function evaluates the suitability of a potential location of a driven atom with respect to a source atom and any duplicates of the source atom. Following placement of the atoms of the user design, a rewiring phase establishes a connection between each driven atom and one of the duplicated source atoms. The duplicate-aware cost function can be used to evaluate sets of duplicate source atoms to optimize the operating speed, power consumption, and/or routability of a user design.
摘要翻译：系统和方法通过动态分配逻辑重复的使用来提高逻辑复制优化的有效性。识别用户设计中的重复原子。满足启发式的原子也可以复制并添加到用户设计中。在放置期间，使用重复感知成本函数来确定可编程器件上由重复原子驱动的原子上的位置。重复感知成本函数评估驱动原子相对于源原子的潜在位置和源原子的任何重复的适用性。在放置用户设计的原子之后，重新布线阶段建立每个被驱动的原子和一个复制的源原子之间的连接。重复感知成本函数可用于评估重复源原子的集合，以优化用户设计的操作速度，功耗和/或可路由性。

10. 发明授权

US09134981B2 OpenCL compilation 有权
标题翻译： OpenCL编译
公开(公告)号：US09134981B2
公开(公告)日：2015-09-15
申请号：US13531353
申请日：2012-06-22
申请人： Doris Tzu Lang Chen , Deshanand Singh
发明人： Doris Tzu Lang Chen , Deshanand Singh
IPC分类号： G06F9/44 , G06F9/45 , G06F17/50
CPC分类号： G06F8/48 , G06F17/5054
摘要： Systems and methods for increasing speed and reducing processing power of a compile process of programmable logic of an integrated circuit (IC) are provided. For example, in one embodiment, a method includes obtaining a high level program, comprising computer-readable instructions for implementation on programmable logic of an integrated circuit (IC); translating the high level program into low level code representative of functional components needed to execute functionalities of the high level program; generating a host program comprising computer-readable instructions for implementing the low level code based upon the high level program; obtaining modifications to the high level program; determining whether the modifications can be implemented by a new host program utilizing the low level code; and generating the new host program to implement the modifications, when the modifications can be implemented by the new host program utilizing the low level code.
摘要翻译：提供了用于提高集成电路（IC）的可编程逻辑的编译过程的速度和降低处理能力的系统和方法。例如，在一个实施例中，一种方法包括获得高级程序，包括用于在集成电路（IC）的可编程逻辑上实现的计算机可读指令; 将高级程序转换为代表执行高级程序的功能所需的功能组件的低级代码; 生成包括用于基于所述高级程序实现所述低级代码的计算机可读指令的主机程序; 获得对高级程序的修改; 确定所述修改是否可以通过利用所述低级代码的新的主机程序来实现; 并且当通过新的主机程序利用低级代码实现修改时，生成新的主机程序来实施修改。

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