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1. 发明授权

US07737794B2 Phase locked loop with temperature and process compensation 失效
标题翻译：具有温度和过程补偿的锁相环
公开(公告)号：US07737794B2
公开(公告)日：2010-06-15
申请号：US12120331
申请日：2008-05-14
申请人： David W. Boerstler , Masaaki Kaneko , Toshiyuki Ogata , Jieming Qi
发明人： David W. Boerstler , Masaaki Kaneko , Toshiyuki Ogata , Jieming Qi
IPC分类号： G01R23/02
CPC分类号： H03L1/022 , H03L1/00 , H03L7/099 , H03L2207/06
摘要： Mechanisms are provided for compensating for process and temperature variations in a circuit. The mechanisms may select at least one resistor in a plurality of resistors in the circuit to provide a resistance value for generating a calibration voltage input to the circuit to compensate for variations in process. A reference signal may be compared to a feedback signal generated by the circuit based on the calibration signal. A determination is made as to whether the feedback signal is within a tolerance of the reference signal and, if so, an identifier of the selected at least one resistor is stored in a memory device coupled to the circuit. The circuit may be operated using the selected at least one resistor based on the identifier stored in the memory device. An apparatus and integrated circuit device utilizing these mechanisms are also provided.
摘要翻译：提供用于补偿电路中的工艺和温度变化的机构。这些机构可以选择电路中的多个电阻器中的至少一个电阻器，以提供用于产生输入到电路的校准电压的电阻值，以补偿过程中的变化。参考信号可以与基于校准信号的电路产生的反馈信号进行比较。确定反馈信号是否在参考信号的公差之内，如果是，则将所选择的至少一个电阻器的标识符存储在耦合到该电路的存储器件中。可以基于存储在存储器件中的标识符，使用所选择的至少一个电阻器来操作该电路。还提供了利用这些机构的装置和集成电路装置。

2. 发明申请

US20090285344A1 Phase Locked Loop with Temperature and Process Compensation 失效
标题翻译：具有温度和过程补偿的锁相环
公开(公告)号：US20090285344A1
公开(公告)日：2009-11-19
申请号：US12120331
申请日：2008-05-14
申请人： David W. Boerstler , Masaaki Kaneko , Toshiyuki Ogata , Jieming Qi
发明人： David W. Boerstler , Masaaki Kaneko , Toshiyuki Ogata , Jieming Qi
IPC分类号： H03D3/24
CPC分类号： H03L1/022 , H03L1/00 , H03L7/099 , H03L2207/06
摘要： Mechanisms are provided for compensating for process and temperature variations in a circuit. The mechanisms may select at least one resistor in a plurality of resistors in the circuit to provide a resistance value for generating a calibration voltage input to the circuit to compensate for variations in process. A reference signal may be compared to a feedback signal generated by the circuit based on the calibration signal. A determination is made as to whether the feedback signal is within a tolerance of the reference signal and, if so, an identifier of the selected at least one resistor is stored in a memory device coupled to the circuit. The circuit may be operated using the selected at least one resistor based on the identifier stored in the memory device. An apparatus and integrated circuit device utilizing these mechanisms are also provided.
摘要翻译：提供用于补偿电路中的工艺和温度变化的机构。这些机构可以选择电路中的多个电阻器中的至少一个电阻器，以提供用于产生输入到电路的校准电压的电阻值，以补偿过程中的变化。参考信号可以与基于校准信号的电路产生的反馈信号进行比较。确定反馈信号是否在参考信号的公差之内，如果是，则将所选择的至少一个电阻器的标识符存储在耦合到该电路的存储器件中。可以基于存储在存储器件中的标识符，使用所选择的至少一个电阻器来操作该电路。还提供了利用这些机构的装置和集成电路装置。

3. 发明申请

US20090132971A1 Structure for a Circuit Obtaining Desired Phase Locked Loop Duty Cycle without Pre-Scaler 失效
标题翻译：获得期望的锁相环占空比的电路的结构，不需要预定标器
公开(公告)号：US20090132971A1
公开(公告)日：2009-05-21
申请号：US12130040
申请日：2008-05-30
申请人： David W. Boerstler , Eskinder Hailu , Masaaki Kaneko , Jieming Qi
发明人： David W. Boerstler , Eskinder Hailu , Masaaki Kaneko , Jieming Qi
IPC分类号： H03B19/00 , G06F17/50
CPC分类号： G06F17/5045 , H03K3/017 , H03L7/0995 , H03L2207/06
摘要： A design structure for a circuit for obtaining a desired phase locked loop (PLL) duty cycle without a pre-scaler is provided. The PLL circuit of the illustrative embodiments utilizes two separate loops that simultaneously operate on the VCO. One loop ensures the frequency and phase lock while the other loop ensures the duty cycle lock. The VCO is modified to have an additional control port to adjust the duty cycle. Thus, the VCO has one control port for performing frequency adjustment and one control port for duty cycle adjustment. As a result, both the duty cycle and the frequency may be controlled using the VCO of the PLL circuit of the illustrative embodiments so as to achieve any desired duty cycle output without requiring a VCO pre-scaler circuit or duty cycle correction circuit.
摘要翻译：提供了一种用于在没有预定标器的情况下获得期望的锁相环（PLL）占空比的电路的设计结构。说明性实施例的PLL电路利用在VCO上同时工作的两个单独的环路。一个环路确保频率和相位锁定，而另一个环路确保占空比锁定。 VCO被修改为具有附加的控制端口来调整占空比。因此，VCO具有用于执行频率调整的一个控制端口和用于占空比调整的一个控制端口。结果，可以使用说明性实施例的PLL电路的VCO来控制占空比和频率，以便实现任何期望的占空比输出，而不需要VCO预定标器电路或占空比校正电路。

4. 发明授权

US07511554B2 Systems and methods for level shifting using AC coupling 失效
标题翻译：使用交流耦合进行电平转换的系统和方法
公开(公告)号：US07511554B2
公开(公告)日：2009-03-31
申请号：US11764262
申请日：2007-06-18
申请人： Masaaki Kaneko , David W. Boerstler , Eskinder Hailu , Jieming Qi
发明人： Masaaki Kaneko , David W. Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： H03L5/00
CPC分类号： H03K19/01812 , H03K19/01831
摘要： Systems and methods for conveying signals between integrated circuit (IC) components in domains having different supply voltages. AC coupling is used to increase the speed at which the common mode voltage of a signal is shifted from one level to another. One embodiment comprises a method for level shifting a binary signal in an IC. This method includes receiving an input binary signal and decoupling its AC component from its common mode component. A second common mode component is added to the AC component, providing a binary output signal. The common mode voltage of the input signal may be greater (or smaller) than that of the output signal. In one embodiment of the method, duty cycle compensation (DCC) is performed. The DCC drives the duty cycle toward a desired value.
摘要翻译：在具有不同电源电压的域中的集成电路（IC）组件之间传送信号的系统和方法。 AC耦合用于增加信号的共模电压从一个电平转移到另一个电平的速度。一个实施例包括用于电平移位IC中的二进制信号的方法。该方法包括接收输入二进制信号并将其AC分量与其共模分量去耦。第二共模分量被添加到AC分量，提供二进制输出信号。输入信号的共模电压可以大于（或更小）输出信号的共模电压。在该方法的一个实施例中，执行占空比补偿（DCC）。 DCC将占空比驱动到所需的值。

5. 发明授权

US08032850B2 Structure for an absolute duty cycle measurement circuit 失效
标题翻译：绝对占空比测量电路的结构
公开(公告)号：US08032850B2
公开(公告)日：2011-10-04
申请号：US12129945
申请日：2008-05-30
申请人： David W. Boerstler , Eskinder Hailu , Masaaki Kaneko , Jieming Qi , Bin Wan
发明人： David W. Boerstler , Eskinder Hailu , Masaaki Kaneko , Jieming Qi , Bin Wan
IPC分类号： G06F17/50 , G01R23/00 , G01R29/26
CPC分类号： G06F17/505 , G06F17/5031 , G06F2217/84
摘要： A design structure for a circuit for measuring the absolute duty cycle of a signal, is provided. A non-inverted path from a signal source is selected and various DCC circuit setting indices are cycled through until a divider, coupled to the output of the DCC circuit, fails. A first minimum pulse width at which the divider fails is then determined based on the index value of the DCC circuit at the time of the failure. An inverted path from the signal source is selected and the various DCC circuit setting indices are cycled through again until the divider fails. A second minimum pulse width at which the divider fails is then determined based on the index value of the DCC circuit at the time of this second failure. The duty cycle is then calculated based on a difference of the first and second minimum pulse width values.
摘要翻译：提供了用于测量信号的绝对占空比的电路的设计结构。选择来自信号源的非反相路径，并循环各种DCC电路设置索引，直到耦合到DCC电路的输出的分频器失效。然后，基于故障时的DCC电路的指标值来确定分路器故障时的第一最小脉冲宽度。选择来自信号源的反向路径，并且各种DCC电路设置索引再次循环，直到分频器失效。然后，基于该第二次故障时的DCC电路的指标值来确定分路器故障时的第二最小脉冲宽度。然后基于第一和第二最小脉冲宽度值的差来计算占空比。

6. 发明申请

US20110121874A1 Systems and Methods for PLL Linearity Measurement, PLL Output Duty Cycle Measurement and Duty Cycle Correction 有权
标题翻译： PLL线性度测量，PLL输出占空比测量和占空比校正的系统和方法
公开(公告)号：US20110121874A1
公开(公告)日：2011-05-26
申请号：US12624630
申请日：2009-11-24
申请人： Masaaki Kaneko , David W. Boerstler , Eskinder Hailu , Jieming Qi
发明人： Masaaki Kaneko , David W. Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： H03L7/06
CPC分类号： H03L7/08 , H03L7/099
摘要： Systems and methods for enabling the determination of voltage controlled oscillator (VCO) linearity, duty cycle determination and duty cycle correction in phase locked loop circuits (PLL's.) One embodiment comprises a method including the steps of determining the frequency response of a PLL's VCO as a function of duty cycle, applying a signal based on the VCO output to the VCO input, measuring the resulting frequency of the VCO output signal, determining the duty cycle corresponding to the measured frequency, and configuring a duty cycle correction unit correct the duty cycle of the VCO output signal to about 50%. Determining the frequency response of the VCO may include, for each of several different duty cycle values between 0% and 100%, applying the VCO input signal to the VCO and determining the corresponding frequency of the VCO output signal. This may also be done for duty cycles of 0% and 100%.
摘要翻译：用于确定锁相环电路（PLL）中的压控振荡器（VCO）线性度，占空比确定和占空比校正的系统和方法一个实施例包括一种方法，包括以下步骤：将PLL的VCO的频率响应确定为占空比的功能，将基于VCO输出的信号施加到VCO输入，测量VCO输出信号的最终频率，确定对应于测量频率的占空比，以及配置占空比校正单元校正占空比的VCO输出信号约为50％。确定VCO的频率响应可以包括对于0％和100％之间的几个不同占空比值的每一个，将VCO输入信号施加到VCO并确定VCO输出信号的对应频率。这也可以在0％和100％的占空比下完成。

7. 发明申请

US20090125857A1 Design Structure for an Absolute Duty Cycle Measurement Circuit 失效
标题翻译：绝对占空比测量电路的设计结构
公开(公告)号：US20090125857A1
公开(公告)日：2009-05-14
申请号：US12129945
申请日：2008-05-30
申请人： David W. Boerstler , Eskinder Hailu , Masaaki Kaneko , Jieming Qi , Bin Wan
发明人： David W. Boerstler , Eskinder Hailu , Masaaki Kaneko , Jieming Qi , Bin Wan
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5031 , G06F2217/84
摘要： A design structure for a circuit for measuring the absolute duty cycle of a signal, is provided. A non-inverted path from a signal source is selected and various DCC circuit setting indices are cycled through until a divider, coupled to the output of the DCC circuit, fails. A first minimum pulse width at which the divider fails is then determined based on the index value of the DCC circuit at the time of the failure. An inverted path from the signal source is selected and the various DCC circuit setting indices are cycled through again until the divider fails. A second minimum pulse width at which the divider fails is then determined based on the index value of the DCC circuit at the time of this second failure. The duty cycle is then calculated based on a difference of the first and second minimum pulse width values.
摘要翻译：提供了用于测量信号的绝对占空比的电路的设计结构。选择来自信号源的非反相路径，并循环各种DCC电路设置索引，直到耦合到DCC电路的输出的分频器失效。然后，基于故障时的DCC电路的指标值来确定分路器故障时的第一最小脉冲宽度。选择来自信号源的反向路径，并且各种DCC电路设置索引再次循环，直到分频器失效。然后，基于该第二次故障时的DCC电路的指标值来确定分路器故障时的第二最小脉冲宽度。然后基于第一和第二最小脉冲宽度值的差来计算占空比。

8. 发明授权

US07969250B2 Structure for a programmable interpolative voltage controlled oscillator with adjustable range 失效
标题翻译：具有可调范围的可编程内插压控振荡器的结构
公开(公告)号：US07969250B2
公开(公告)日：2011-06-28
申请号：US12129811
申请日：2008-05-30
申请人： David W. Boerstler , Eskinder Hailu , Masaaki Kaneko , Jieming Qi
发明人： David W. Boerstler , Eskinder Hailu , Masaaki Kaneko , Jieming Qi
IPC分类号： H03B27/00
CPC分类号： H03L7/183 , H03L7/0998
摘要： A design structure for a programmable interpolative voltage controlled oscillator (VCO) with adjustable frequency range output is provided. Programmable delay cells whose size is modifiable based on control inputs to the programmable delay cells are utilized. A different set of control inputs may be provided to programmable delay cells of an inner sub-ring from the set of control inputs provided to programmable delay cells of a main ring of the VCO. The minimum frequency output of the VCO is governed by the main ring programmable delay cell strength with the maximum frequency output of the VCO being governed by a ratio of strengths of the main ring programmable delay cells to the inner sub-ring programmable delay cell. By modifying the control inputs to the inner sub-ring and main ring programmable delay cells, the minimum and maximum frequency outputs, and thus the range between these two frequency outputs, are made programmable.
摘要翻译：提供了具有可调频率范围输出的可编程内插压控振荡器（VCO）的设计结构。利用基于可编程延迟单元的控制输入来修改尺寸的可编程延迟单元。从提供给VCO的主环的可编程延迟单元的控制输入的集合可以向内部子环的可编程延迟单元提供不同的一组控制输入。 VCO的最小频率输出由主环路可编程延迟单元强度控制，VCO的最大频率输出由主环可编程延迟单元与内部子环可编程延迟单元的强度比控制。通过修改内部子环和主环可编程延迟单元的控制输入，可以将最小和最大频率输出，从而将这两个频率输出之间的范围编程为可编程。

9. 发明授权

US07917318B2 Structure for a duty cycle measurement circuit 有权
标题翻译：占空比测量电路的结构
公开(公告)号：US07917318B2
公开(公告)日：2011-03-29
申请号：US12129980
申请日：2008-05-30
申请人： David W. Boerstler , Eskinder Hailu , Masaaki Kaneko , Jieming Qi , Bin Wan
发明人： David W. Boerstler , Eskinder Hailu , Masaaki Kaneko , Jieming Qi , Bin Wan
IPC分类号： G01R13/00
CPC分类号： H03K5/1565 , G01R31/31727
摘要： A design structure for a circuit for measuring the absolute duty cycle of a signal anywhere on an integrated circuit device is provided. The circuit has a plurality of substantially identical pulse shaper elements, each of which expand the pulse of an input signal whose duty cycle is to be measured by a same amount. The outputs of the pulse shaper elements may be coupled to substantially identical divider circuits whose outputs are coupled to a multiplexer that selects two inputs for output to a set of master/slave configured flip-flops, one input serving as a clock and the other as data to the flip-flops. The flip-flops sample the divider outputs selected by the multiplexer to detect if the dividers have failed or not. The outputs of the flip-flops are provided to an XOR gate which outputs a duty cycle signal indicative of the duty cycle of the input signal.
摘要翻译：提供了用于测量集成电路装置上任何地方的信号的绝对占空比的电路的设计结构。该电路具有多个基本上相同的脉冲整形器元件，每个脉冲整形器元件使占空比要被测量相同量的输入信号的脉冲扩展。脉冲整形器元件的输出可以耦合到基本相同的分频器电路，其输出耦合到多路复用器，其选择两个输入以输出到一组主/从配置的触发器，一个输入用作时钟，另一个作为时钟，另一个作为数据到触发器。触发器对由多路复用器选择的分频器输出进行采样，以检测分频器是否发生故障。触发器的输出被提供给异或门，其输出表示输入信号的占空比的占空比信号。

10. 发明授权

US07895005B2 Duty cycle measurement for various signals throughout an integrated circuit device 有权
标题翻译：整个集成电路设备中各种信号的占空比测量
公开(公告)号：US07895005B2
公开(公告)日：2011-02-22
申请号：US11942966
申请日：2007-11-20
申请人： David W. Boerstler , Eskinder Hailu , Masaaki Kaneko , Jieming Qi , Bin Wan
发明人： David W. Boerstler , Eskinder Hailu , Masaaki Kaneko , Jieming Qi , Bin Wan
IPC分类号： G01R13/00
CPC分类号： G01R29/02 , G01R31/31725
摘要： A mechanism is provided for measuring the absolute duty cycle of a signal anywhere on an integrated circuit device. The mechanism employs a circuit having a plurality of substantially identical pulse shaper elements, each of which expand the pulse of an input signal whose duty cycle is to be measured by a same amount. The outputs of the pulse shaper elements may be coupled to substantially identical divider circuits whose outputs are coupled to a multiplexer that selects two inputs for output to a set of master/slave configured flip-flops, one input serving as a clock and the other as data to the flip-flops. The flip-flops sample the divider outputs selected by the multiplexer to detect if the dividers have failed or not. The outputs of the flip-flops are provided to an XOR gate which outputs a duty cycle signal indicative of the duty cycle of the input signal.
摘要翻译：提供了用于测量集成电路设备上任何地方的信号的绝对占空比的机制。该机构采用具有多个基本相同的脉冲整形器元件的电路，每个脉冲整形器元件的占空比将被测量相同量的输入信号的脉冲。脉冲整形器元件的输出可以耦合到基本相同的分频器电路，其输出耦合到多路复用器，其选择两个输入以输出到一组主/从配置的触发器，一个输入用作时钟，另一个作为时钟，另一个作为数据到触发器。触发器对由多路复用器选择的分频器输出进行采样，以检测分频器是否发生故障。触发器的输出被提供给异或门，其输出表示输入信号的占空比的占空比信号。

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