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1. 发明申请

US20080222640A1 Prediction Based Priority Scheduling 有权
标题翻译：基于预测的优先级调度
公开(公告)号：US20080222640A1
公开(公告)日：2008-09-11
申请号：US11683147
申请日：2007-03-07
申请人： David M. Daly , Peter A. Franaszek , Luis A. Lastras-Montano
发明人： David M. Daly , Peter A. Franaszek , Luis A. Lastras-Montano
IPC分类号： G06F9/46
CPC分类号： G06F9/4881
摘要： Systems and methods are provided that schedule task requests within a computing system based upon the history of task requests. The history of task requests can be represented by a historical log that monitors the receipt of high priority task request submissions over time. This historical log in combination with other user defined scheduling rules is used to schedule the task requests. Task requests in the computer system are maintained in a list that can be divided into a hierarchy of queues differentiated by the level of priority associated with the task requests contained within that queue. The user-defined scheduling rules give scheduling priority to the higher priority task requests, and the historical log is used to predict subsequent submissions of high priority task requests so that lower priority task requests that would interfere with the higher priority task requests will be delayed or will not be scheduled for processing.
摘要翻译：提供了系统和方法，其基于任务请求的历史在计算系统内调度任务请求。任务请求的历史可以由历史日志表示，该日志监视随时间的收到高优先级任务请求提交。该历史日志与其他用户定义的调度规则相结合用于调度任务请求。计算机系统中的任务请求被维护在列表中，该列表可以被划分成由包含在该队列内的任务请求所关联的优先级所区分的队列层次。用户定义的调度规则给予较高优先级任务请求的调度优先级，并且使用历史日志来预测高优先级任务请求的后续提交，使得将干扰较高优先级任务请求的较低优先级任务请求将被延迟或不会安排进行处理。

2. 发明授权

US08185899B2 Prediction based priority scheduling 有权
标题翻译：基于预测的优先级调度
公开(公告)号：US08185899B2
公开(公告)日：2012-05-22
申请号：US11683147
申请日：2007-03-07
申请人： David M. Daly , Peter A. Franaszek , Luis A. Lastras-Montano
发明人： David M. Daly , Peter A. Franaszek , Luis A. Lastras-Montano
IPC分类号： G06F9/46
CPC分类号： G06F9/4881
摘要： Systems and methods are provided that schedule task requests within a computing system based upon the history of task requests. The history of task requests can be represented by a historical log that monitors the receipt of high priority task request submissions over time. This historical log in combination with other user defined scheduling rules is used to schedule the task requests. Task requests in the computer system are maintained in a list that can be divided into a hierarchy of queues differentiated by the level of priority associated with the task requests contained within that queue. The user-defined scheduling rules give scheduling priority to the higher priority task requests, and the historical log is used to predict subsequent submissions of high priority task requests so that lower priority task requests that would interfere with the higher priority task requests will be delayed or will not be scheduled for processing.
摘要翻译：提供了系统和方法，其基于任务请求的历史在计算系统内调度任务请求。任务请求的历史可以由历史日志表示，该日志监视随时间的收到高优先级任务请求提交。该历史日志与其他用户定义的调度规则相结合用于调度任务请求。计算机系统中的任务请求被维护在列表中，该列表可以被划分成由包含在该队列内的任务请求所关联的优先级所区分的队列层次。用户定义的调度规则给予较高优先级任务请求的调度优先级，并且使用历史日志来预测高优先级任务请求的后续提交，使得将干扰较高优先级任务请求的较低优先级任务请求将被延迟或不会安排进行处理。

3. 发明授权

US08838901B2 Coordinated writeback of dirty cachelines 有权
标题翻译：脏缓存行的协调回写
公开(公告)号：US08838901B2
公开(公告)日：2014-09-16
申请号：US12775510
申请日：2010-05-07
申请人： David M. Daly , Benjiman L. Goodman , Hillery C. Hunter , William J. Starke , Jeffrey A. Stuecheli
发明人： David M. Daly , Benjiman L. Goodman , Hillery C. Hunter , William J. Starke , Jeffrey A. Stuecheli
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0804 , G06F12/0817 , G06F12/0897 , Y02D10/13
摘要： A data processing system includes a processor core and a cache memory hierarchy coupled to the processor core. The cache memory hierarchy includes at least one upper level cache and a lowest level cache. A memory controller is coupled to the lowest level cache and to a system memory and includes a physical write queue from which the memory controller writes data to the system memory. The memory controller initiates accesses to the lowest level cache to place into the physical write queue selected cachelines having spatial locality with data present in the physical write queue.
摘要翻译：数据处理系统包括处理器核心和耦合到处理器核心的高速缓存存储器层级。高速缓存存储器层级包括至少一个上级高速缓存和最低级高速缓存。存储器控制器耦合到最低级缓存和系统存储器，并且包括物理写队列，存储器控制器从该物理写队列将数据写入系统存储器。存储器控制器启动对最低级高速缓存的访问以放置到物理写入队列中，所选择的高速缓存线具有空间局部性，其中数据存在于物理写入队列中。

4. 发明授权

US08788757B2 Dynamic inclusive policy in a hybrid cache hierarchy using hit rate 失效
标题翻译：使用命中率的混合缓存层次结构中的动态包容性策略
公开(公告)号：US08788757B2
公开(公告)日：2014-07-22
申请号：US13315381
申请日：2011-12-09
申请人： David M. Daly , Benjiman L. Goodman , Stephen J. Powell , Aaron C. Sawdey , Jeffrey A. Stuecheli
发明人： David M. Daly , Benjiman L. Goodman , Stephen J. Powell , Aaron C. Sawdey , Jeffrey A. Stuecheli
IPC分类号： G06F13/28
CPC分类号： G06F12/0888 , G06F12/0897 , G06F12/126
摘要： A mechanism is provided for dynamic cache allocation using a cache hit rate. A first cache hit rate is monitored in a first subset utilizing a first allocation policy of N sets of a lower level cache. A second cache hit rate is also monitored in a second subset utilizing a second allocation policy different from the first allocation policy of the N sets of the lower level cache. A periodic comparison of the first cache hit rate to the second cache hit rate is made to identify a third allocation policy for a third subset of the N-sets of the lower level cache. The third allocation policy for the third subset is then periodically adjusted to at least one of the first allocation policy or the second allocation policy based on the comparison of the first cache hit rate to the second cache hit rate.
摘要翻译：提供了一种用于使用高速缓存命中率进行动态高速缓存分配的机制。使用N组较低级高速缓存的第一分配策略，在第一子集中监视第一高速缓存命中率。利用与下一级高速缓存的N组的第一分配策略不同的第二分配策略，也在第二子集中监视第二高速缓存命中率。进行第一高速缓存命中率与第二高速缓存命中率的周期性比较，以识别下级高速缓存的N组的第三子集的第三分配策略。然后，基于第一高速缓存命中率与第二高速缓存命中率的比较，将第三子集的第三分配策略周期性地调整为第一分配策略或第二分配策略中的至少一个。

5. 发明申请

US20130151780A1 Weighted History Allocation Predictor Algorithm in a Hybrid Cache 有权
公开(公告)号：US20130151780A1
公开(公告)日：2013-06-13
申请号：US13611614
申请日：2012-09-12
申请人： David M. Daly , Benjiman L. Goodman , Stephen J. Powell , Aaron C. Sawdey , Jeffrey A. Stuecheli
发明人： David M. Daly , Benjiman L. Goodman , Stephen J. Powell , Aaron C. Sawdey , Jeffrey A. Stuecheli
IPC分类号： G06F12/08
CPC分类号： G06F12/122 , G06F12/0897 , G06F12/121
摘要： A mechanism is provided for weighted history allocation prediction. For each member in a plurality of members in a lower level cache, an associated reference counter is initialized to an initial value based on an operation type that caused data to be allocated to a member location of the member. For each access to the member in the lower level cache, the associated reference counter is incremented. Responsive to a new allocation of data to the lower level cache and responsive to the new allocation of data requiring the victimization of another member in the lower level cache, a member of the lower level cache is identified that has a lowest reference count value in its associated reference counter. The member with the lowest reference count value in its associated reference counter is then evicted.

6. 发明申请

US20130151777A1 Dynamic Inclusive Policy in a Hybrid Cache Hierarchy Using Hit Rate 失效
标题翻译：使用命中率的混合缓存层次结构中的动态包容性策略
公开(公告)号：US20130151777A1
公开(公告)日：2013-06-13
申请号：US13315381
申请日：2011-12-09
申请人： David M. Daly , Benjiman L. Goodman , Stephen J. Powell , Aaron C. Sawdey , Jeffrey A. Stuecheli
发明人： David M. Daly , Benjiman L. Goodman , Stephen J. Powell , Aaron C. Sawdey , Jeffrey A. Stuecheli
IPC分类号： G06F12/08
CPC分类号： G06F12/0888 , G06F12/0897 , G06F12/126
摘要： A mechanism is provided for dynamic cache allocation using a cache hit rate. A first cache hit rate is monitored in a first subset utilizing a first allocation policy of N sets of a lower level cache. A second cache hit rate is also monitored in a second subset utilizing a second allocation policy different from the first allocation policy of the N sets of the lower level cache. A periodic comparison of the first cache hit rate to the second cache hit rate is made to identify a third allocation policy for a third subset of the N-sets of the lower level cache. The third allocation policy for the third subset is then periodically adjusted to at least one of the first allocation policy or the second allocation policy based on the comparison of the first cache hit rate to the second cache hit rate.
摘要翻译：提供了一种用于使用高速缓存命中率进行动态高速缓存分配的机制。使用N组较低级高速缓存的第一分配策略，在第一子集中监视第一高速缓存命中率。利用与下一级高速缓存的N组的第一分配策略不同的第二分配策略，也在第二子集中监视第二高速缓存命中率。进行第一高速缓存命中率与第二高速缓存命中率的周期性比较，以识别下级高速缓存的N组的第三子集的第三分配策略。然后，基于第一高速缓存命中率与第二高速缓存命中率的比较，将第三子集的第三分配策略周期性地调整为第一分配策略或第二分配策略中的至少一个。

7. 发明授权

US08688915B2 Weighted history allocation predictor algorithm in a hybrid cache 有权
标题翻译：混合高速缓存中加权历史分配预测算法
公开(公告)号：US08688915B2
公开(公告)日：2014-04-01
申请号：US13315411
申请日：2011-12-09
申请人： David M. Daly , Benjiman L. Goodman , Stephen J. Powell , Aaron C. Sawdey , Jeffrey A. Stuecheli
发明人： David M. Daly , Benjiman L. Goodman , Stephen J. Powell , Aaron C. Sawdey , Jeffrey A. Stuecheli
IPC分类号： G06F12/16
CPC分类号： G06F12/122 , G06F12/0897 , G06F12/121
摘要： A mechanism is provided for weighted history allocation prediction. For each member in a plurality of members in a lower level cache, an associated reference counter is initialized to an initial value based on an operation type that caused data to be allocated to a member location of the member. For each access to the member in the lower level cache, the associated reference counter is incremented. Responsive to a new allocation of data to the lower level cache and responsive to the new allocation of data requiring the victimization of another member in the lower level cache, a member of the lower level cache is identified that has a lowest reference count value in its associated reference counter. The member with the lowest reference count value in its associated reference counter is then evicted.
摘要翻译：提供了一种用于加权历史分配预测的机制。对于较低级缓存中的多个成员中的每个成员，相关联的引用计数器基于导致数据被分配给成员的成员位置的操作类型被初始化为初始值。对于对较低级缓存中的成员的每次访问，相关联的引用计数器递增。响应于对低级缓存的新数据分配并响应于需要在较低级别高速缓存中另一成员受害的数据的新分配，识别出在其级别缓存中具有最低参考计数值的成员相关参考计数器。然后将其相关参考计数器中具有最低参考计数值的成员逐出。

8. 发明授权

US4145082A Cradle for controlling abnormal sitting postures 失效
标题翻译：用于控制异常坐姿的摇篮
公开(公告)号：US4145082A
公开(公告)日：1979-03-20
申请号：US786498
申请日：1977-04-11
申请人： David M. Daly , Cynthia L. Stone
发明人： David M. Daly , Cynthia L. Stone
IPC分类号： A61F5/37 , A61G5/10 , A47C3/00 , A47C25/00 , A61F13/00
CPC分类号： A61F5/3792 , A61G5/10 , A61G5/1091 , Y10S297/04
摘要： A support cradle for supporting a person seated in a chair by cradling the upper legs of the person, and maintaining the legs in a desired passive restraint arranged so that if the person moves the hips or legs in an abnormal degree such as excessive hip flexion, hip adduction, hip internal rotation, hip extension, scissoring or the like, the cradle will restrain such movement. The cradle provides no restraint so long as normal sitting posture is maintained. The cradle is especially useful in treatment and management of patients with neurogenic movement disorders which manifest with spasticity and abnormal movement patterns such as with spinal cord injury or in cerebral palsy.
摘要翻译：支撑座，用于支撑坐在椅子上的人坐在人的上肢上，并将腿保持在所希望的被动约束中，以使得如果髋或腿以异常程度如髋关节过度屈曲而移动，髋关节内收，髋内旋，髋关节伸展，剪刀等，摇篮会抑制这种运动。只要保持正常的坐姿，摇篮就不会有任何限制。摇篮在治疗和管理患有神经源性运动障碍的患者中特别有用，其表现为痉挛和异常运动模式，例如脊髓损伤或脑瘫。

9. 发明授权

US08683128B2 Memory bus write prioritization 有权
公开(公告)号：US08683128B2
公开(公告)日：2014-03-25
申请号：US12775511
申请日：2010-05-07
申请人： David M. Daly , Benjiman L. Goodman , Hillery C. Hunter , William J. Starke , Jeffrey A. Stuecheli
发明人： David M. Daly , Benjiman L. Goodman , Hillery C. Hunter , William J. Starke , Jeffrey A. Stuecheli
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0888 , Y02D10/13
摘要： A data processing system includes a multi-level cache hierarchy including a lowest level cache, a processor core coupled to the multi-level cache hierarchy, and a memory controller coupled to the lowest level cache and to a memory bus of a system memory. The memory controller includes a physical read queue that buffers data read from the system memory via the memory bus and a physical write queue that buffers data to be written to the system memory via the memory bus. The memory controller grants priority to write operations over read operations on the memory bus based upon a number of dirty cachelines in the lowest level cache memory.

10. 发明申请

US20140068319A1 Error Detection And Correction In A Memory System 审中-公开
标题翻译：内存系统中的错误检测和纠正
公开(公告)号：US20140068319A1
公开(公告)日：2014-03-06
申请号：US13622521
申请日：2012-09-19
申请人： David M. Daly
发明人： David M. Daly
IPC分类号： G06F11/10 , G06F12/02
CPC分类号： G11C7/1006 , G06F11/1076 , G06F2211/1088 , G11C2029/0411 , G11C2211/4062
摘要： An apparatus including at least one memory controller; and a plurality of random access memories, where the at least one memory controller is configured to allocate the plurality of random access memories among at least a first portion, a second portion and a third portion. The first portion is configured to store protected data. The second portion is configured to store parity information for the stored protected data. The third portion is configured to store unprotected data.
摘要翻译：一种装置，包括至少一个存储器控制器; 以及多个随机存取存储器，其中至少一个存储器控制器被配置为在至少第一部分，第二部分和第三部分之间分配多个随机存取存储器。第一部分被配置为存储受保护的数据。第二部分被配置为存储所存储的受保护数据的奇偶校验信息。第三部分被配置为存储未受保护的数据。

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