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1. 发明授权

US07924862B2 Systems and methods for reducing reflections and frequency dependent dispersions in redundant links 有权
标题翻译：用于减少冗余链路中反射和频率分散的系统和方法
公开(公告)号：US07924862B2
公开(公告)日：2011-04-12
申请号：US12687593
申请日：2010-01-14
申请人： David Chengson , Jaya Bandyopadhyay
发明人： David Chengson , Jaya Bandyopadhyay
IPC分类号： H04L12/28 , H04L12/56 , H04L12/66
CPC分类号： H04L1/22 , H04L25/0272 , H04L25/0314 , H04L25/03878
摘要： A network device includes a group of high speed redundant transmission lines and a switch. The switch is configured to select one of the high speed redundant transmission lines. The switch causes reflections and frequency dependent dispersions in the selected high speed redundant transmission line. The network device further includes a transmitting device that is configured to adjust signals transmitted over the selected high speed redundant transmission line so as to reduce the reflections and frequency dependent dispersions.
摘要翻译：网络设备包括一组高速冗余传输线和一个交换机。该开关被配置为选择一个高速冗余传输线。该开关导致所选择的高速冗余传输线中的反射和频率分散。网络设备还包括发送设备，其被配置为调整通过所选择的高速冗余传输线路发送的信号，以便减少反射和频率依赖的分散。

2. 发明授权

US08675483B2 Systems and methods for reducing reflections and frequency dependent dispersions in redundant links 有权
标题翻译：用于减少冗余链路中反射和频率分散的系统和方法
公开(公告)号：US08675483B2
公开(公告)日：2014-03-18
申请号：US13043348
申请日：2011-03-08
申请人： David Chengson , Jaya Bandyopadhyay
发明人： David Chengson , Jaya Bandyopadhyay
IPC分类号： H04L1/00 , H04L12/26
CPC分类号： H04L1/22 , H04L25/0272 , H04L25/0314 , H04L25/03878
摘要： A network device includes a group of high speed redundant transmission lines and a switch. The switch is configured to select one of the high speed redundant transmission lines. The switch causes reflections and frequency dependent dispersions in the selected high speed redundant transmission line. The network device further includes a transmitting device that is configured to adjust signals transmitted over the selected high speed redundant transmission line so as to reduce the reflections and frequency dependent dispersions.
摘要翻译：网络设备包括一组高速冗余传输线和一个交换机。该开关被配置为选择一个高速冗余传输线。该开关导致所选择的高速冗余传输线中的反射和频率分散。网络设备还包括发送设备，其被配置为调整通过所选择的高速冗余传输线路发送的信号，以便减少反射和频率依赖的分散。

3. 发明授权

US07724761B1 Systems and methods for reducing reflections and frequency dependent dispersions in redundant links 有权
标题翻译：用于减少冗余链路中反射和频率分散的系统和方法
公开(公告)号：US07724761B1
公开(公告)日：2010-05-25
申请号：US10405341
申请日：2003-04-03
申请人： David Chengson , Jaya Bandyopadhyay
发明人： David Chengson , Jaya Bandyopadhyay
IPC分类号： H04L12/28 , H04L12/56 , H04L12/66
CPC分类号： H04L1/22 , H04L25/0272 , H04L25/0314 , H04L25/03878
摘要： A network device includes a group of high speed redundant transmission lines and a switch. The switch is configured to select one of the high speed redundant transmission lines. The switch causes reflections and frequency dependent dispersions in the selected high speed redundant transmission line. The network device further includes a transmitting device that is configured to adjust signals transmitted over the selected high speed redundant transmission line so as to reduce the reflections and frequency dependent dispersions.
摘要翻译：网络设备包括一组高速冗余传输线和一个交换机。该开关被配置为选择一个高速冗余传输线。该开关导致所选择的高速冗余传输线中的反射和频率分散。网络设备还包括发送设备，其被配置为调整通过所选择的高速冗余传输线路发送的信号，以便减少反射和频率依赖的分散。

4. 发明授权

US5793259A Apparatus for generating differential noise between power and ground planes 失效
标题翻译：用于在电源和接地层之间产生差分噪声的装置
公开(公告)号：US5793259A
公开(公告)日：1998-08-11
申请号：US879957
申请日：1997-06-20
申请人： David Chengson
发明人： David Chengson
IPC分类号： H03B29/00 , H05K1/02 , H01H31/02
CPC分类号： H03B29/00 , H05K1/0216 , H05K1/0266
摘要： The present invention provides an apparatus for generating a differential noise between a power and ground planes in a printed wiring board (PWB). The apparatus comprises a power plane, a ground plane, and a signal transmission circuit. A plurality of cuts comprising a first pattern is formed on the power plane. The ground plane also provides a plurality of cuts comprising a second pattern. Both the power plane and the ground plane are disposed in the PWB. A signal transmission circuit transmits a signal current over the ground plane and the power plane. The signal current induces an image return current on both the power plane and the ground plane. The first and second patterns of cuts on the power plane and the ground plane, respectively, disrupt the image return current and cause a differential voltage noise to be generated between the power plane and the ground plane.
摘要翻译：本发明提供了一种用于在印刷电路板（PWB）中的电源和接地层之间产生差分噪声的装置。该装置包括电力平面，接地平面和信号传输电路。在动力平面上形成包括第一图案的多个切口。接地平面还提供包括第二图案的多个切口。功率平面和接地平面均布置在PWB中。信号传输电路在地平面和电源平面上传输信号电流。信号电流在电源平面和接地平面上都会产生一个图像返回电流。分别在电源平面和接地平面上的第一和第二切割模式破坏了图像的返回电流并且在电源平面和接地平面之间产生差分电压噪声。

5. 发明授权

US08000351B2 Source synchronous link with clock recovery and bit skew alignment 有权
标题翻译：源同步链路，具有时钟恢复和位偏移对齐
公开(公告)号：US08000351B2
公开(公告)日：2011-08-16
申请号：US12394958
申请日：2009-02-27
申请人： David Chengson , Joel Frederick Darnauer , Matthew A. Tucker
发明人： David Chengson , Joel Frederick Darnauer , Matthew A. Tucker
IPC分类号： H04J3/06 , H04L7/02
CPC分类号： H04L25/14 , H04L7/0066 , H04L7/033
摘要： A high speed transmission system transfers data streams over a plurality of data links. Each data link may carry a number of bit streams. A clock signal is not transmitted over the optical link. Instead, an indication of the appropriate clock signal frequency and phase is embedded in the transmitted data. At the receiving end, a clock signal of an appropriate frequency and phase is generated. The new clock signal is used to sample and reconstruct the original data streams.
摘要翻译：高速传输系统通过多个数据链路传输数据流。每个数据链路可以携带多个比特流。时钟信号不通过光链路传输。相反，适当的时钟信号频率和相位的指示被嵌入在发送的数据中。在接收端，产生适当频率和相位的时钟信号。新的时钟信号用于对原始数据流进行采样和重建。

6. 发明授权

US07515614B1 Source synchronous link with clock recovery and bit skew alignment 有权
标题翻译：源同步链路，具有时钟恢复和位偏移对齐
公开(公告)号：US07515614B1
公开(公告)日：2009-04-07
申请号：US11400222
申请日：2006-04-10
申请人： David Chengson , Joel Frederick Darnauer , Matthew A. Tucker
发明人： David Chengson , Joel Frederick Darnauer , Matthew A. Tucker
IPC分类号： H04J3/06 , H04L7/02
CPC分类号： H04L25/14 , H04L7/0066 , H04L7/033
摘要： A high speed transmission system transfers data streams over a set of data links. Each data link may carry a number of bit streams. A clock signal is not transmitted over the optical link. Instead, an indication of the appropriate clock signal frequency and please is embedded in the transmitted data. At the receiving end, a clock signal of an appropriate frequency and phase is generated. The new clock signal is used to sample and reconstruct the original data streams.
摘要翻译：高速传输系统通过一组数据链路传输数据流。每个数据链路可以携带多个比特流。时钟信号不通过光链路传输。而是将适当的时钟信号频率的指示嵌入到发送的数据中。在接收端，产生适当频率和相位的时钟信号。新的时钟信号用于对原始数据流进行采样和重建。

7. 发明授权

US07061939B1 Source synchronous link with clock recovery and bit skew alignment 有权
标题翻译：源同步链路，具有时钟恢复和位偏移对齐
公开(公告)号：US07061939B1
公开(公告)日：2006-06-13
申请号：US09879176
申请日：2001-06-13
申请人： David Chengson , Joel Frederick Darnauer , Matthew A. Tucker
发明人： David Chengson , Joel Frederick Darnauer , Matthew A. Tucker
IPC分类号： H04J3/06
CPC分类号： H04L25/14 , H04L7/0066 , H04L7/033
摘要： A high speed transmission system transfers data streams over a plurality of data links. Each data link may carry a number of bit streams. On the transmitting end, multiplexers serialize the bit streams, which are then transmitted to the receiving end. A clock signal is not transmitted over the optical link. Instead, an indication of the appropriate clock signal frequency and phase is embedded in the transmitted data. At the receiving end, a clock recovery circuit generates a clock signal of an appropriate frequency and phase based on the embedded indication. The new clock signal is used to sample and reconstruct the original data streams.
摘要翻译：高速传输系统通过多个数据链路传输数据流。每个数据链路可以携带多个比特流。在发送端，多路复用器将比特流串行化，然后将其发送到接收端。时钟信号不通过光链路传输。相反，适当的时钟信号频率和相位的指示被嵌入在发送的数据中。在接收端，时钟恢复电路基于嵌入的指示产生适当频率和相位的时钟信号。新的时钟信号用于对原始数据流进行采样和重建。

8. 发明授权

US06538518B1 Multi-loop phase lock loop for controlling jitter in a high frequency redundant system 有权
标题翻译：用于控制高频冗余系统抖动的多回路锁相环
公开(公告)号：US06538518B1
公开(公告)日：2003-03-25
申请号：US09745450
申请日：2000-12-26
申请人： David Chengson
发明人： David Chengson
IPC分类号： H03L700
CPC分类号： H03L7/107 , H03L7/095 , H04J3/0688 , Y10S331/02
摘要： A multi-loop phase lock loop (PLL) contains multiple loop filters, each having different bandwidths. The multi-loop PLL receives one of multiple high-frequency clock signals as an input. A phase detector outputs a signal, based on the phase difference between the high-frequency clock signal and a feedback signal to the loop filters. A voltage controlled oscillator generates an output clock signal based on signals received from the loop filters. During a clock switch over sequence between the multiple high-frequency input clock signals, the multi-loop PLL uses one of its loop filters with a wide bandwidth to quickly lock the input clock signal. Once the clock signal is locked, a narrower bandwidth loop filter in the PLL is then used to reduce jitter in the locked signal.
摘要翻译：多回路锁相环（PLL）包含多个环路滤波器，每个环路滤波器具有不同的带宽。多回路PLL接收多个高频时钟信号之一作为输入。相位检测器基于高频时钟信号和反馈信号之间的相位差输出到环路滤波器。压控振荡器基于从环路滤波器接收的信号产生输出时钟信号。在多个高频输入时钟信号之间的时钟切换序列期间，多环路PLL使用其宽带宽的环路滤波器之一来快速锁定输入时钟信号。一旦时钟信号被锁定，则PLL中的较窄带宽环路滤波器然后用于减少锁定信号中的抖动。

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