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1. 发明申请

US20080077891A1 METHOD AND APPARATUS FOR PARALLEL DATA PREPARATION AND PROCESSING OF INTEGRATED CIRCUIT GRAPHICAL DESIGN DATA 失效
标题翻译：用于并行数据准备和处理集成电路图形设计数据的方法和装置
公开(公告)号：US20080077891A1
公开(公告)日：2008-03-27
申请号：US11535789
申请日：2006-09-27
申请人： Daria R. Dooling , Kenneth T. Settlemyer , Jacek G. Smolinski , Stephen D. Thomas , Ralph J. Williams
发明人： Daria R. Dooling , Kenneth T. Settlemyer , Jacek G. Smolinski , Stephen D. Thomas , Ralph J. Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/36
摘要： A method for implementing an ORC process to facilitate physical verification of an integrated circuit (IC) graphical design. The method includes partitioning the IC graphical design data into files by a host machine such that the files correspond to regions of interest or partitions with defined margins, dispersing the partitioned data files to available cpus within the network, processing of each job by the cpu receiving the file, wherein artifacts arising from bisection of partitioning margins during the partitioning, including cut-induced false errors, are detected and removed, and the shape-altering effects of such artifact errors are minimized and transmitting the results of processing at each cpu to the host machine for aggregate processing.
摘要翻译：一种用于实现ORC过程以促进集成电路（IC）图形设计的物理验证的方法。该方法包括：通过主机将IC图形设计数据划分成文件，使得文件对应于具有定义边距的感兴趣区域或分区，将分割的数据文件分散到网络内的可用CPU，通过cpu接收处理每个作业文件，其中检测和去除在划分期间由分割边缘的二分分割产生的伪像，包括切割引起的错误错误，并且将这些伪像误差的形状改变效果最小化，并将每个cpu处理的结果传送到主机用于聚合处理。

2. 发明申请

US20080261128A1 Methods and structures for protecting one area while processing another area on a chip 有权
标题翻译：在处理芯片上的另一个区域时保护一个区域的方法和结构
公开(公告)号：US20080261128A1
公开(公告)日：2008-10-23
申请号：US12106586
申请日：2008-04-21
申请人： Deok-kee Kim , Kenneth T. Settlemyer , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Dirk Pfeiffer , Thimothy Dalton , Katherina Babich , Arpan P. Mahorowala , Harald Okorn-Schmidt
发明人： Deok-kee Kim , Kenneth T. Settlemyer , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Dirk Pfeiffer , Thimothy Dalton , Katherina Babich , Arpan P. Mahorowala , Harald Okorn-Schmidt
IPC分类号： G03F7/004 , G03F7/20
CPC分类号： H01L21/0337 , G03F7/11 , H01L21/027 , H01L21/0332 , H01L21/0334 , H01L21/0338 , H01L21/31144
摘要： Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.
摘要翻译：增加对芯片区域的保护是通过在半导体制造工艺方面具有增强的鲁棒性的掩模结构来提供的，或者可以以相对于下面的材料或两者的增加的选择性和可控性被去除。提供掩模结构，其显示化学反应，颗粒或材料类型的界面，其可被利用以增强任一种或两种类型的保护。这种掩模的结构包括TERA材料，其可以使用氟化氢和吸湿性酸或有机溶剂的混合物以及相似或不同材料的两层结构进行转化或水合并选择性蚀刻。

3. 发明授权

US07718993B2 Pattern enhancement by crystallographic etching 有权
标题翻译：通过晶体蚀刻的图案增强
公开(公告)号：US07718993B2
公开(公告)日：2010-05-18
申请号：US12108574
申请日：2008-04-24
申请人： Thomas W. Dyer , Kenneth T. Settlemyer , James J. Toomey , Haining Yang
发明人： Thomas W. Dyer , Kenneth T. Settlemyer , James J. Toomey , Haining Yang
IPC分类号： H01L31/00
CPC分类号： H01L21/30608 , H01L21/32134
摘要： A method for producing predetermined shapes in a crystalline Si-containing material that have substantially uniform straight sides or edges and well-defined inside and outside corners is provided together with the structure that is formed utilizing the method of the present invention. The inventive method utilizes conventional photolithography and etching to transfer a pattern, i.e., shape, to a crystalline Si-containing material. Since conventional processing is used, the patterns have the inherent limitations of rounded corners. A selective etching process utilizing a solution of diluted ammonium hydroxide is used to eliminate the rounded corners providing a final shape that has substantially straight sides or edges and substantially rounded corners.
摘要翻译：与使用本发明的方法形成的结构一起设置在具有基本均匀的直边或边缘以及良好限定的内角和外角的含Si结晶材料中产生预定形状的方法。本发明的方法利用常规的光刻和蚀刻将图案（即形状）转移到含结晶的含Si材料。由于使用了常规处理，所以图案具有圆角的固有限制。使用利用稀释氢氧化铵溶液的选择性蚀刻方法来消除圆角，提供具有基本上直的边或边缘和基本上圆角的最终形状。

4. 发明申请

US20080242021A1 METHOD OF FABRICATING A BOTTLE TRENCH AND A BOTTLE TRENCH CAPACITOR 失效
标题翻译：制造瓶子和透气电容器的方法
公开(公告)号：US20080242021A1
公开(公告)日：2008-10-02
申请号：US12033984
申请日：2008-02-20
申请人： Oh-Jung Kwon , Kenneth T. Settlemyer , Ravikumar Ramachandran , Min-Soo Kim
发明人： Oh-Jung Kwon , Kenneth T. Settlemyer , Ravikumar Ramachandran , Min-Soo Kim
IPC分类号： H01L21/8242
CPC分类号： H01L27/1087 , H01L29/66181
摘要： A method of fabricating a bottle trench and a bottle trench capacitor. The method including: providing a substrate; forming a trench in the substrate, the trench having sidewalls and a bottom, the trench having an upper region adjacent to a top surface of the substrate and a lower region adjacent to the bottom of the trench; forming an oxidized layer of the substrate in the bottom region of the trench; and removing the oxidized layer of the substrate from the bottom region of the trench, a cross-sectional area of the lower region of the trench greater than a cross-sectional area of the upper region of the trench.
摘要翻译：制造瓶沟槽和瓶沟电容器的方法。该方法包括：提供衬底; 在所述衬底中形成沟槽，所述沟槽具有侧壁和底部，所述沟槽具有与所述衬底的顶表面相邻的上部区域和与所述沟槽的底部相邻的下部区域; 在沟槽的底部区域形成衬底的氧化层; 并且从沟槽的底部区域去除衬底的氧化层，沟槽的下部区域的横截面面积大于沟槽的上部区域的横截面面积。

5. 发明申请

US20080246059A1 Device Fabrication by Anisotropic Wet Etch 失效
标题翻译：各向异性湿蚀刻器件制造
公开(公告)号：US20080246059A1
公开(公告)日：2008-10-09
申请号：US12141878
申请日：2008-06-18
申请人： Yujun Li , Kenneth T. Settlemyer , Jochen Beintner
发明人： Yujun Li , Kenneth T. Settlemyer , Jochen Beintner
IPC分类号： H01L29/772 , H01L21/306
CPC分类号： H01L21/84 , H01L21/30608 , H01L27/1203 , H01L29/045 , H01L29/66772 , H01L29/66818 , H01L29/785
摘要： A method of fabrication and a field effect device structure are presented that reduce source/drain capacitance and allow for device body contact. A Si based material pedestal is produced, the top surface and the sidewalls of which are oriented in a way to be substantially parallel with selected crystallographic planes of the pedestal and of a supporting member. The pedestal is wet etched with an anisotropic solution containing ammonium hydroxide. The sidewalls of the pedestal become faceted forming a segment in the pedestal with a reduced cross section. The dopant concentration in the reduced cross section segment is chosen to be sufficiently high for it to provide for electrical continuity through the pedestal.
摘要翻译：提出了一种制造方法和场效应器件结构，其减少源/漏电容并允许器件接触。制造基于Si的材料基座，其顶表面和其侧壁的取向方向基本上平行于基座和支撑构件的选定结晶平面。用包含氢氧化铵的各向异性溶液湿式蚀刻基座。基座的侧壁变小，在基座上形成截面减小的部分。选择减小的横截面段中的掺杂剂浓度足够高以使其提供穿过基座的电连续性。

6. 发明申请

US20080230868A1 PATTERN ENHANCEMENT BY CRYSTALLOGRAPHIC ETCHING 有权
标题翻译：晶体蚀刻的图案增强
公开(公告)号：US20080230868A1
公开(公告)日：2008-09-25
申请号：US12108574
申请日：2008-04-24
申请人： Thomas W. Dyer , Kenneth T. Settlemyer , James J. Toomey , Haining Yang
发明人： Thomas W. Dyer , Kenneth T. Settlemyer , James J. Toomey , Haining Yang
IPC分类号： H01L29/06
CPC分类号： H01L21/30608 , H01L21/32134
摘要： A method for producing predetermined shapes in a crystalline Si-containing material that have substantially uniform straight sides or edges and well-defined inside and outside corners is provided together with the structure that is formed utilizing the method of the present invention. The inventive method utilizes conventional photolithography and etching to transfer a pattern, i.e., shape, to a crystalline Si-containing material. Since conventional processing is used, the patterns have the inherent limitations of rounded corners. A selective etching process utilizing a solution of diluted ammonium hydroxide is used to eliminate the rounded corners providing a final shape that has substantially straight sides or edges and substantially rounded corners.
摘要翻译：与使用本发明的方法形成的结构一起设置在具有基本上均匀的直边或边缘以及明确限定的内角和外角的含Si结晶材料中产生预定形状的方法。本发明的方法利用常规的光刻和蚀刻将图案（即形状）转移到含结晶的含Si材料。由于使用了常规处理，所以图案具有圆角的固有限制。使用利用稀释氢氧化铵溶液的选择性蚀刻方法来消除圆角，提供具有基本上直的边或边缘和基本上圆角的最终形状。

7. 发明申请

US20080111175A1 METHOD FOR ETCHING SINGLE-CRYSTAL SEMICONDUCTOR SELECTIVE TO AMORPHOUS/POLYCRYSTALLINE SEMICONDUCTOR AND STRUCTURE FORMED BY SAME 有权
标题翻译：用于蚀刻单晶半导体选择性到非晶态/多晶半导体的方法和由其形成的结构
公开(公告)号：US20080111175A1
公开(公告)日：2008-05-15
申请号：US11558974
申请日：2006-11-13
申请人： Kangguo Cheng , Richard O. Henry , Kenneth T. Settlemyer
发明人： Kangguo Cheng , Richard O. Henry , Kenneth T. Settlemyer
IPC分类号： H01L27/108 , H01L21/8242 , H01L21/306
CPC分类号： H01L21/32134 , H01L21/30608 , H01L27/10841 , H01L27/10864
摘要： A method of forming a vertical DRAM device. A lower trench is filled with polycrystalline or amorphous semiconductor for a capacitor. An upper trench portion has exposed sidewalls of single-crystal semiconductor. The method then includes etching the single-crystal semiconductor sidewalls to widen the of the upper trench portion beyond the exposed upper surface of the semiconductor fill of the capacitor to form exposed regions of single-crystal semiconductor on a bottom portion of the upper trench adjacent to the exposed upper surface of the semiconductor fill. A trench top insulating layer is deposited on the bottom portion of the upper trench, over the upper surface of the semiconductor fill and over the adjacent regions of single-crystal semiconductor. The method then includes forming a vertical gate dielectric layer, wherein the trench top insulating layer extends below the vertical gate insulating layer.
摘要翻译：一种形成垂直DRAM装置的方法。下沟槽填充有用于电容器的多晶或非晶半导体。上沟槽部分具有暴露的单晶半导体的侧壁。该方法然后包括蚀刻单晶半导体侧壁以将上部沟槽部分加宽超过电容器的半导体填充物的暴露的上表面，以在邻近上部沟槽的上部沟槽的底部上形成单晶半导体的暴露区域半导体填充物的暴露的上表面。沟槽顶部绝缘层沉积在上沟槽的底部上方，半导体填充物的上表面和相邻的单晶半导体区域上方。该方法然后包括形成垂直栅极电介质层，其中沟槽顶部绝缘层延伸到垂直栅极绝缘层下方。

8. 发明授权

US07157328B2 Selective etching to increase trench surface area 有权
标题翻译：选择性蚀刻以增加沟槽表面积
公开(公告)号：US07157328B2
公开(公告)日：2007-01-02
申请号：US11047312
申请日：2005-01-31
申请人： Helmut Horst Tews , Stephan Kudelka , Kenneth T. Settlemyer
发明人： Helmut Horst Tews , Stephan Kudelka , Kenneth T. Settlemyer
IPC分类号： H01L21/8242
CPC分类号： H01L21/30604 , H01L29/66181
摘要： The surface area of the walls of a trench formed in a substrate is increased. A barrier layer is formed on the walls of the trench such that the barrier layer is thinner near the corners of the trench and is thicker between the corners of the trench. A dopant is introduced into the substrate through the barrier layer to form higher doped regions in the substrate near the corners of the trench and lesser doped regions between the corners of the trench. The barrier layer is removed, and the walls of the trench are etched in a manner that etches the lesser doped regions of the substrate at a higher rate than the higher doped regions of the substrate to widen and lengthen the trench and to form rounded corners at the intersections of the walls of the trench.
摘要翻译：在衬底中形成的沟槽的壁的表面积增加。阻挡层形成在沟槽的壁上，使得阻挡层在沟槽的角部附近更薄，并且在沟槽的角部之间更厚。通过势垒层将掺杂剂引入到衬底中，以在衬底附近的沟槽的角部附近形成更高的掺杂区域，并且在沟槽的角部之间形成较小的掺杂区域。去除阻挡层，并且以如下方式蚀刻沟槽的壁，该方式是以比衬底的较高掺杂区域更高的速率蚀刻衬底的较小掺杂区域，以加宽和延长沟槽并且形成圆角沟渠墙壁的交叉点。

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