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1. 发明授权

US5930719A Data and voice cordless telephone system 失效
标题翻译：数据和语音无绳电话系统
公开(公告)号：US5930719A
公开(公告)日：1999-07-27
申请号：US715938
申请日：1996-09-19
申请人： Daniel Babitch , Andrew G. Varadi , James Wong
发明人： Daniel Babitch , Andrew G. Varadi , James Wong
IPC分类号： H04M1/65 , H04M1/725 , H04B1/38 , H04M11/00
CPC分类号： H04M1/72513 , H04M1/6505 , H04M1/725 , H04M1/72527
摘要： A cordless system comprises a laptop computer with a modem connected to a modem data port on a cordless telephone handset. A direct sequence spread spectrum RF link is established between the cordless telephone handset and a base station. Both the telephone network and a desktop computer with a modem are connected to the base station. When the cordless telephone handset detects that the laptop computer wants to go off-hook, a selection signal is also sent by the cordless telephone handset to the base station to indicate whether the call is to be directed to the telephone network or the desktop computer. When the base station detects that the desktop computer wants to go off-hook, a selection signal is also sent by the desktop computer to the base station to indicate whether the call is to be directed to the telephone network or over the RF link to the laptop computer. Incoming calls from the telephone network are directed to the desktop computer by the base station with a ring indication going to the cordless telephone handset. If the laptop computer answers the ringing, the cordless telephone handset indicates an off-hook condition to the base station and the base station routes the incoming call over the RF link to the cordless telephone handset and the laptop computer.
摘要翻译：无线系统包括具有连接到无绳电话手机上的调制解调器数据端口的调制解调器的膝上型计算机。在无绳电话手机和基站之间建立直接序列扩频RF链路。电话网络和具有调制解调器的台式计算机都连接到基站。当无绳电话听筒检测到膝上型计算机想要摘机时，无线电话手机也将选择信号发送到基站，以指示呼叫是否被引导到电话网络或台式计算机。当基站检测到台式计算机想要摘机时，桌面计算机还向基站发送选择信号，以指示该呼叫是要被引导到电话网络还是通过RF链路到达笔记本电脑。来自电话网络的来电由基站指向桌面计算机，其中指示进入无绳电话手机。如果膝上型计算机应答振铃，则无绳电话手机向基站指示摘机状态，并且基站通过RF链路将呼入路由到无绳电话听筒和笔记本电脑。

2. 发明授权

US4290186A Method of making integrated semiconductor structure having an MOS and a capacitor device 失效
公开(公告)号：US4290186A
公开(公告)日：1981-09-22
申请号：US059637
申请日：1979-07-23
申请人： Thomas Klein , Andrew G. Varadi , Charles E. Boettcher
发明人： Thomas Klein , Andrew G. Varadi , Charles E. Boettcher
IPC分类号： H01L21/8242 , H01L27/108 , H01L29/94 , B01J17/00 , H01L21/265
CPC分类号： H01L27/1085 , H01L27/10805 , H01L29/94
摘要： This disclosure is directed to an improved semiconductor capacitor structure especially useful in an integrated semiconductor structure with an MOS device and fabrication methods therefor. This semiconductor capacitor is particularly useful for forming the capacitor portion of a single MOS memory cell structure in a dynamic MOS random access memory which utilizes one MOS device in combination with a capacitor. In one specific disclosure embodiment, the semiconductor capacitor comprises a boron (P) implanted region in a substrate of P- type conductivity followed by a shallow arsenic (N) implant into the boron implanted region. The boron implanted region provides a P type conductivity which has a higher concentration of P type impurities than the concentration of impurities contained in the substrate which is of P- type conductivity. Thus, the boron implanted region performs the important function of preventing a surface N type inversion layer from being formed across the semiconductor surface beneath the silicon dioxide insulating layer which could occur across the substrate P- surface if the arsenic implant region was made into the P- substrate without the P type boron implant. The arsenic implant is of N type conductivity and has a higher concentration of impurities than the boron implant region. The dielectric portion of the semiconductor capacitor is the portion of the silicon dioxide layer located on the surface of the arsenic implanted region. A doped polysilicon electrode is formed over this portion of the silicon dioxide insulating layer and provides the other plate of the capacitor structure. In another embodiment that is disclosed, this above described semiconductor capacitor structure or device is combined with an MOS device in a single integrated semiconductor structure in order to provide a single MOS memory cell for dynamic random access memory chip utilizing the MOS device and the capacitor. Preferably, the semiconductor capacitor is shown as a connected extension of either the source or drain region of the MOS device.

3. 发明授权

US4120047A Quasi-static MOS memory array with standby operation 失效
标题翻译：具有待机操作的准静态MOS存储器阵列
公开(公告)号：US4120047A
公开(公告)日：1978-10-10
申请号：US789175
申请日：1977-04-20
申请人： Andrew G. Varadi
发明人： Andrew G. Varadi
IPC分类号： G11C11/412 , G11C7/00
CPC分类号： G11C11/412
摘要： This disclosure relates to an MOS or FET memory array that uses a single voltage source (i.e., 5 volts) and operates basically as a static memory array rather than as a dynamic memory array that requires the gates of the MOS devices of the memory array to be periodically refreshed to restore or refresh the memory states contained therein. Each of the memory cells of the memory array contains four MOS devices that are cross-coupled into a flip-flop type of memory cell. All of the memory cells connected to a common word line are also connected to a common return line to which is connected a single resistor and a single large MOS or FET device. The large MOS device is turned on during the active operation of the memory array (during write and read operations) and is turned off during the standby operation of the memory array. The resistor functions to insure that some current flow takes place, during the standby operation, from all the memory cells connected to the common return line in order to maintain the data states ("1" or "0") in each of the memory cells.
摘要翻译：本公开涉及使用单个电压源（即，5伏）并且基本上作为静态存储器阵列操作的MOS或FET存储器阵列，而不是需要存储器阵列的MOS器件的栅极的动态存储器阵列定期刷新以恢复或刷新其中包含的记忆状态。存储器阵列的每个存储单元包含交叉耦合到触发器型存储器单元的四个MOS器件。连接到公共字线的所有存储单元也连接到连接单个电阻器和单个大型MOS或FET器件的公共返回线。在存储器阵列的有效操作期间（在写入和读取操作期间），大的MOS器件导通，并且在存储器阵列的待机操作期间被关闭。电阻器用于确保在备用操作期间从连接到公共返回线路的所有存储器单元发生一些电流，以便保持每个存储器单元中的数据状态（“1”或“0”）。

4. 发明授权

US4115871A MOS random memory array 失效
标题翻译： MOS随机存储器阵列
公开(公告)号：US4115871A
公开(公告)日：1978-09-19
申请号：US788871
申请日：1977-04-19
申请人： Andrew G. Varadi
发明人： Andrew G. Varadi
IPC分类号： G11C11/404 , G11C11/4074 , H01L23/522 , H01L27/108 , G11C11/24 , G11C7/02
CPC分类号： H01L23/522 , G11C11/404 , G11C11/4074 , H01L27/10805 , H01L2924/0002
摘要： This disclosure relates to an MOS random access memory array which utilizes a very small memory cell having a single MOS device and a small size, high capacitance, semiconductor capacitor device connected together to form one bit or memory cell of an MOS dynamic, random access memory array. Preferably, either the source or drain region of the MOS device is connected to the semiconductor portion of the semiconductor capacitor device which is of the electrode-insulator-semiconductor type. The semiconductor capacitor has a very high capacitance due to the use of a very shallow arsenic (N type) implanted region within a boron (P type) implanted region so that the PN junction formed is located where the concentration of Boron impurities is high thereby increasing the capacitance of the semiconductor capacitor. For each memory cell of the memory array, one of the active regions of the MOS device, for example, the source region, is connected to a Bit/Sense line of the memory array. The semiconductor portion of the semiconductor capacitor is connected to the drain region of the MOS device and the electrode plate of the semiconductor capacitor device that is not connected to the drain region of the MOS device is connected to a word line which word line is the next adjacent word line of the MOS random access memory array. The gate of the MOS device is connected up to the word line for that MOS device.
摘要翻译：本公开涉及一种使用具有单个MOS器件的非常小的存储单元和连接在一起的小尺寸，高电容的半导体电容器器件的MOS随机存取存储器阵列，以形成MOS动态随机存取存储器的一位或存储单元数组。优选地，MOS器件的源极或漏极区域连接到具有电极 - 绝缘体 - 半导体型的半导体电容器器件的半导体部分。由于在硼（P型）注入区域内使用非常浅的砷（N型）注入区域，因此半导体电容器具有非常高的电容，使得形成的PN结位于硼杂质浓度高的地方，从而增加半导体电容器的电容。对于存储器阵列的每个存储器单元，MOS器件的有源区域之一，例如源极区域连接到存储器阵列的位/检测线。半导体电容器的半导体部分连接到MOS器件的漏极区域，并且未连接到MOS器件的漏极区域的半导体电容器器件的电极板连接到字线，该字线是下一个字线 MOS随机存取存储器阵列的相邻字线。 MOS器件的栅极连接到该MOS器件的字线。

5. 发明授权

US4413401A Method for making a semiconductor capacitor 失效
公开(公告)号：US4413401A
公开(公告)日：1983-11-08
申请号：US280984
申请日：1981-07-06
申请人： Thomas Klein , Andrew G. Varadi , Charles E. Boettcher
发明人： Thomas Klein , Andrew G. Varadi , Charles E. Boettcher
IPC分类号： H01L21/8234 , H01L27/108 , H01L29/94 , B01J17/00 , H01L21/265
CPC分类号： H01L21/8234 , H01L27/10805 , H01L29/94
摘要： This disclosure is directed to an improved semiconductor capacitor structure especially useful in an integrated semiconductor structure with an MOS device and fabrication methods therefor. This semiconductor capacitor is particularly useful for forming the capacitor portion of a single MOS memory cell structure in a dynamic MOS random access memory which utilizes one MOS device in combination with a capacitor. In one specific disclosure embodiment, the semiconductor capacitor comprises a boron (P) implanted region in a substrate of P- type conductivity followed by a shallow arsenic (N) implant into the boron implanted region. The boron implanted region provides a P type conductivity which has a higher concentration of P type impurities than the concentration of impurities contained in the substrate which is of P- type conductivity. Thus, the boron implanted region performs the important function of preventing a surface N type inversion layer from being formed across the semiconductor surface beneath the silicon dioxide insulating layer which could occur across the substrate P- surface if the arsenic implant region was made into the P- substrate without the P type boron implant. The arsenic implant is of N type conductivity and has a higher concentration of impurities than the boron implant region. The dielectric portion of the semiconductor capacitor is the portion of the silicon dioxide layer located on the surface of the arsenic implanted region. A doped polysilicon electrode is formed over this portion of the silicon dioxide insulating layer and provides the other plate of the capacitor structure. In another embodiment that is disclosed, this above described semiconductor capacitor structure or device is combined with an MOS device in a single integrated semiconductor structure in order to provide a single MOS memory cell for dynamic random access memory chip utilizing the MOS device and the capacitor. Preferably, the semiconductor capacitor is shown as a connected extension of either the source or drain region of the MOS device.

6. 发明授权

US4069474A MOS Dynamic random access memory having an improved sensing circuit 失效
标题翻译： MOS具有改进的感测电路的动态随机存取存储器
公开(公告)号：US4069474A
公开(公告)日：1978-01-17
申请号：US677462
申请日：1976-04-15
申请人： Charles E. Boettcher , Joel A. Karp , John A. Reed , Andrew G. Varadi
发明人： Charles E. Boettcher , Joel A. Karp , John A. Reed , Andrew G. Varadi
IPC分类号： G11C11/404 , G11C11/4091 , H03K3/356 , G11C7/06 , G11C11/24 , G11C11/40
CPC分类号： G11C11/4091 , G11C11/404 , H03K3/356017 , H03K3/35606 , H03K3/356095
摘要： In a memory circuit, first and second bit line portions, each having a plurality of memory cells coupled thereto are provided for reading and writing electrical potentials into and out of the coupled memory cells. A bistable flip-flop type sensing amplifier is coupled between the first and second bit portion for sensing the voltage difference therebetween and for latching into one of the two states in response to sensing either a "0" or a "1" accessed to one of the bit line portions from an addressed memory cell to be read out of the memory. A high input impedance amplifier is provided between the respective bit line portion and the respective input terminal of the sensing amplifier for isolating (buffering) the stray capacitance of the sensing amplifier circuit from the capacitance of its bit line. Switchable restore circuitry bypasses each of the isolating line amplifiers for the purposes of restoring electrical potentials read out of the addressed memory cells. In a preferred embodiment, the buffer line amplifiers comprise source follower amplifiers.
摘要翻译：在存储器电路中，提供每个具有与其耦合的多个存储单元的第一和第二位线部分，用于将电位读入和写入耦合的存储单元。双稳态触发器型感测放大器耦合在第一和第二位部分之间，用于感测其间的电压差，并且响应于感测到访问到“0”或“1”之一的“0”或“1”来锁存到两个状态之一来自寻址的存储器单元的位线部分将从存储器读出。在相应的位线部分和感测放大器的相应输入端之间提供高输入阻抗放大器，用于将感测放大器电路的寄生电容与其位线的电容隔离（缓冲）。可切换的恢复电路绕过每个隔离线路放大器，以恢复从寻址的存储单元读出的电位。在优选实施例中，缓冲线路放大器包括源极跟随放大器。

7. 发明授权

US4379259A Process of performing burn-in and parallel functional testing of integrated circuit memories in an environmental chamber 失效
标题翻译：在环境室中执行集成电路存储器的老化和并行功能测试的过程
公开(公告)号：US4379259A
公开(公告)日：1983-04-05
申请号：US129721
申请日：1980-03-12
申请人： Andrew G. Varadi , Walid H. Maghribi
发明人： Andrew G. Varadi , Walid H. Maghribi
IPC分类号： G01R31/28 , G01R15/12
CPC分类号： G01R31/2868
摘要： A process performed by the manufacturer for testing integrated circuits (ICs) to insure better quality and higher reliability thereof and to eliminate the need for incoming inspection and board level testing by the chip customer. In the embodiment disclosed, in-process testing, wafer-probe testing, die separation, packaging, and one by one assembly line testing of the digital memory ICs for catastrophic failures all proceed according to conventional techniques. A large number of the ICs are then plugged into high-temperature, high signal integrity PC storage cards, each adapted for interconnecting the ICs in row-column arrays to form a memory board. The storage cards are mounted within an environmental chamber and are operatively coupled to corresponding PC driver cards mounted externally of the chamber. Next, accelerated dynamic burn-in of the ICs takes place. The PC storage cards are constructed to electrically isolate groups of the ICs so that if an IC in one group has a shorted input, the ICs in the remaining groups will still receive the appropriate dynamic signals to ensure burn-in thereof. Thereafter long functional/pattern testing of the ICs with continuous error logging occurs while the ICs are still mounted in the chamber. Finally the PC storage cards are removed from the chamber and those ICs which have logged either hard or soft errors are separated. The remaining good ICs are subjected to one by one short functional testing to determine compliance with data sheet specs. After quality control testing, the good ICs are shipped to the chip customer who can safely assemble them into user systems without performing the usual customer level incoming inspection and board level testing.
摘要翻译：制造商执行的用于测试集成电路（IC）的过程，以确保更好的质量和更高的可靠性，并消除芯片客户对进入检查和板级测试的需求。在所公开的实施例中，用于灾难性故障的数字存储器IC的进程中测试，晶片探针测试，管芯分离，封装以及逐一组装线测试都是根据常规技术进行的。然后，大量的IC被插入到高温，高信号完整性的PC存储卡中，每个存储卡适于互连行列阵列中的IC以形成存储器板。存储卡安装在环境室中，并且可操作地耦合到安装在室外部的相应的PC驱动器卡。接下来，IC的加速动态老化发生。 PC存储卡被构造为电隔离IC的组，使得如果一组中的IC具有短路输入，则其余组中的IC仍将接收适当的动态信号以确保其被烧录。此后，当IC仍然安装在腔室中时，发生具有连续错误记录的IC的长功能/图案测试。最后，从存储室中取出PC存储卡，并且分离了硬或软错误记录的那些IC。剩下的很好的IC经受一个接一个的短功能测试，以确定符合数据表规格。在质量控制测试之后，良好的IC被运送到芯片客户，他们可以安全地将它们组装到用户系统中，而无需执行通常的客户级别的进入检查和电路板级测试。

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