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1. 发明授权

US08195440B2 Method and apparatus for simulating quasi-periodic circuit operating conditions using a mixed frequency/time algorithm 有权
标题翻译：使用混合频率/时间算法模拟准周期性电路工作条件的方法和装置
公开(公告)号：US08195440B2
公开(公告)日：2012-06-05
申请号：US12372608
申请日：2009-02-17
申请人： Dan Feng , Joel R. Phillips , Kenneth Kundert
发明人： Dan Feng , Joel R. Phillips , Kenneth Kundert
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Described is a process for performing an improved mixed frequency-time algorithm to simulate responses of a circuit that receives a periodic sample signal and at least one information signal. The process selects a set of evenly spaced distinct time points and a set of reference time points. Each of the reference points is associated with a distinct time point, and a reference time point is a signal period away from its respective distinct time point. The process finds a first set of relationships between the values at the distinct time points and the values the reference time points. The process also finds a second set of relationships between the values at the distinct time points and the values at the reference time points. The process then combines the first and second sets of relationships to establish a system of nonlinear equations in terms of the values at the distinct time points only. By solving the system of nonlinear equations, the process finds simulated responses of the circuit in time domain. The process then converts the simulated circuit responses from time domain to frequency domain.
摘要翻译：描述了一种用于执行改进的混合频率 - 时间算法来模拟接收周期性采样信号的电路和至少一个信息信号的响应的过程。该过程选择一组均匀间隔不同的时间点和一组参考时间点。每个参考点与不同的时间点相关联，并且参考时间点是远离其各自的不同时间点的信号周期。该过程在不同时间点的值和参考时间点之间找到第一组关系。该过程还在不同时间点的值和参考时间点的值之间找到第二组关系。然后，该过程组合第一组和第二组关系，以仅在不同时间点处建立非线性方程组的系数。通过求解非线性方程组，该过程在时域中发现电路的仿真响应。然后，该过程将模拟电路响应从时域转换到频域。

2. 发明申请

US20090210202A1 METHOD AND APPARATUS FOR SIMULATING QUASI-PERIODIC CIRCUIT OPERATING CONDITIONS USING A MIXED FREQUENCY/TIME ALGORITHM 有权
标题翻译：使用混合频率/时间算法模拟准周期性电路运行条件的方法和装置
公开(公告)号：US20090210202A1
公开(公告)日：2009-08-20
申请号：US12372608
申请日：2009-02-17
申请人： Dan Feng , Joel R. Phillips , Kenneth Kundert
发明人： Dan Feng , Joel R. Phillips , Kenneth Kundert
IPC分类号： G06F17/10
CPC分类号： G06F17/5036
摘要： Described is a process for performing an improved mixed frequency-time algorithm to simulate responses of a circuit that receives a periodic sample signal and at least one information signal. The process selects a set of evenly spaced distinct time points and a set of reference time points. Each of the reference points is associated with a distinct time point, and a reference time point is a signal period away from its respective distinct time point. The process finds a first set of relationships between the values at the distinct time points and the values the reference time points. The process also finds a second set of relationships between the values at the distinct time points and the values at the reference time points. The process then combines the first and second sets of relationships to establish a system of nonlinear equations in terms of the values at the distinct time points only. By solving the system of nonlinear equations, the process finds simulated responses of the circuit in time domain. The process then converts the simulated circuit responses from time domain to frequency domain.
摘要翻译：描述了一种用于执行改进的混合频率 - 时间算法来模拟接收周期性采样信号的电路和至少一个信息信号的响应的过程。该过程选择一组均匀间隔不同的时间点和一组参考时间点。每个参考点与不同的时间点相关联，并且参考时间点是远离其各自的不同时间点的信号周期。该过程在不同时间点的值和参考时间点之间找到第一组关系。该过程还在不同时间点的值和参考时间点的值之间找到第二组关系。然后，该过程组合第一组和第二组关系，以仅在不同时间点处建立非线性方程组的系数。通过求解非线性方程组，该过程在时域中发现电路的仿真响应。然后，该过程将模拟电路响应从时域转换到频域。

3. 发明授权

US07493240B1 Method and apparatus for simulating quasi-periodic circuit operating conditions using a mixed frequency/time algorithm 有权
标题翻译：使用混合频率/时间算法模拟准周期性电路工作条件的方法和装置
公开(公告)号：US07493240B1
公开(公告)日：2009-02-17
申请号：US09570709
申请日：2000-05-15
申请人： Dan Feng , Joel R. Phillips , Kenneth Kundert
发明人： Dan Feng , Joel R. Phillips , Kenneth Kundert
IPC分类号： G06F17/10
CPC分类号： G06F17/5036
摘要： Described is a process for performing an improved mixed frequency-time algorithm to simulate responses of a circuit that receives a periodic sample signal and at least one information signal. The process selects a set of evenly spaced distinct time points and a set of reference time points. Each of the reference points is associated with a distinct time point, and a reference time point is a signal period away from its respective distinct time point. The process finds a first set of relationships between the values at the distinct time points and the values at the reference time points. The process also finds a second set of relationships between the values at the distinct time points and the values at the reference time points. The process then combines the first and second sets of relationships to establish a system of nonlinear equations in terms of the values at the distinct time points only. By solving the system of nonlinear equations, the process finds simulated responses of the circuit in time domain. The process then converts the simulated circuit responses from time domain to frequency domain.
摘要翻译：描述了一种用于执行改进的混合频率 - 时间算法来模拟接收周期性采样信号的电路和至少一个信息信号的响应的过程。该过程选择一组均匀间隔不同的时间点和一组参考时间点。每个参考点与不同的时间点相关联，并且参考时间点是远离其各自的不同时间点的信号周期。该过程在不同时间点的值和参考时间点的值之间找到第一组关系。该过程还在不同时间点的值和参考时间点的值之间找到第二组关系。然后，该过程组合第一组和第二组关系，以仅在不同时间点处建立非线性方程组的系数。通过求解非线性方程组，该过程在时域中发现电路的仿真响应。然后，该过程将模拟电路响应从时域转换到频域。

4. 发明授权

US08245165B1 Methods and apparatus for waveform based variational static timing analysis 有权
标题翻译：基于波形变分静态时序分析的方法和装置
公开(公告)号：US08245165B1
公开(公告)日：2012-08-14
申请号：US12331072
申请日：2008-12-09
申请人： Saurabh K. Tiwary , Joel R. Phillips , Igor Keller
发明人： Saurabh K. Tiwary , Joel R. Phillips , Igor Keller
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A system and method are disclosed for waveform based variational static timing analysis. A circuit is divided into its linear circuit parts and non-linear circuit parts and modeled together, by a combination of linear modeling techniques, into linear equations that may be represented by matrices. The linear equations in matrix form may be readily solved by a computer such that an input waveform to an input pin of the circuit can be sequentially “pushed” through the various interconnects and logic networks of the circuit to an output pin. Output voltage waveforms are obtained at each stage of the waveform pushing and may be used to perform static timing analysis.
摘要翻译：公开了一种基于波形变分静态时序分析的系统和方法。电路分为线性电路部分和非线性电路部分，并通过线性建模技术的组合建模在一起，形成可以由矩阵表示的线性方程组。矩阵形式的线性方程可以由计算机容易地解决，使得到电路的输入引脚的输入波形可以顺序地“推动”到电路的各种互连和逻辑网络到输出引脚。在波形推送的每个阶段获得输出电压波形，可用于执行静态时序分析。

5. 发明授权

US07533359B2 Method and system for chip design using physically appropriate component models and extraction 有权
标题翻译：使用物理上适当的组件模型和提取的芯片设计方法和系统
公开(公告)号：US07533359B2
公开(公告)日：2009-05-12
申请号：US11437583
申请日：2006-05-19
申请人： Louis K. Scheffer , Joel R. Phillips
发明人： Louis K. Scheffer , Joel R. Phillips
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F17/5081
摘要： An improved method, system, and computer program product is disclosed for predicting the geometric model of transistors once manufacturing and lithographic process effects are taken into consideration. This provides a much more accurate approach for modeling transistors since it is the actual expected geometric shapes that are analyzed, rather than an idealized model of the layout that does not accurately correspond to the actual manufactured IC product. The expected geometric shape includes systematic variations, which can be determined based on the layout, and the expected random variations, which can be determined based on the lithographic process.
摘要翻译：公开了一种改进的方法，系统和计算机程序产品，用于预测制造中的晶体管的几何模型，并考虑光刻处理效果。这为模拟晶体管提供了更加准确的方法，因为它是被分析的实际预期几何形状，而不是不能准确对应于实际制造的IC产品的理想化模型。期望的几何形状包括可以基于布局确定的系统变化以及可以基于平版印刷过程确定的预期随机变化。

6. 发明授权

US08601420B1 Equivalent waveform model for static timing analysis of integrated circuit designs 有权
标题翻译：集成电路设计静态时序分析的等效波形模型
公开(公告)号：US08601420B1
公开(公告)日：2013-12-03
申请号：US12960387
申请日：2010-12-03
申请人： Igor Keller , Joel R. Phillips , Jijun Chen
发明人： Igor Keller , Joel R. Phillips , Jijun Chen
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/50 , G06F17/5036 , G06F2217/84
摘要： In one embodiment, a method of constructing an equivalent waveform model for static timing analysis of integrated circuit designs is disclosed. The method includes fitting time point coefficients (qk) and known time delay values from a delay and slew model of a receiving gate from a timing library; determining waveform values (Ikj) for input waveforms from the timing library; determining timing values (dj) from a timing table in the timing library in response to the input waveforms of the timing library; and determining coefficients (qk) by minimizing a residual of a delay equation.
摘要翻译：在一个实施例中，公开了一种构建用于集成电路设计的静态时序分析的等效波形模型的方法。该方法包括从定时库中接收来自延迟和转换模型的时间点系数（qk）和已知的时间延迟值; 从定时库确定输入波形的波形值（Ikj）; 响应于定时库的输入波形从定时库中的定时表确定定时值（dj）; 以及通过使延迟方程的残差最小化来确定系数（qk）。

7. 发明授权

US08375343B1 Methods and apparatus for waveform based variational static timing analysis 有权
标题翻译：基于波形变分静态时序分析的方法和装置
公开(公告)号：US08375343B1
公开(公告)日：2013-02-12
申请号：US12331172
申请日：2008-12-09
申请人： Saurabh K. Tiwary , Joel R. Phillips , Igor Keller
发明人： Saurabh K. Tiwary , Joel R. Phillips , Igor Keller
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A system and method are disclosed for waveform based variational static timing analysis. A circuit is divided into its linear circuit parts and non-linear circuit parts and modeled together, by a combination of linear modeling techniques, into linear equations that may be represented by matrices. The linear equations in matrix form may be readily solved by a computer such that an input waveform to an input pin of the circuit can be sequentially “pushed” through the various interconnects and logic networks of the circuit to an output pin. Output voltage waveforms are obtained at each stage of the waveform pushing and may be used to perform static timing analysis.
摘要翻译：公开了一种基于波形变分静态时序分析的系统和方法。电路分为线性电路部分和非线性电路部分，并通过线性建模技术的组合建模在一起，形成可以由矩阵表示的线性方程组。矩阵形式的线性方程式可以由计算机容易地解决，使得可以将电路的输入引脚的输入波形顺序推送到电路的各种互连和逻辑网络到输出引脚。在波形推送的每个阶段获得输出电压波形，可用于执行静态时序分析。

8. 发明授权

US07590518B2 Circuit analysis utilizing rank revealing factorization 失效
标题翻译：电路分析利用秩揭示因式分解
公开(公告)号：US07590518B2
公开(公告)日：2009-09-15
申请号：US10932406
申请日：2004-09-02
申请人： Joel R. Phillips
发明人： Joel R. Phillips
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： Method of forming a reduced model of a circuit. A circuit parameter is selected, and a plurality of values for the parameter are selected. A circuit or operator equation is solved for the selected plurality of values to generate a result. The acts of selecting parameter and its plurality of values and solving the equation are repeated to generate sufficient results to form a reduced model. For each iteration, a rank revealing factorization is performed on the matrix for use in determining whether a sufficient number of results or vectors have been generated to form the reduced model so as to form a reduced model. In the plurality of values for a selected parameter, there may exist large deviation between two of the plurality of values for a selected parameter, and such deviation need not be based upon a nominal point or deviation thereof.
摘要翻译：形成电路简化模型的方法。选择电路参数，并且选择参数的多个值。解决所选择的多个值的电路或算子方程式以产生结果。重复选择参数及其多个值并求解该方程的行为以产生足够的结果以形成简化的模型。对于每个迭代，对矩阵执行等级揭示因式分解，以用于确定是否已经产生足够数量的结果或向量以形成简化模型以形成简化模型。在所选参数的多个值中，对于所选择的参数，可能存在两个多个值之间的大偏差，并且这种偏差不需要基于标称点或其偏差。

9. 发明授权

US08631369B1 Methods, systems, and apparatus for timing and signal integrity analysis of integrated circuits with semiconductor process variations 有权
标题翻译：具有半导体工艺变化的集成电路的定时和信号完整性分析的方法，系统和装置
公开(公告)号：US08631369B1
公开(公告)日：2014-01-14
申请号：US12981504
申请日：2010-12-30
申请人： Vinod Kariat , Joel R. Phillips , Igor Keller
发明人： Vinod Kariat , Joel R. Phillips , Igor Keller
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： In one embodiment of the invention, a method of statically analyzing an integrated circuit with process and environment variations is provided. The method includes characterizing each circuit cell of a cell library for a sensitivity to process parameter variations within a predetermined range; creating a timing graph corresponding to a netlist representing an integrated circuit design; along nodes of the timing graph, computing delay values including sensitivities to process variations; for each selected output node of the netlist, propagating a full timing value function with the sensitivities to the selected output nodes; and generating a parameterized timing report including the sensitivities to the process variations.
摘要翻译：在本发明的一个实施例中，提供了一种静态分析具有过程和环境变化的集成电路的方法。该方法包括表征单元库的每个电路单元以便在预定范围内处理参数变化的灵敏度; 创建对应于表示集成电路设计的网表的时序图; 沿着定时图的节点计算包括对过程变化的敏感度的延迟值; 对于网表的每个选择的输出节点，传播具有对所选输出节点的灵敏度的完整定时值函数; 以及生成包括对所述过程变化的灵敏度的参数化定时报告。

10. 发明授权

US08341567B1 Boolean satisfiability based verification of analog circuits 有权
标题翻译：基于布尔可满足性的模拟电路验证
公开(公告)号：US08341567B1
公开(公告)日：2012-12-25
申请号：US12345449
申请日：2008-12-29
申请人： Saurabh K. Tiwary , Anubhav Gupta , Joel R. Phillips , Claudio Pinello , Radu Zlatanovici
发明人： Saurabh K. Tiwary , Anubhav Gupta , Joel R. Phillips , Claudio Pinello , Radu Zlatanovici
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5036 , G06F17/504
摘要： A method is provided to formally verify a property of a circuit design comprising: receiving a description of at least a portion of the circuit; receiving an indication of search accuracy criteria; receiving a description of a relationship between current and voltage (I-V relationship) for one or more of devices of the circuit; converting each I-V relationship to a conservative approximation of such I-V relationship; assigning voltage labels to one or more terminals of one or more identified devices that indicate voltage relationships among the one or more terminals consistent with KVL; defining a respective current relationship among one or more respective sets of currents of the one or more of the identified devices that is consistent with KCL; searching for one or more combinations of current and voltage values that are within at least one region of each conservative approximation and that are consistent with the voltage labels and that are consistent with each respective defined current relationship; converting each region determined to have a searched for combination of current and voltage values to multiple respective smaller regions; and repeating the acts of searching and converting until regions are obtained that meet the received search accuracy criteria.
摘要翻译：提供了一种用于正式验证电路设计的属性的方法，包括：接收电路的至少一部分的描述; 接收搜索精度准则的指示; 接收电路中的一个或多个设备的电流和电压之间的关系（I-V关系）的描述; 将每个I-V关系转换成这种I-V关系的保守近似值; 将电压标签分配给指示符合KVL的一个或多个终端之间的电压关系的一个或多个识别设备的一个或多个终端; 定义与KCL一致的所识别设备中的一个或多个的一个或多个相应电流集合中的相应电流关系; 搜索在每个保守近似的至少一个区域内并且与电压标签一致并且与每个相应限定的电流关系一致的电流和电压值的一个或多个组合; 将确定为将搜索到的电流和电压值的组合的每个区域转换为多个相应的较小区域; 并重复搜索和转换的行为，直到获得满足所接收到的搜索精度标准的区域。

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