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1. 发明申请

US20170316955A1 POWER MODULE PACKAGE HAVING PATTERNED INSULATION METAL SUBSTRATE 有权
公开(公告)号：US20170316955A1
公开(公告)日：2017-11-02
申请号：US15142458
申请日：2016-04-29
申请人： Delta Electronics, Inc.
发明人： Hsin-Chang TSAI , Chia-Yen LEE , Peng-Hsin LEE
IPC分类号： H01L21/48 , H01L23/498 , B32B37/12
CPC分类号： H01L21/4857 , B32B37/12 , B32B2307/202 , H01L21/4839 , H01L21/486 , H01L23/49503 , H01L23/49541 , H01L23/49562 , H01L23/49575 , H01L23/49582 , H01L23/49827 , H01L23/49844 , H01L23/49861 , H01L2224/0603 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/19105 , H01L2924/19107 , H01L2924/00014
摘要： A power module package is provided, including a substrate, a first chip, and a second chip. The substrate includes a metal carrier, a patterned insulation layer disposed on the metal carrier and partially covering the metal carrier, and a patterned conductive layer disposed on the patterned insulation layer. The first chip is disposed on the metal carrier not covered by the patterned insulation layer. The second chip is disposed on the patterned conductive layer and electrically connected to the first chip.

2. 发明申请

US20170317014A1 POWER MODULE PACKAGE HAVING PATTERNED INSULATION METAL SUBSTRATE 有权
公开(公告)号：US20170317014A1
公开(公告)日：2017-11-02
申请号：US15142588
申请日：2016-04-29
申请人： Delta Electronics, Inc.
发明人： Hsin-Chang TSAI , Chia-Yen LEE , Peng-Hsin LEE
IPC分类号： H01L23/495 , H01L21/48 , H01L23/00
CPC分类号： H01L23/49575 , H01L21/4839 , H01L23/49503 , H01L23/49531 , H01L23/49541 , H01L23/49558 , H01L23/49562 , H01L23/49582 , H01L24/48 , H01L24/49 , H01L2224/48091 , H01L2224/48137 , H01L2224/49111 , H01L2924/01007 , H01L2924/01029 , H01L2924/01031 , H01L2924/13064
摘要： A power module package is provided, including a substrate, a first chip, and a second chip. The substrate includes a metal carrier, a patterned insulation layer disposed on the metal carrier and partially covering the metal carrier, and a patterned conductive layer disposed on the patterned insulation layer. The first chip is disposed on the metal carrier not covered by the patterned insulation layer. The second chip is disposed on the patterned conductive layer and electrically connected to the first chip.

3. 发明申请

US20150125995A1 METHOD OF FORMING PACKAGE STRUCTURE 审中-公开
标题翻译：形成包装结构的方法
公开(公告)号：US20150125995A1
公开(公告)日：2015-05-07
申请号：US14591551
申请日：2015-01-07
申请人： Delta Electronics, Inc.
发明人： Chia-Yen LEE , Hsin-Chang TSAI , Peng-Hsin LEE
IPC分类号： H01L25/00 , H01L21/768 , H01L25/065
CPC分类号： H01L25/50 , H01L21/768 , H01L21/76877 , H01L21/76898 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L25/074 , H01L25/18 , H01L2224/02372 , H01L2224/0332 , H01L2224/0401 , H01L2224/05009 , H01L2224/05147 , H01L2224/05548 , H01L2224/0557 , H01L2224/06181 , H01L2224/13024 , H01L2224/131 , H01L2224/13147 , H01L2224/16146 , H01L2224/16148 , H01L2224/81193 , H01L2224/81815 , H01L2924/00014 , H01L2924/12042 , H01L2924/00012 , H01L2224/05599 , H01L2924/014 , H01L2224/05552 , H01L2924/00
摘要： A package structure including: a first semiconductor device including a first semiconductor substrate and a first electronic device, the first semiconductor device having a first side and a second side, wherein at least part of the first electronic device being adjacent to the first side, and the first semiconductor device has a via-hole formed through the first semiconductor device, wherein the via-hole has a first opening adjacent to the first side; an interconnection structure disposed in the first semiconductor device, wherein the interconnection structure includes: a via structure disposed in the via-hole without exceeding the first opening; a first pad disposed on the first side of the first semiconductor device and covering the via-hole; and a second semiconductor device vertically integrated with the first semiconductor device.
摘要翻译：一种封装结构，包括：第一半导体器件，包括第一半导体衬底和第一电子器件，所述第一半导体器件具有第一侧面和第二侧面，其中所述第一电子器件的至少部分与所述第一侧相邻，以及第一半导体器件具有通过第一半导体器件形成的通孔，其中通孔具有与第一侧相邻的第一开口; 布置在所述第一半导体器件中的互连结构，其中所述互连结构包括：通孔结构，其设置在所述通孔中而不超过所述第一开口; 第一焊盘，设置在所述第一半导体器件的第一侧上并覆盖所述通孔; 以及与第一半导体器件垂直集成的第二半导体器件。

4. 发明申请

US20150001727A1 EMBEDDED PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THEREOF 有权
标题翻译：嵌入式包装结构及其制造方法
公开(公告)号：US20150001727A1
公开(公告)日：2015-01-01
申请号：US13930949
申请日：2013-06-28
申请人： DELTA ELECTRONICS, INC.
发明人： Chia-Yen LEE , Hsin-Chang TSAI , Peng-Hsin LEE
IPC分类号： H01L23/498 , H01L23/00
CPC分类号： H01L24/85 , H01L23/492 , H01L23/49894 , H01L23/5389 , H01L24/06 , H01L24/16 , H01L24/24 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/82 , H01L2224/0401 , H01L2224/06181 , H01L2224/16245 , H01L2224/24137 , H01L2224/291 , H01L2224/2919 , H01L2224/32145 , H01L2224/32245 , H01L2224/73253 , H01L2224/73267 , H01L2224/82031 , H01L2224/82039 , H01L2224/82101 , H01L2224/85 , H01L2224/92244 , H01L2924/00014 , H01L2924/12042 , H01L2924/014 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： The disclosure provides an embedded package structure comprising a metal substrate, a chip module, an insulation material layer, and at least one patterned metal layer. The metal substrate has a first surface and a second surface. The chip module is disposed on the first surface of the metal substrate, and comprises at least two stacked chips being electrically connected to each. The insulation material layer covers the first surface of the metal substrate and the stacked chips and has an electrical interconnection formed therein. The patterned metal layer is positioned on the insulation material layer, and is electrically connected the chip module through the electrical interconnection. The method for manufacturing the embedded package structure also provides.
摘要翻译：本公开提供了一种嵌入式封装结构，其包括金属基板，芯片模块，绝缘材料层和至少一个图案化的金属层。金属基板具有第一表面和第二表面。芯片模块设置在金属基板的第一表面上，并且包括至少两个堆叠的芯片，其电连接到每个。绝缘材料层覆盖金属基板的第一表面和堆叠的芯片，并且其中形成有电互连。图案化的金属层位于绝缘材料层上，并且通过电互连电连接芯片模块。嵌入式封装结构的制造方法也提供了。

5. 发明申请

US20200251405A1 MANUFACTURING METHOD OF PACKAGING DEVICE 审中-公开
公开(公告)号：US20200251405A1
公开(公告)日：2020-08-06
申请号：US16856797
申请日：2020-04-23
申请人： DELTA ELECTRONICS, INC.
发明人： Hsin-Chang TSAI , Chia-Yen LEE , Peng-Hsin LEE
IPC分类号： H01L23/433 , H01L23/31
摘要： A packaging device including a first semiconductor device, a thermal dissipating component, an encapsulation layer, a via, and a pad. The first semiconductor device includes a substrate, an active region, and an electrode. The active region is disposed between the substrate and the electrode. The substrate has a first surface opposite to the active region, and the electrode has a second surface opposite to the active region. The thermal dissipating component is disposed on the first surface of the substrate. The encapsulation layer encloses the second surface of the electrode and a part of the thermal dissipating component, such that another part of the thermal dissipating component is exposed by the encapsulation layer. The pad is disposed on the encapsulation layer. The via is disposed in the encapsulation layer and connects the pad to the electrode.

6. 发明申请

US20170317015A1 POWER MODULE PACKAGE HAVING PATTERNED INSULATION METAL SUBSTRATE 审中-公开
公开(公告)号：US20170317015A1
公开(公告)日：2017-11-02
申请号：US15484714
申请日：2017-04-11
申请人： Delta Electronics, Inc.
发明人： Chia-Yen LEE , Hsin-Chang TSAI , Peng-Hsin LEE , Shiau-Shi LIN , Tzu-Hsuan CHENG
IPC分类号： H01L23/495 , H01L23/31 , H01L23/00 , H01L25/065 , H01L23/29
CPC分类号： H01L23/49586 , H01L23/29 , H01L23/3114 , H01L23/49575 , H01L24/09 , H01L24/48 , H01L24/49 , H01L25/0655 , H01L2224/0233 , H01L2224/40245 , H01L2224/48137 , H01L2224/49105 , H01L2924/13064 , H01L2924/19105
摘要： A packaging structure is provided, including a substrate, a first chip, a second chip, and a conductive unit. The substrate includes a metal carrier, a patterned insulation layer disposed on the metal carrier and partially covering the metal carrier, and a patterned conductive layer disposed on the patterned insulation layer. The first chip is disposed on the metal carrier not covered by the patterned insulation layer. The second chip is disposed on the patterned conductive layer and electrically connected to the first chip by the conductive unit.

7. 发明申请

US20140131871A1 INTERCONNECTION STRUCTURE AND FABRICATION THEREOF 有权
标题翻译：互连结构与制造
公开(公告)号：US20140131871A1
公开(公告)日：2014-05-15
申请号：US13675297
申请日：2012-11-13
申请人： DELTA ELECTRONICS, INC.
发明人： Hsin-Chang TSAI , Chia-Yen LEE , Peng-Hisn LEE
IPC分类号： H01L23/00 , H01L23/48
CPC分类号： H01L21/76898 , H01L21/268 , H01L21/2885 , H01L21/76834 , H01L21/76879 , H01L21/76895 , H01L23/481 , H01L23/49562 , H01L23/49575 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/81 , H01L24/91 , H01L25/074 , H01L25/18 , H01L25/50 , H01L2224/02372 , H01L2224/0332 , H01L2224/0401 , H01L2224/05009 , H01L2224/05147 , H01L2224/05548 , H01L2224/05557 , H01L2224/0557 , H01L2224/06181 , H01L2224/13024 , H01L2224/131 , H01L2224/13147 , H01L2224/16146 , H01L2224/16147 , H01L2224/16148 , H01L2224/16238 , H01L2224/17181 , H01L2224/73221 , H01L2224/73255 , H01L2224/73257 , H01L2224/81193 , H01L2224/81815 , H01L2924/00014 , H01L2924/12042 , H01L2924/13064 , H01L2924/00012 , H01L2224/05599 , H01L2924/014 , H01L2924/00 , H01L2224/05552
摘要： A method of forming an interconnection structure is disclosed, including providing a substrate having a first side and a second side opposite to the first side, forming a via hole through the substrate, wherein the via hole has a first opening in the first side and a second opening in the second side, forming a first pad covering the first opening, and forming a via structure in the via hole subsequent to forming the first pad, wherein the via structure includes a conductive material and is adjoined to the first pad.
摘要翻译：公开了一种形成互连结构的方法，包括提供具有第一侧和与第一侧相对的第二侧的基板，通过基板形成通孔，其中通孔在第一侧具有第一开口，在第二侧形成第二开口，形成覆盖第一开口的第一焊盘，以及在形成第一焊盘之后在通孔中形成通孔结构，其中通孔结构包括导电材料并与第一焊盘邻接。

8. 发明申请

US20210373533A1 METHOD FOR PREDICTING AND COMPENSATING FRICTIONS OF FEED SYSTEM, AND COMPUTER READABLE STORAGE 有权
公开(公告)号：US20210373533A1
公开(公告)日：2021-12-02
申请号：US17031235
申请日：2020-09-24
申请人： Delta Electronics, Inc.
发明人： Chia-Yen LEE , Yu-Hsiang CHENG , Chia-Hui CHEN , Ping-Chun TSAI
IPC分类号： G05B19/416 , G05B23/02 , G05B19/414
摘要： A method for predicting and compensating frictions of a feed system includes following steps: constantly obtaining current signals and angle-position signals of a motor by a motor driver of a feed system after being activated; calculating frictions of the motor upon each rotating position according to the obtained current signals and angle-position signals and generating multiple records of friction data; creating a friction model according to the multiple records of friction data and the angle-position signals each respectively corresponding to each record of friction data with respect to each rotating position; importing current angle-position signal of the motor to the friction model for predicting a predicted friction; calculating a compensation current based on the predicted friction; and, controlling the motor driver to additionally provide the compensation current to the motor for conquering an upcoming friction of the feed system approximate to the predicted friction.

9. 发明申请

US20150348889A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20150348889A1
公开(公告)日：2015-12-03
申请号：US14291563
申请日：2014-05-30
申请人： DELTA ELECTRONICS, INC.
发明人： Hsin-Chang TSAI , Chia-Yen LEE , Peng-Hsin LEE
IPC分类号： H01L23/495 , H01L25/07
CPC分类号： H01L23/49562 , H01L23/49503 , H01L23/49524 , H01L23/49541 , H01L23/49548 , H01L23/49575 , H01L24/34 , H01L24/37 , H01L24/40 , H01L24/41 , H01L25/072 , H01L2224/0603 , H01L2224/32245 , H01L2224/371 , H01L2224/40245 , H01L2924/00014 , H01L2224/84
摘要： A semiconductor device includes a lead frame, a first semiconductor component, a second semiconductor component, and a first conductive member. The lead frame includes a first segment having a first bottom plate, and a second segment having a second bottom plate. The first segment and the second segment are arranged side by side, the first bottom plate is spatially isolated from the second bottom plate, and the first bottom plate is thicker than the second bottom plate. The first semiconductor component is disposed on the first bottom plate, and the second semiconductor component is disposed on the second bottom plate. The second semiconductor component is thicker than the first semiconductor component. The first conductive member electrically connects the second semiconductor component to the first segment.
摘要翻译：半导体器件包括引线框架，第一半导体部件，第二半导体部件和第一导电部件。引线框架包括具有第一底板的第一段和具有第二底板的第二段。第一段和第二段并排布置，第一底板在空间上与第二底板隔离，第一底板比第二底板厚。第一半导体部件设置在第一底板上，第二半导体部件设置在第二底板上。第二半导体部件比第一半导体部件厚。第一导电部件将第二半导体部件电连接到第一部分。

10. 发明申请

US20140185126A1 ELECTROWETTING CELLS AND DRIVING METHODS THEREFOR 审中-公开
标题翻译：电镀细胞及其驱动方法
公开(公告)号：US20140185126A1
公开(公告)日：2014-07-03
申请号：US13728665
申请日：2012-12-27
申请人： DELTA ELECTRONICS, INC
发明人： Rong-Chang LIANG , Ching-Tung HSU , Yeong-Feng WANG , Ming-Wei TSAI , Chia-Yen LEE , Meng-Han LIU , Yen-I CHOU
IPC分类号： G02B26/00
CPC分类号： G02B26/005 , G09G3/348 , G09G2310/065
摘要： An electrowetting cell includes first and second substrates, a spacer, first and second electrodes, a dielectric layer, and a medium. The spacer is disposed between the first and second substrates to substrate define a compartment. The first and second electrodes are disposed on the first and second substrates respectively. The dielectric layer is formed on the first electrode. The medium is filled in the compartment and deformed in accordance with an electric potential difference between the first and second electrodes. One of the first and second electrodes is applied by a driving signal. The driving signal is divided into a plurality of driving sections in a first time period. A first driving section is changed between first and second threshold voltage levels, and a horizontal voltage level is inserted into the first driving section.
摘要翻译：电润湿单元包括第一和第二基板，间隔件，第一和第二电极，电介质层和介质。间隔件设置在第一和第二基板之间，基板限定隔室。第一和第二电极分别设置在第一和第二基板上。介电层形成在第一电极上。介质填充在隔室中并根据第一和第二电极之间的电位差而变形。通过驱动信号施加第一和第二电极中的一个。驱动信号在第一时间段被分成多个驱动部分。在第一和第二阈值电压电平之间改变第一驱动部分，并且将水平电压电平插入到第一驱动部分中。

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