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1. 发明申请

US20110258844A1 METHOD OF MANUFACTURING A POWER TRANSISTOR MODULE AND PACKAGE WITH INTEGRATED BUS BAR 有权
标题翻译：一个功率晶体管模块和集成总线的封装方法
公开(公告)号：US20110258844A1
公开(公告)日：2011-10-27
申请号：US13174048
申请日：2011-06-30
申请人： Cynthia Blair , Donald Fowlkes
发明人： Cynthia Blair , Donald Fowlkes
IPC分类号： H01C17/00
CPC分类号： H01L24/49 , H01L23/66 , H01L24/48 , H01L2223/6644 , H01L2223/665 , H01L2224/48 , H01L2224/48195 , H01L2224/49175 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01072 , H01L2924/01074 , H01L2924/01077 , H01L2924/19041 , H01L2924/19105 , H01L2924/30105 , H01L2924/30107 , Y10T29/49082 , Y10T29/49169 , H01L2224/45099
摘要： According to an embodiment of a method of manufacturing a power transistor module, the method includes mechanically fastening a first terminal, a second terminal and at least two different DC bias terminals to an electrically conductive flange; connecting the flange to a source of a power transistor device; electrically connecting the first terminal to a gate of the power transistor device; electrically connecting the second terminal to a drain of the power transistor device; mechanically fastening a bus bar to the flange which extends between and connects the DC bias terminals; and electrically connecting the bus bar to the drain via one or more RF grounded connections.
摘要翻译：根据制造功率晶体管模块的方法的实施例，该方法包括将第一端子，第二端子和至少两个不同的DC偏置端子机械地紧固到导电凸缘; 将法兰连接到功率晶体管器件的源极; 将第一端子电连接到功率晶体管器件的栅极; 将所述第二端子电连接到所述功率晶体管器件的漏极; 将母线机械地紧固到在DC偏置端子之间延伸并连接到DC偏置端子的凸缘; 并且经由一个或多个RF接地连接将母线电连接到漏极。

2. 发明授权

US08299856B2 Power transistor output match network with high Q RF path and low Q low frequency path 有权
标题翻译：功率晶体管输出与高Q RF路径和低Q低频路径匹配网络
公开(公告)号：US08299856B2
公开(公告)日：2012-10-30
申请号：US12973613
申请日：2010-12-20
申请人： Cynthia Blair
发明人： Cynthia Blair
IPC分类号： H03F3/191
CPC分类号： H03F3/195 , H01L23/66 , H01L24/49 , H01L2223/6655 , H01L2223/6666 , H01L2224/45014 , H01L2224/49175 , H01L2924/00014 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H03F1/565 , H03F2200/387 , Y10T29/4913 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： A power circuit includes a power device, an output match network and a bypass network. The output match network is coupled to an output of the power device and includes a blocking capacitor which forms part of a high quality factor RF path of the output match network. The output match network is operable to provide a range of impedance matching over a signal bandwidth and a low frequency gain peak outside the signal bandwidth which corresponds to a low frequency resonance of the high quality factor RF path. The bypass network is coupled in parallel with the blocking capacitor of the output match network. The bypass network is operable to attenuate the low frequency gain peak while maintaining the high quality factor RF path.
摘要翻译：电源电路包括电源设备，输出匹配网络和旁路网络。输出匹配网络耦合到功率器件的输出，并且包括构成输出匹配网络的高品质因子RF路径的一部分的阻塞电容器。输出匹配网络可操作以在对应于高品质因子RF路径的低频谐振的信号带宽之外的信号带宽和低频增益峰值之间提供一定范围的阻抗匹配。旁路网络与输出匹配网络的阻塞电容并联耦合。旁路网络可操作以在保持高质量因子RF路径的同时衰减低频增益峰值。

3. 发明申请

US20100200979A1 Power Transistor Package with Integrated Bus Bar 有权
标题翻译：带集成母线的功率晶体管封装
公开(公告)号：US20100200979A1
公开(公告)日：2010-08-12
申请号：US12367719
申请日：2009-02-09
申请人： Cynthia Blair , Donald Fowlkes
发明人： Cynthia Blair , Donald Fowlkes
IPC分类号： H01L23/48 , H05K13/00
CPC分类号： H01L24/49 , H01L23/66 , H01L24/48 , H01L2223/6644 , H01L2223/665 , H01L2224/48 , H01L2224/48195 , H01L2224/49175 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01072 , H01L2924/01074 , H01L2924/01077 , H01L2924/19041 , H01L2924/19105 , H01L2924/30105 , H01L2924/30107 , Y10T29/49082 , Y10T29/49169 , H01L2224/45099
摘要： According to one embodiment, a power transistor package includes an electrically conductive flange configured to be connected to a source of a power transistor device. The package further includes a first terminal mechanically fastened to the flange and configured to be electrically connected to a gate of the power transistor device and a second terminal mechanically fastened to the flange and configured to be electrically connected to a drain of the power transistor device. The package also includes a bus bar mechanically fastened to the flange which extends between and connects at least two different DC bias terminals mechanically fastened to the flange. The bus bar is configured to be electrically connected to the drain via one or more RF grounded connections.
摘要翻译：根据一个实施例，功率晶体管封装包括被配置为连接到功率晶体管器件的源极的导电凸缘。所述封装还包括机械地紧固到所述凸缘并被配置为电连接到所述功率晶体管器件的栅极的第一端子和机械地紧固到所述凸缘并被配置为电连接到所述功率晶体管器件的漏极的第二端子。该包装还包括机械地紧固到凸缘的汇流条，该汇流条在凸缘之间延伸并连接至少两个机械地紧固到凸缘的DC偏压端子。母线被配置成通过一个或多个RF接地连接电连接到漏极。

4. 发明申请

US20100097155A1 Stripline Balun 有权
公开(公告)号：US20100097155A1
公开(公告)日：2010-04-22
申请号：US12253323
申请日：2008-10-17
申请人： Cynthia Blair
发明人： Cynthia Blair
IPC分类号： H01P5/107 , H01P11/00
CPC分类号： H01P5/10 , Y10T29/4902
摘要： According to one embodiment, a balun includes one or more transformers configured to block DC power between a line and a device at microwave frequencies. The one or more transformers block DC power between the line and the device by electromagnetically coupling the device to the line.
摘要翻译：根据一个实施例，平衡 - 不平衡变压器包括被配置为在微波频率处阻断线路和器件之间的直流电力的一个或多个变压器。一个或多个变压器通过将设备电磁耦合到线路来阻断线路和器件之间的直流电力。

5. 发明授权

US08258014B2 Method of manufacturing a power transistor module and package with integrated bus bar 有权
标题翻译：集成母线制造功率晶体管模块和封装的方法
公开(公告)号：US08258014B2
公开(公告)日：2012-09-04
申请号：US13174048
申请日：2011-06-30
申请人： Cynthia Blair , Donald Fowlkes
发明人： Cynthia Blair , Donald Fowlkes
IPC分类号： H01L23/48
CPC分类号： H01L24/49 , H01L23/66 , H01L24/48 , H01L2223/6644 , H01L2223/665 , H01L2224/48 , H01L2224/48195 , H01L2224/49175 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01072 , H01L2924/01074 , H01L2924/01077 , H01L2924/19041 , H01L2924/19105 , H01L2924/30105 , H01L2924/30107 , Y10T29/49082 , Y10T29/49169 , H01L2224/45099
摘要： According to an embodiment of a method of manufacturing a power transistor module, the method includes mechanically fastening a first terminal, a second terminal and at least two different DC bias terminals to an electrically conductive flange; connecting the flange to a source of a power transistor device; electrically connecting the first terminal to a gate of the power transistor device; electrically connecting the second terminal to a drain of the power transistor device; mechanically fastening a bus bar to the flange which extends between and connects the DC bias terminals; and electrically connecting the bus bar to the drain via one or more RF grounded connections.
摘要翻译：根据制造功率晶体管模块的方法的实施例，该方法包括将第一端子，第二端子和至少两个不同的DC偏置端子机械地紧固到导电凸缘; 将法兰连接到功率晶体管器件的源极; 将第一端子电连接到功率晶体管器件的栅极; 将所述第二端子电连接到所述功率晶体管器件的漏极; 将母线机械地紧固到在DC偏置端子之间延伸并连接到DC偏置端子的凸缘; 并且经由一个或多个RF接地连接将母线电连接到漏极。

6. 发明申请

US20120154053A1 Power Transistor Output Match Network with High Q RF Path and Low Q Low Frequency Path 有权
标题翻译：功率晶体管输出匹配网络与高Q射频路径和低Q低频路径
公开(公告)号：US20120154053A1
公开(公告)日：2012-06-21
申请号：US12973613
申请日：2010-12-20
申请人： Cynthia Blair
发明人： Cynthia Blair
IPC分类号： H03G3/30 , H05K3/30
CPC分类号： H03F3/195 , H01L23/66 , H01L24/49 , H01L2223/6655 , H01L2223/6666 , H01L2224/45014 , H01L2224/49175 , H01L2924/00014 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H03F1/565 , H03F2200/387 , Y10T29/4913 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： A power circuit includes a power device, an output match network and a bypass network. The output match network is coupled to an output of the power device and includes a blocking capacitor which forms part of a high quality factor RF path of the output match network. The output match network is operable to provide a range of impedance matching over a signal bandwidth and a low frequency gain peak outside the signal bandwidth which corresponds to a low frequency resonance of the high quality factor RF path. The bypass network is coupled in parallel with the blocking capacitor of the output match network. The bypass network is operable to attenuate the low frequency gain peak while maintaining the high quality factor RF path.
摘要翻译：电源电路包括电源设备，输出匹配网络和旁路网络。输出匹配网络耦合到功率器件的输出，并且包括构成输出匹配网络的高品质因子RF路径的一部分的阻塞电容器。输出匹配网络可操作以在对应于高品质因子RF路径的低频谐振的信号带宽之外的信号带宽和低频增益峰值之间提供一定范围的阻抗匹配。旁路网络与输出匹配网络的阻塞电容并联耦合。旁路网络可操作以在保持高质量因子RF路径的同时衰减低频增益峰值。

7. 发明授权

US07902939B2 Stripline balun 有权
标题翻译：平衡不平衡变压器
公开(公告)号：US07902939B2
公开(公告)日：2011-03-08
申请号：US12253323
申请日：2008-10-17
申请人： Cynthia Blair
发明人： Cynthia Blair
IPC分类号： H03H7/42 , H01P3/08
CPC分类号： H01P5/10 , Y10T29/4902
摘要： According to one embodiment, a balun includes one or more transformers configured to block DC power between a line and a device at microwave frequencies. The one or more transformers block DC power between the line and the device by electromagnetically coupling the device to the line.
摘要翻译：根据一个实施例，平衡 - 不平衡变压器包括被配置为在微波频率处阻断线路和器件之间的直流电力的一个或多个变压器。一个或多个变压器通过将设备电磁耦合到线路来阻断线路和器件之间的直流电力。

8. 发明授权

US06304129B1 Compensation circuit and method for a power transistor 失效
标题翻译：功率晶体管的补偿电路和方法
公开(公告)号：US06304129B1
公开(公告)日：2001-10-16
申请号：US09415524
申请日：1999-10-08
申请人： Cynthia Blair , Henrik Sjoden
发明人： Cynthia Blair , Henrik Sjoden
IPC分类号： H03K1714
CPC分类号： H03F3/191 , H03F1/301 , H03F2200/15 , H03F2200/18 , H03F2200/456
摘要： A circuit and method are disclosed for biasing a power transistor to offset unwanted variations in the operating characteristics thereof. The circuit includes a correction transistor having the same device structure as the structure of the power transistor. In addition, one or more dimensions of the correction transistor is scaled relative to corresponding dimensions of the power transistor. The correction transistor is biased so that the ratio of drain currents of the correction transistor and the power transistor is the same as the size ratio thereof. In this way, the output signal of the correction transistor is based upon an unwanted variation in the operating characteristics of the power transistor. The output terminal of the correction transistor is amplified and coupled to the control terminal of the power transistor so that the bias signal applied to the control terminal thereof offsets the unwanted variation in the operating characteristics of the power transistor.
摘要翻译：公开了用于偏置功率晶体管以消除其工作特性中的不期望的变化的电路和方法。该电路包括具有与功率晶体管的结构相同的器件结构的校正晶体管。此外，校正晶体管的一个或多个维度相对于功率晶体管的相应尺寸缩放。校正晶体管被偏置，使得校正晶体管和功率晶体管的漏极电流的比率与其尺寸比相同。以这种方式，校正晶体管的输出信号基于功率晶体管的工作特性的不期望的变化。校正晶体管的输出端被放大并耦合到功率晶体管的控制端，使得施加到其控制端的偏置信号抵消功率晶体管的工作特性的不期望的变化。

9. 发明授权

US07728671B2 Semiconductor power device with bias circuit 有权
标题翻译：具有偏置电路的半导体功率器件
公开(公告)号：US07728671B2
公开(公告)日：2010-06-01
申请号：US12015890
申请日：2008-01-17
申请人： Cynthia Blair , Prasanth Perugupalli
发明人： Cynthia Blair , Prasanth Perugupalli
IPC分类号： H03F1/26
CPC分类号： H03F1/565 , H01L23/66 , H01L24/48 , H01L24/49 , H01L2223/6644 , H01L2223/6655 , H01L2224/48091 , H01L2224/49111 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01033 , H01L2924/01068 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/19051 , H01L2924/30105 , H01L2924/30107 , H03F1/301 , H03F3/195 , H03F3/245 , H03F2200/18 , H03F2200/222 , H03F2200/387 , H03F2200/451 , H01L2224/45099 , H01L2224/05599
摘要： An RF power circuit comprises a power transistor having a gate and drain, an output matching network coupled to the drain and an input matching network coupled to the gate. A closed-loop bias circuit is integrated with the power transistor on the same die and coupled to the gate for biasing the RF power transistor based on a reference voltage applied to the bias circuit.
摘要翻译： RF功率电路包括具有栅极和漏极的功率晶体管，耦合到漏极的输出匹配网络和耦合到栅极的输入匹配网络。闭环偏置电路与同一管芯上的功率晶体管集成，并耦合到栅极，用于基于施加到偏置电路的参考电压来偏置RF功率晶体管。

10. 发明授权

US06573796B2 Automatic LDMOS biasing with long term hot carrier compensation 有权
标题翻译：自动LDMOS偏置长期热载波补偿
公开(公告)号：US06573796B2
公开(公告)日：2003-06-03
申请号：US09962975
申请日：2001-09-24
申请人： Cynthia Blair , Robert Bartola , Nagaraj V. Dixit
发明人： Cynthia Blair , Robert Bartola , Nagaraj V. Dixit
IPC分类号： H03F304
CPC分类号： H03F1/304 , H03F3/193
摘要： Disclosed are systems and methods for automatic biasing of LDMOS devices at turn-on. The invention provides bias point setting with compensation for hot carrier effects each time the LDMOS device is turned on and also provides temperature compensation during operation of the device. The systems and methods of the invention are scalable such that a plurality of LDMOS devices may simultaneously have their bias points set, and temperature compensation provided.
摘要翻译：公开了用于在开启时自动偏置LDMOS器件的系统和方法。本发明提供了每次LDMOS器件接通时补偿热载体效应的偏置点设置，并且还在器件的操作期间提供温度补偿。本发明的系统和方法是可扩展的，使得多个LDMOS设备可以同时设置其偏置点并提供温度补偿。

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