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1. 发明授权

US6105083A Apparatus and method for controlling transfer of data between and processing of data by interconnected data processing elements 失效
标题翻译：用于通过互连的数据处理元件来控制数据传输和数据处理之间的装置和方法
公开(公告)号：US6105083A
公开(公告)日：2000-08-15
申请号：US879981
申请日：1997-06-20
申请人： Jeffrey D. Kurtze , Craig R. Frink , James Hamilton , Frank C. Sarnowski , Raymond D. Cacciatore , Scott A. Markinson , Michael F. Lamenza , Anthony O'Connor , Hamed Eshraghian
发明人： Jeffrey D. Kurtze , Craig R. Frink , James Hamilton , Frank C. Sarnowski , Raymond D. Cacciatore , Scott A. Markinson , Michael F. Lamenza , Anthony O'Connor , Hamed Eshraghian
IPC分类号： G06F13/38 , G06F13/42 , H04N7/24 , H04N7/26 , H04N7/50
CPC分类号： G06F13/4213 , H04N19/42 , H04N19/61 , H04N7/24
摘要： The present invention provides a generic interface which enables asynchronous data processing elements to be interconnected using an interconnection protocol that controls flow of data between the processing elements. The flow control allows the processing elements to be data independent from, i.e., the processing elements need not be designed for a fixed sample rate or resolution, sample format and other data dependent factors. When used with digital motion video data, the processing elements may process motion video data at various temporal and spatial resolutions and color formats. Flow of data between processing elements may be controlled by handshake signals indicating whether the sender has valid data and the receiver can receive data. When valid data is available at the sender and is requested by the receiver, a transfer of data occurs. The characteristics of the data, and functions to be performed on the data may be specified using control inputs to the processing elements. A counting circuit may be used to specify the number of the data samples for which the control inputs are valid. The interface allows each processing element to have a small number of storage locations for storing data, such as a pair of registers, which eliminates the need for large buffers and simplifies implementation of the processing element with such flow control as a simple integrated circuit.
摘要翻译：本发明提供了一种通用接口，其使得能够使用控制处理元件之间的数据流的互连协议来互连异步数据处理元件。流量控制允许处理元件与数据无关，即处理元件不需要被设计用于固定的采样率或分辨率，采样格式和其他依赖于数据的因素。当与数字运动视频数据一起使用时，处理元件可以处理各种时间和空间分辨率和颜色格式的运动视频数据。处理元件之间的数据流可以由指示发送者是否具有有效数据并且接收方可以接收数据的握手信号来控制。当有效数据在发送器处可用并且被接收器请求时，发生数据传送。可以使用对处理元件的控制输入来指定数据的特性和对数据执行的功能。可以使用计数电路来指定控制输入有效的数据样本的数量。该接口允许每个处理元件具有用于存储数据的少量存储位置，诸如一对寄存器，其消除了对大缓冲器的需要并且简化了具有如简单集成电路的流量控制的处理元件的实现。

2. 发明授权

US06239815B1 Video data storage and transmission formats and apparatus and methods for processing video data in such formats 失效
标题翻译：视频数据存储和传输格式以及用于以这种格式处理视频数据的装置和方法
公开(公告)号：US06239815B1
公开(公告)日：2001-05-29
申请号：US09054321
申请日：1998-04-03
申请人： Craig R. Frink , Raymond D. Cacciatore , Hamed Eshraghian
发明人： Craig R. Frink , Raymond D. Cacciatore , Hamed Eshraghian
IPC分类号： G09G500
CPC分类号： H04N19/00 , H04N19/42 , H04N19/61
摘要： In order to efficiently use processing and transmission bandwidth and data storage of a computer system, video data is represented using integer and fractional values. The integer value has a precision defined by the precision of the data paths of the computer system. These integer and fractional components are packed into byte-oriented data packets in a manner that minimizes waste of storage space and transmission bandwidth. This packing of data also may be done in such a way so as to minimize processing for performing packing and unpacking of the data. Because the video data may be easily separated and combined into its integer and fractional components, these components may be processed or transported separately, in parallel or in series, and then later recombined. As a result, lower precision devices may be used in parallel to process or transport streams of higher precision data without having a high precision data processing or transport path.
摘要翻译：为了有效地使用计算机系统的处理和传输带宽和数据存储，使用整数和小数值来表示视频数据。整数值具有由计算机系统的数据路径的精度定义的精度。这些整数和分数组件以最小化浪费存储空间和传输带宽的方式打包成面向字节的数据包。数据的这种打包也可以以这样的方式完成，以便最小化用于执行打包和打包数据的处理。因为视频数据可以容易地分离并组合成其整数和分数分量，这些分量可以并行或串联地分开处理或传输，然后再重新组合。因此，较低精度的设备可以并行处理或传输更高精度数据的流，而不需要高精度的数据处理或传输路径。

3. 发明授权

US08266466B2 Globally synchronized timestamp value counter 有权
标题翻译：全局同步时间戳值计数器
公开(公告)号：US08266466B2
公开(公告)日：2012-09-11
申请号：US11804821
申请日：2007-05-21
申请人： Hamed Eshraghian , Werner Niebel , Matthew H. Harper
发明人： Hamed Eshraghian , Werner Niebel , Matthew H. Harper
IPC分类号： G06F1/12
CPC分类号： H04J3/0685 , H04J3/0688 , H04J3/0697
摘要： The present invention relates to a synchronized timestamp mechanism in a packet processing system. This synchronized timestamp mechanism provides a globally synchronized counter value so counters located on separate packet processing cards can be synchronized. The synchronizing of these packet processing cards provides tracking of how long it takes for packets to be processed, provides the ability to generate packet headers that include sequence numbers for robust header compression, and allows the use of encryption protocols without a time reference signal. The synchronization is provided by sending the cards with counter value information and this information can be used to update the card's internal counter value information so that the card is synchronized with other cards.
摘要翻译：本发明涉及分组处理系统中的同步时间戳机制。该同步时间戳机制提供全局同步的计数器值，因此可以同步位于单独的数据包处理卡上的计数器。这些分组处理卡的同步提供对要处理分组所需的时间的跟踪，提供生成包含用于鲁棒报头压缩的序列号的分组报头的能力，并且允许使用加密协议而没有时间参考信号。通过发送具有计数器值信息的卡来提供同步，并且该信息可以用于更新卡的内部计数器值信息，使得卡与其他卡同步。

4. 发明申请

US20080294926A1 Globally synchronized timestamp value counter 有权
标题翻译：全局同步时间戳值计数器
公开(公告)号：US20080294926A1
公开(公告)日：2008-11-27
申请号：US11804821
申请日：2007-05-21
申请人： Hamed Eshraghian , Werner Niebel , Matthew H. Harper
发明人： Hamed Eshraghian , Werner Niebel , Matthew H. Harper
IPC分类号： G06F1/00
CPC分类号： H04J3/0685 , H04J3/0688 , H04J3/0697
摘要： The present invention relates to a synchronized timestamp mechanism in a packet processing system. This synchronized timestamp mechanism provides a globally synchronized counter value so counters located on separate packet processing cards can be synchronized. The synchronizing of these packet processing cards provides tracking of how long it takes for packets to be processed, provides the ability to generate packet headers that include sequence numbers for robust header compression, and allows the use of encryption protocols without a time reference signal. The synchronization is provided by sending the cards with counter value information and this information can be used to update the card's internal counter value information so that the card is synchronized with other cards.
摘要翻译：本发明涉及分组处理系统中的同步时间戳机制。该同步时间戳机制提供全局同步的计数器值，因此可以同步位于单独的数据包处理卡上的计数器。这些分组处理卡的同步提供对要处理分组所需的时间的跟踪，提供生成包含用于鲁棒报头压缩的序列号的分组报头的能力，并且允许使用加密协议而没有时间参考信号。通过发送具有计数器值信息的卡来提供同步，并且该信息可以用于更新卡的内部计数器值信息，使得卡与其他卡同步。

5. 发明申请

US20050033891A1 System and method for communication over a bus 审中-公开
标题翻译：通过总线进行通信的系统和方法
公开(公告)号：US20050033891A1
公开(公告)日：2005-02-10
申请号：US10859783
申请日：2004-06-03
申请人： Hamed Eshraghian
发明人： Hamed Eshraghian
IPC分类号： G06F13/42 , H04L12/56
CPC分类号： G06F13/4273
摘要： Systems and methods for communicating data over a communication bus are disclosed. In some aspects, the data is digital information communicated over a multiple-line bus connecting two or more electronic devices such as integrated circuits. The disclosure presents useful formats for arranging data into data cells communicated over the bus, and include some exemplary features as shared clock signals, Ready bit information, and vertical parity checking.
摘要翻译：公开了通过通信总线传送数据的系统和方法。在一些方面，数据是通过连接两个或多个电子设备（诸如集成电路）的多线总线传送的数字信息。本公开提供了用于将数据排列到通过总线传送的数据单元中的有用格式，并且包括一些示例性特征作为共享时钟信号，就绪位信息和垂直奇偶校验。

6. 发明申请

US20120008621A1 COMMUNICATING IN VOICE AND DATA COMMUNICATIONS SYSTEMS 有权
标题翻译：通信语音和数据通信系统
公开(公告)号：US20120008621A1
公开(公告)日：2012-01-12
申请号：US13235993
申请日：2011-09-19
申请人： Parvez KHAN , Hamed Eshraghian
发明人： Parvez KHAN , Hamed Eshraghian
IPC分类号： H04L12/66
CPC分类号： H04M7/1255 , H04L12/6402 , H04L49/3081 , H04L2012/5665 , H04M2207/18 , H04M2207/185 , H04M2207/187 , H04Q3/0045 , H04Q11/04 , H04Q11/0478 , H04Q2213/13003 , H04Q2213/13034 , H04Q2213/13107 , H04Q2213/13178 , H04Q2213/13204 , H04Q2213/1329 , H04Q2213/13292 , H04Q2213/13296 , H04Q2213/13389 , H04Q2213/13399
摘要： A data and voice communication system includes communication between a line card and an accelerator card. Voice, data, and control traffic is received from the line card and is transmitted to the accelerator card via a physical link having separate voice, data, and control logical channels. The separate voice, data, and control logical channels are represented by labeled data packets.
摘要翻译：数据和语音通信系统包括线卡和加速卡之间的通信。从线路卡接收语音，数据和控制业务，并通过具有独立语音，数据和控制逻辑信道的物理链路将其发送到加速卡。单独的语音，数据和控制逻辑信道由标记的数据分组表示。

7. 发明授权

US08023507B2 Card to card communications in voice and data communications systems 有权
标题翻译：语音和数据通信系统中的卡到卡通信
公开(公告)号：US08023507B2
公开(公告)日：2011-09-20
申请号：US12482910
申请日：2009-06-11
申请人： Parvez Khan , Hamed Eshraghian
发明人： Parvez Khan , Hamed Eshraghian
IPC分类号： H04L12/28 , G06F13/36
CPC分类号： H04M7/1255 , H04L12/6402 , H04L49/3081 , H04L2012/5665 , H04M2207/18 , H04M2207/185 , H04M2207/187 , H04Q3/0045 , H04Q11/04 , H04Q11/0478 , H04Q2213/13003 , H04Q2213/13034 , H04Q2213/13107 , H04Q2213/13178 , H04Q2213/13204 , H04Q2213/1329 , H04Q2213/13292 , H04Q2213/13296 , H04Q2213/13389 , H04Q2213/13399
摘要： A data and voice communication system includes communication between a line card and an accelerator card. Voice, data, and control traffic is received from the line card and is transmitted to the accelerator card via a physical link having separate voice, data, and control logical channels. The separate voice, data, and control logical channels are represented by labeled data packets.
摘要翻译：数据和语音通信系统包括线卡和加速卡之间的通信。从线路卡接收语音，数据和控制业务，并通过具有独立语音，数据和控制逻辑信道的物理链路将其发送到加速卡。单独的语音，数据和控制逻辑信道由标记的数据分组表示。

8. 发明授权

US07903685B2 System and method for reformatting data 有权
标题翻译：重新格式化数据的系统和方法
公开(公告)号：US07903685B2
公开(公告)日：2011-03-08
申请号：US10860365
申请日：2004-06-03
申请人： Hamed Eshraghian
发明人： Hamed Eshraghian
IPC分类号： H04J3/16
CPC分类号： H04L12/5601 , H04L2012/5652
摘要： A converter for converting serial (e.g. TDM) data streams into parallel (e.g. cell) data is presented. Conversion from cell to TDM format is also disclosed. Methods for converting between serial and parallel data formats are provided. In some applications, communication data streams of digital data may be captured, processed, and stored in one or more of the serial and cell data formats.
摘要翻译：呈现用于将串行（例如TDM）数据流转换成并行（例如，单元）数据的转换器。还公开了从小区到TDM格式的转换。提供了串行和并行数据格式转换的方法。在一些应用中，数字数据的通信数据流可以被捕获，处理和存储在一个或多个串行和单元数据格式中。

9. 发明授权

US08599846B2 Communicating in voice and data communications systems 有权
标题翻译：在语音和数据通信系统中进行通信
公开(公告)号：US08599846B2
公开(公告)日：2013-12-03
申请号：US13235993
申请日：2011-09-19
申请人： Parvez Khan , Hamed Eshraghian
发明人： Parvez Khan , Hamed Eshraghian
IPC分类号： H04L12/28
CPC分类号： H04M7/1255 , H04L12/6402 , H04L49/3081 , H04L2012/5665 , H04M2207/18 , H04M2207/185 , H04M2207/187 , H04Q3/0045 , H04Q11/04 , H04Q11/0478 , H04Q2213/13003 , H04Q2213/13034 , H04Q2213/13107 , H04Q2213/13178 , H04Q2213/13204 , H04Q2213/1329 , H04Q2213/13292 , H04Q2213/13296 , H04Q2213/13389 , H04Q2213/13399
摘要： A data and voice communication system includes communication between a line card and an accelerator card. Voice, data, and control traffic is received from the line card and is transmitted to the accelerator card via a physical link having separate voice, data, and control logical channels. The separate voice, data, and control logical channels are represented by labeled data packets.
摘要翻译：数据和语音通信系统包括线卡和加速卡之间的通信。从线路卡接收语音，数据和控制业务，并通过具有独立语音，数据和控制逻辑信道的物理链路将其发送到加速卡。单独的语音，数据和控制逻辑信道由标记的数据分组表示。

10. 发明申请

US20050030982A1 System and method for reformatting data 有权
标题翻译：重新格式化数据的系统和方法
公开(公告)号：US20050030982A1
公开(公告)日：2005-02-10
申请号：US10860365
申请日：2004-06-03
申请人： Hamed Eshraghian
发明人： Hamed Eshraghian
IPC分类号： H04J3/16 , H04L12/56
CPC分类号： H04L12/5601 , H04L2012/5652
摘要： A converter for converting serial (e.g. TDM) data streams into parallel (e.g. cell) data is presented. Conversion from cell to TDM format is also disclosed. Methods for converting between serial and parallel data formats are provided. In some applications, communication data streams of digital data may be captured, processed, and stored in one or more of the serial and cell data formats.
摘要翻译：呈现用于将串行（例如TDM）数据流转换成并行（例如，单元）数据的转换器。还公开了从小区到TDM格式的转换。提供了串行和并行数据格式转换的方法。在一些应用中，数字数据的通信数据流可以被捕获，处理和存储在一个或多个串行和单元数据格式中。

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