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1. 发明申请

US20080246533A1 METHODS AND CIRCUITS TO REDUCE THRESHOLD VOLTAGE TOLERANCE AND SKEW IN MULTI-THRESHOLD VOLTAGE APPLICATIONS 审中-公开
标题翻译：降低多电压电压应用中阈值电压公差和电流的方法和电路
公开(公告)号：US20080246533A1
公开(公告)日：2008-10-09
申请号：US12138514
申请日：2008-06-13
申请人： Corey Kenneth Barrows , Douglas W. Kemerer , Stephen Gerard Shuma , Douglas Willard Stout , Oscar Conrad Strohacker , Mark Steven Styduhar , Paul Steven Zuchowski
发明人： Corey Kenneth Barrows , Douglas W. Kemerer , Stephen Gerard Shuma , Douglas Willard Stout , Oscar Conrad Strohacker , Mark Steven Styduhar , Paul Steven Zuchowski
IPC分类号： H03K3/01
CPC分类号： G06F17/5063 , H01L27/088 , H01L27/092
摘要： A circuit and a method for adjusting the performance of an integrated circuit, the circuit includes: first and second sets of FETs having respective first and second threshold voltages, the first threshold voltage different from the second threshold voltage; a first monitor circuit containing at least one FET of the first set of FETs and a second monitor circuit containing at least one FET of the second set of FETs; a compare circuit configured to generate a compare signal based on a performance measurement of the first monitor circuit and a performance measurement of the second monitor circuit; and a control unit configured to generate a control signal to a voltage regulator based on the compare signal, the voltage regulator configured to supply a bias voltage to wells of FETs of the second set of FETs, the value of the bias voltage based on the control signal.
摘要翻译：一种用于调整集成电路性能的电路和方法，所述电路包括：具有相应的第一和第二阈值电压的第一和第二组FET，所述第一阈值电压不同于所述第二阈值电压; 包含第一组FET的至少一个FET的第一监视器电路和包含第二组FET的至少一个FET的第二监视电路; 比较电路，被配置为基于所述第一监视电路的性能测量和所述第二监视电路的性能测量来产生比较信号; 以及控制单元，被配置为基于所述比较信号向电压调节器产生控制信号，所述电压调节器被配置为向所述第二组FET的FET的阱提供偏置电压，所述偏置电压的值基于所述控制信号。

2. 发明授权

US07459958B2 Circuits to reduce threshold voltage tolerance and skew in multi-threshold voltage applications 有权
标题翻译：降低多阈值电压应用中阈值电压容限和偏斜的电路
公开(公告)号：US07459958B2
公开(公告)日：2008-12-02
申请号：US11424961
申请日：2006-06-19
申请人： Corey Kenneth Barrows , Douglas W. Kemerer , Stephen Gerard Shuma , Douglas Willard Stout , Oscar Conrad Strohacker , Mark Steven Styduhar , Paul Steven Zuchowski
发明人： Corey Kenneth Barrows , Douglas W. Kemerer , Stephen Gerard Shuma , Douglas Willard Stout , Oscar Conrad Strohacker , Mark Steven Styduhar , Paul Steven Zuchowski
IPC分类号： H03K3/01
CPC分类号： G06F17/5063 , H01L27/088 , H01L27/092
摘要： A circuit and a method for adjusting the performance of an integrated circuit, the circuit includes: first and second sets of FETs having respective first and second threshold voltages, the first threshold voltage different from the second threshold voltage; a first monitor circuit containing at least one FET of the first set of FETs and a second monitor circuit containing at least one FET of the second set of FETs; a compare circuit adapted to generate a compare signal based on a performance measurement of the first monitor circuit and a performance measurement of the second monitor circuit; and a control unit adapted to generate a control signal to a voltage regulator based on the compare signal, the voltage regulator adapted to supply a bias voltage to wells of FETs of the second set of FETs, the value of the bias voltage based on the control signal.
摘要翻译：一种用于调整集成电路性能的电路和方法，所述电路包括：具有相应的第一和第二阈值电压的第一和第二组FET，所述第一阈值电压不同于所述第二阈值电压; 包含第一组FET的至少一个FET的第一监视器电路和包含第二组FET的至少一个FET的第二监视电路; 比较电路，其适于基于第一监视电路的性能测量和第二监视电路的性能测量来产生比较信号; 以及控制单元，其适于基于所述比较信号向所述电压调节器产生控制信号，所述电压调节器适于向所述第二组FET的FET的阱提供偏置电压，所述偏置电压的值基于所述控制信号。

3. 发明授权

US07696811B2 Methods and circuits to reduce threshold voltage tolerance and skew in multi-threshold voltage applications 失效
标题翻译：降低多阈值电压应用中阈值电压容限和偏斜的方法和电路
公开(公告)号：US07696811B2
公开(公告)日：2010-04-13
申请号：US11941342
申请日：2007-11-16
申请人： Corey Kenneth Barrows , Douglas W. Kemerer , Stephen Gerard Shuma , Douglas Willard Stout , Oscar Conrad Strohacker , Mark Steven Styduhar , Paul Steven Zuchowski
发明人： Corey Kenneth Barrows , Douglas W. Kemerer , Stephen Gerard Shuma , Douglas Willard Stout , Oscar Conrad Strohacker , Mark Steven Styduhar , Paul Steven Zuchowski
IPC分类号： H03K3/01
CPC分类号： G06F17/5063 , H01L27/088 , H01L27/092
摘要： A design structure. The design structure includes: a first set of FETs having a designed first Vt and a second set of FETs having a designed second Vt, the first Vt different from the second Vt; a first monitor circuit containing at least one FET of the first set of FETs and a second monitor circuit containing at least one FET of the second set of FETs; a compare circuit configured to generate a compare signal based on a performance measurement of the first monitor circuit and of the second monitor circuit; a control unit responsive to the compare signal and configured to generate a control signal regulator based on the compare signal; and an adjustable voltage regulator responsive to the control signal and configured to voltage bias wells of FETs of the second set of FETs, the value of the voltage bias applied based on the control signal.
摘要翻译：设计结构。该设计结构包括：具有设计的第一Vt的第一组FET和具有设计的第二Vt的第二组FET，第一Vt与第二Vt不同; 包含第一组FET的至少一个FET的第一监视器电路和包含第二组FET的至少一个FET的第二监视电路; 比较电路，被配置为基于所述第一监视电路和所述第二监视电路的性能测量来产生比较信号; 控制单元，响应于比较信号并被配置为基于比较信号产生控制信号调节器; 以及响应于所述控制信号并被配置为所述第二组FET的FET的电压偏置阱的可调电压调节器，所述电压偏置值基于所述控制信号施加。

4. 发明申请

US20080265983A1 METHODS TO REDUCE THRESHOLD VOLTAGE TOLERANCE AND SKEW IN MULTI-THRESHOLD VOLTAGE APPLICATIONS 失效
标题翻译：降低多电压电压应用中阈值电压公差的方法
公开(公告)号：US20080265983A1
公开(公告)日：2008-10-30
申请号：US12169705
申请日：2008-07-09
申请人： Corey Kenneth Barrows , Douglas W. Kemerer , Stephen Gerard Shuma , Douglas Willard Stout , Oscar Conrad Strohacker , Mark Steven Styduhar , Paul Steven Zuchowski
发明人： Corey Kenneth Barrows , Douglas W. Kemerer , Stephen Gerard Shuma , Douglas Willard Stout , Oscar Conrad Strohacker , Mark Steven Styduhar , Paul Steven Zuchowski
IPC分类号： G05F1/44
CPC分类号： G06F17/5063 , H01L27/088 , H01L27/092
摘要： A circuit and a method for adjusting the performance of an integrated circuit, the method includes: comprising: (a) measuring the performance of a first monitor circuit having at least one field effect transistor (FET) of a first set of FETs, each FET of the first set of FETs having a designed first threshold voltage; (b) measuring the performance of a second monitor circuit having at least one field effect transistor (FET) of a second set of FETs, each FET of the second set of FETs having a designed second threshold voltage, the second threshold voltage different from the first threshold voltage; and (c) applying a bias voltage to wells of the FETs of the second set of FETs based on comparing a measured performance of the first and second monitor circuits to specified performances of the first and second monitor circuits.
摘要翻译：一种用于调整集成电路性能的电路和方法，所述方法包括：（a）测量具有第一组FET的至少一个场效应晶体管（FET）的第一监视电路的性能，每个FET 的第一组FET具有设计的第一阈值电压; （b）测量具有第二组FET的至少一个场效应晶体管（FET）的第二监视器电路的性能，所述第二组FET的每个FET具有设计的第二阈值电压，所述第二阈值电压不同于第一阈值电压; 并且（c）基于将第一和第二监视器电路的测量性能与第一和第二监视器电路的指定性能进行比较，向第二组FET的FET施加偏置电压。

5. 发明申请

US20080122524A1 Methods And Circuits To Reduce Threshold Voltage Tolerance and Skew In Multi-Threshold Voltage Applications 有权
标题翻译：降低多阈值电压应用中阈值电压容差和偏斜的方法和电路
公开(公告)号：US20080122524A1
公开(公告)日：2008-05-29
申请号：US11424961
申请日：2006-06-19
申请人： Corey Kenneth Barrows , Douglas W. Kemerer , Stephen Gerard Shuma , Douglas Willard Stout , Oscar Conrad Strohacker , Mark Steven Styduhar , Paul Steven Zuchowski
发明人： Corey Kenneth Barrows , Douglas W. Kemerer , Stephen Gerard Shuma , Douglas Willard Stout , Oscar Conrad Strohacker , Mark Steven Styduhar , Paul Steven Zuchowski
IPC分类号： G05F1/44 , G05F1/10
CPC分类号： G06F17/5063 , H01L27/088 , H01L27/092
摘要： A circuit and a method for adjusting the performance of an integrated circuit, the circuit includes: first and second sets of FETs having respective first and second threshold voltages, the first threshold voltage different from the second threshold voltage; a first monitor circuit containing at least one FET of the first set of FETs and a second monitor circuit containing at least one FET of the second set of FETs; a compare circuit adapted to generate a compare signal based on a performance measurement of the first monitor circuit and a performance measurement of the second monitor circuit; and a control unit adapted to generate a control signal to a voltage regulator based on the compare signal, the voltage regulator adapted to supply a bias voltage to wells of FETs of the second set of FETs, the value of the bias voltage based on the control signal.
摘要翻译：一种用于调整集成电路性能的电路和方法，所述电路包括：具有相应的第一和第二阈值电压的第一和第二组FET，所述第一阈值电压不同于所述第二阈值电压; 包含第一组FET的至少一个FET的第一监视器电路和包含第二组FET的至少一个FET的第二监视电路; 比较电路，其适于基于第一监视电路的性能测量和第二监视电路的性能测量来产生比较信号; 以及控制单元，其适于基于所述比较信号向所述电压调节器产生控制信号，所述电压调节器适于向所述第二组FET的FET的阱提供偏置电压，所述偏置电压的值基于所述控制信号。

6. 发明授权

US07671666B2 Methods to reduce threshold voltage tolerance and skew in multi-threshold voltage applications 失效
标题翻译：降低多阈值电压应用中阈值电压容限和偏斜的方法
公开(公告)号：US07671666B2
公开(公告)日：2010-03-02
申请号：US12169705
申请日：2008-07-09
申请人： Corey Kenneth Barrows , Douglas W. Kemerer , Stephen Gerard Shuma , Douglas Willard Stout , Oscar Conrad Strohacker , Mark Steven Styduhar , Paul Steven Zuchowski
发明人： Corey Kenneth Barrows , Douglas W. Kemerer , Stephen Gerard Shuma , Douglas Willard Stout , Oscar Conrad Strohacker , Mark Steven Styduhar , Paul Steven Zuchowski
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G06F17/5063 , H01L27/088 , H01L27/092
摘要： A circuit and a method for adjusting the performance of an integrated circuit, the method includes: comprising: (a) measuring the performance of a first monitor circuit having at least one field effect transistor (FET) of a first set of FETs, each FET of the first set of FETs having a designed first threshold voltage; (b) measuring the performance of a second monitor circuit having at least one field effect transistor (FET) of a second set of FETs, each FET of the second set of FETs having a designed second threshold voltage, the second threshold voltage different from the first threshold voltage; and (c) applying a bias voltage to wells of the FETs of the second set of FETs based on comparing a measured performance of the first and second monitor circuits to specified performances of the first and second monitor circuits.
摘要翻译：一种用于调整集成电路性能的电路和方法，所述方法包括：（a）测量具有第一组FET的至少一个场效应晶体管（FET）的第一监视电路的性能，每个FET 的第一组FET具有设计的第一阈值电压; （b）测量具有第二组FET的至少一个场效应晶体管（FET）的第二监视器电路的性能，所述第二组FET的每个FET具有设计的第二阈值电压，所述第二阈值电压不同于第一阈值电压; 并且（c）基于将第一和第二监视器电路的测量性能与第一和第二监视器电路的指定性能进行比较，向第二组FET的FET施加偏置电压。

7. 发明授权

US06731154B2 Global voltage buffer for voltage islands 有权
标题翻译：电压岛的全局电压缓冲器
公开(公告)号：US06731154B2
公开(公告)日：2004-05-04
申请号：US10063504
申请日：2002-05-01
申请人： Thomas Richard Bednar , Scott Whitney Gould , David E. Lackey , Douglas Willard Stout , Paul Steven Zuchowski
发明人： Thomas Richard Bednar , Scott Whitney Gould , David E. Lackey , Douglas Willard Stout , Paul Steven Zuchowski
IPC分类号： H03K1706
CPC分类号： H03K19/0016
摘要： A method and apparatus for buffering a signal in a voltage island that is in standby or sleep mode. The apparatus uses a buffer(s) that are powered from a global power supply voltage that is always powered, and such buffer(s) are placed within the sleeping island itself. The sleeping island can be at the same or different voltage from the global voltage.
摘要翻译：一种用于缓冲处于待机或休眠模式的电压岛中的信号的方法和装置。该设备使用由始终供电的全局电源电压供电的缓冲器，并且这样的缓冲器被放置在睡眠岛本身内。睡眠岛可以处于与全局电压相同或不同的电压。

8. 发明授权

US06993692B2 Method, system and apparatus for aggregating failures across multiple memories and applying a common defect repair solution to all of the multiple memories 有权
标题翻译：用于聚合多个存储器上的故障的方法，系统和装置，并将共同的缺陷修复解决方案应用于所有多个存储器
公开(公告)号：US06993692B2
公开(公告)日：2006-01-31
申请号：US10604195
申请日：2003-06-30
申请人： Michael R. Ouellette , Gustavo Enrique Tellez , Paul Steven Zuchowski
发明人： Michael R. Ouellette , Gustavo Enrique Tellez , Paul Steven Zuchowski
IPC分类号： G11C29/00 , G06F11/00
CPC分类号： G11C29/4401 , G11C29/44 , G11C29/789 , G11C29/802 , G11C29/806 , G11C2029/0401
摘要： An integrated circuit includes a plurality of separate memory arrays each having a respective one of a plurality of inputs and a respective one of a plurality of outputs. Each output provides an output value indicative of whether a storage location associated with an applied address is passing or failing. The integrated circuit further includes a shared built-in self-test (BIST) and repair system coupled to all of the plurality of inputs and all of the plurality of outputs. The shared BIST and repair system applies addresses and data to the plurality of inputs to test the plurality of memory arrays for failing storage locations. In response to detection of a failing storage location in any of the plurality of memory arrays, the shared BIST and repair system applies a common address remapping to all of the plurality of memory arrays to remap, in each memory array, the address associated with the failing storage location to a different storage location
摘要翻译：集成电路包括多个单独的存储器阵列，每个存储器阵列具有多个输入中的相应一个和多个输出中的相应一个。每个输出提供指示与应用地址相关联的存储位置是否通过或失败的输出值。集成电路还包括耦合到所有多个输入和所有多个输出的共享内置自检（BIST）和修复系统。共享的BIST和修复系统将地址和数据应用于多个输入以测试多个存储器阵列以用于故障存储位置。响应于检测多个存储器阵列中的任一个中的故障存储位置，共享BIST和修复系统将公共地址重新映射应用于所有多个存储器阵列，以在每个存储器阵列中重新映射与该存储器阵列相关联的地址将存储位置的故障存储到不同的存储位置

9. 发明授权

US06651230B2 Method for reducing design effect of wearout mechanisms on signal skew in integrated circuit design 失效
标题翻译：降低集成电路设计中信号偏移的设计效应的方法
公开(公告)号：US06651230B2
公开(公告)日：2003-11-18
申请号：US09683276
申请日：2001-12-07
申请人： John Maxwell Cohn , Jose Luis Pontes Correia Neves , Paul Steven Zuchowski
发明人： John Maxwell Cohn , Jose Luis Pontes Correia Neves , Paul Steven Zuchowski
IPC分类号： G06F1750
CPC分类号： G06F17/505 , G06F1/10
摘要： A method for reducing the effect of signal skew degradation in the design of an integrated circuit is provided. First, a circuit design library is created describing library cells as a function of one or more environmental variable, wherein the one or more environmental variable includes a skew degradation variable indicating skew degradation of a signal as a function of a total number of signal switches of the signal. Then, the integrated circuit design is modeled utilizing the circuit design library to determine a first skew degradation for each of the first and second signals at a first predetermined number of signal switches, and a second skew degradation for each of the first and second signals for a second predetermined number of signal switches, and further to determine a first relative skew degradation for a first predetermined number of signal switches and a second relative skew degradation for a second predetermined number of signal switches, wherein a relative skew degradation is equal to the difference of the skew degradation of the first signal and the skew degradation of the second signal for a given number of signal switches. Next, a skew shift equal to the difference between the first relative skew degradation and the second relative skew degradation is calculated. Finally, the integrated circuit design is modified such that a skew degradation of the first signal at the first predetermined number of signal switches is determined to be equal to the first skew degradation of the first signal minus half of the skew shift.
摘要翻译：提供了一种降低集成电路设计中的信号偏差劣化的方法。首先，创建描述作为一个或多个环境变量的函数的库单元的电路设计库，其中所述一个或多个环境变量包括歪斜劣化变量，其指示作为信号开关总数的函数的信号的歪斜退化信号。然后，使用电路设计库对集成电路设计进行建模，以在第一预定数量的信号开关处确定第一和第二信号中的每一个的第一偏斜劣化，以及用于第一和第二信号中的每一个的第二偏斜劣化第二预定数量的信号开关，并且还用于确定第一预定数量的信号开关的第一相对偏斜劣化和第二预定数量的信号开关的第二相对偏斜劣化，其中相对偏斜劣化等于差对于给定数量的信号开关，第一信号的偏斜劣化和第二信号的偏斜劣化。接下来，计算等于第一相对偏斜劣化和第二相对偏斜劣化之间的差的偏移偏移。最后，对集成电路设计进行修改，使得第一预定数量的信号开关处的第一信号的偏斜劣化被确定为等于第一信号的第一偏斜劣化减去偏移偏移的一半。

10. 发明授权

US06185722B2 Three dimensional track-based parasitic extraction 失效
标题翻译：基于三维轨道的寄生提取
公开(公告)号：US06185722B2
公开(公告)日：2001-02-06
申请号：US09037469
申请日：1998-03-10
申请人： Laura Rohwedder Darden , James John Engel , Peter Anton Habitz , William John Livingstone , Daniel Joseph Mainiero , Jeannie Harrigan Panner , Michael Timothy Trick , Paul Steven Zuchowski
发明人： Laura Rohwedder Darden , James John Engel , Peter Anton Habitz , William John Livingstone , Daniel Joseph Mainiero , Jeannie Harrigan Panner , Michael Timothy Trick , Paul Steven Zuchowski
IPC分类号： G06F1750
CPC分类号： G06F17/5036 , G06F17/5018 , G06F2217/36
摘要： A computerized tool or method that calculates the capacitance and resistance of each global wire on the chip, one wire at a time. The invention steps along a track containing a wire segment, grid point by grid point, calculating the resistance and capacitance at that point. At each grid point it searches the neighboring tracks within the surrounding cube for adjacent elements that could cause capacitive effects or affect the resistance of the wire. The method delivers capacitance and resistance values for each process condition for a grid unit length of wire, given the wire type and 3 dimensional environment of the wire segment. The capacitance and resistance at a grid point along the wire are generally determined by one table lookup for wire types based on the surrounding environment. These values are added along wire segments to deliver accurate 3 dimensional capacitances and resistances. The invention can also provide for wires and spaces of various types and widths not provided for in the tables and for calculation of net to net coupling capacitances.
摘要翻译：一种计算机工具或方法，用于计算芯片上每根全局线的电容和电阻，一次一根线。本发明沿着包含线段的轨道，通过网格点的网格点，计算该点处的电阻和电容。在每个网格点，它会搜索相邻元素周围的相邻轨道，以产生电容效应或影响线的电阻。鉴于线段的线型和三维环境，该方法为网格单元长度的线的每个工艺条件提供电容和电阻值。沿线的网格点的电容和电阻通常由基于周围环境的电线类型的一个表查找来确定。这些值沿线段添加以提供精确的3维电容和电阻。本发明还可以提供在表中未提供的各种类型和宽度的电线和空间以及用于计算网络与网络耦合电容的电线和空间。

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