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1. 发明授权

US06121101A Process for fabricating bipolar and BiCMOS devices 失效
标题翻译：制造双极和BiCMOS器件的工艺
公开(公告)号：US06121101A
公开(公告)日：2000-09-19
申请号：US42388
申请日：1998-03-12
申请人： Clifford Alan King , Kwok K. Ng
发明人： Clifford Alan King , Kwok K. Ng
IPC分类号： H01L21/331 , H01L21/8222 , H01L21/8248 , H01L21/8249 , H01L27/06 , H01L29/732
CPC分类号： H01L21/8249
摘要： A process for device fabrication in which amorphous silicon is deposited into a narrow gap is disclosed. The gap is an opening between two layers of material. The gap results when a window is formed in one of the two layers and a portion of a third layer at the base of the window is removed. In the formation of a bipolar device, a layer of oxide is formed on a silicon substrate and a layer of silicon is formed on the oxide layer which serves as the extrinsic base for the device. In the bipolar device, a window is formed in the polysilicon and the oxide layer at the base of the window is then removed. In the bipolar device, the silicon substrate underlies the gap and the extrinsic base silicon overlies the gap. When the oxide is removed from the base of the window, a portion of the oxide layer underlying the extrinsic base silicon is removed as well, thereby forming a gap between the extrinsic base silicon and the underlying silicon substrate. In the process of the present invention, the resulting gap has a proximate end which is the opening of the gap into a window and a distal end which is the interface between the gap and the remaining oxide. The width of the gap is less than about 20 nm. The gap is then subjected to conditions that cause the gap to have a first height at its proximate end which is greater than its height at its distal end. The tapered gap is then filled with polysilicon. Because of its tapered configuration, the polysilicon uniformly fills the gap, without significant voids therein.
摘要翻译：公开了一种其中非晶硅沉积到窄间隙中的器件制造工艺。间隙是两层材料之间的开口。当窗口形成在两个层中的一个层中并且在窗口的基部处的第三层的一部分被去除时，产生间隙。在双极器件的形成中，在硅衬底上形成氧化物层，并且在作为器件的外在基极的氧化物层上形成硅层。在双极器件中，在多晶硅中形成窗口，然后去除窗口底部的氧化物层。在双极器件中，硅衬底位于间隙之下，而外部基极硅覆盖在间隙上。当从窗口的底部去除氧化物时，除去外部基底硅下面的一部分氧化物层，从而在外部基极硅和下面的硅衬底之间形成间隙。在本发明的方法中，所得到的间隙具有近端，该近端是间隙进入窗口的开口，而远端是间隙和剩余氧化物之间的界面。间隙的宽度小于约20nm。然后使间隙受到使其间隙在其近端具有大于其远端高度的第一高度的条件。然后用多晶硅填充锥形间隙。由于其锥形构造，多晶硅均匀地填充间隙，其中没有显着的空隙。

2. 发明授权

US06509242B2 Heterojunction bipolar transistor 有权
公开(公告)号：US06509242B2
公开(公告)日：2003-01-21
申请号：US09759120
申请日：2001-01-12
申请人： Michel Ranjit Frei , Clifford Alan King , Yi Ma , Marco Mastrapasqua , Kwok K Ng
发明人： Michel Ranjit Frei , Clifford Alan King , Yi Ma , Marco Mastrapasqua , Kwok K Ng
IPC分类号： H01L21331
CPC分类号： H01L29/66242 , H01L29/7378
摘要： A heterojunction bipolar transistor includes an emitter or collector region of doped silicon, a base region including silicon-germanium, and a spacer. The emitter or collector region form a heterojunction with the base region. The spacer is positioned to electrically insulate the emitter or collector region from an external region. The spacer includes a silicon dioxide layer physically interposed between the emitter or collector region and the remainder of the spacer.

3. 发明授权

US5767561A Integrated circuit device with isolated circuit elements 失效
标题翻译：具有隔离电路元件的集成电路器件
公开(公告)号：US5767561A
公开(公告)日：1998-06-16
申请号：US853582
申请日：1997-05-09
申请人： Michel Ranjit Frei , Clifford Alan King , Kwok K. Ng , Harry Thomas Weston , Ya-Hong Xie
发明人： Michel Ranjit Frei , Clifford Alan King , Kwok K. Ng , Harry Thomas Weston , Ya-Hong Xie
IPC分类号： H01L21/822 , H01L21/762 , H01L21/764 , H01L27/04 , H01L29/00
CPC分类号： H01L21/764 , H01L21/762
摘要： A device with at least one noise-sensitive element, at least one noise-generating element, and a porous silicon barrier in the substrate is disclosed. The porous silicon barrier isolates the noise-sensitive element from the signals coupled into the substrate by the noise-generating element. A process for making this device is also disclosed.
摘要翻译：公开了一种在衬底中具有至少一个噪声敏感元件，至少一个噪声产生元件和多孔硅阻挡层的器件。多孔硅屏障将噪声敏感元件与由噪声产生元件耦合到衬底中的信号隔离。还公开了制造该器件的过程。

4. 发明授权

US5834800A Heterojunction bipolar transistor having mono crystalline SiGe intrinsic base and polycrystalline SiGe and Si extrinsic base regions 失效
标题翻译：具有单晶SiGe本征基极和多晶SiGe和Si外基极区的异质结双极晶体管
公开(公告)号：US5834800A
公开(公告)日：1998-11-10
申请号：US610026
申请日：1996-03-04
申请人： Bahram Jalali-Farahani , Clifford Alan King
发明人： Bahram Jalali-Farahani , Clifford Alan King
IPC分类号： H01L29/73 , H01L21/265 , H01L21/331 , H01L29/165 , H01L29/737 , H03K3/286 , H03K19/082 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L29/66242 , H01L29/7378
摘要： A heterojunction bipolar transistor in an integrated circuit has intrinsic and extrinsic base portions. The intrinsic base portion substantially comprises epitaxial silicon-germanium alloy. The extrinsic base portion substantially comprises polycrystalline material, and contains a distribution of ion-implanted impurities. An emitter overlies the intrinsic base portion, and a spacer at least partially overlies the emitter. The spacer overhangs the extrinsic base portion by at least a distance characteristic of lateral straggle of the ion-implanted impurities.
摘要翻译：集成电路中的异质结双极晶体管具有固有和非本征基极部分。本征基本部分基本上包括外延硅 - 锗合金。外在基部基本上包括多晶材料，并且包含离子注入杂质的分布。发射极覆盖本征基极部分，并且间隔物至少部分地覆盖发射极。间隔物通过离子注入的杂质的横向偏移的至少一个距离特性突出到外部基部。

5. 发明申请

US20120043637A1 IMAGE SENSOR COMPRISING ISOLATED GERMANIUM PHOTODETECTORS INTEGRATED WITH A SILICON SUBSTRATE AND SILICON CIRCUITRY 有权
标题翻译：包含与硅衬底和硅电路集成的隔离锗光电子的图像传感器
公开(公告)号：US20120043637A1
公开(公告)日：2012-02-23
申请号：US13116411
申请日：2011-05-26
申请人： Clifford Alan King , Conor S. Rafferty
发明人： Clifford Alan King , Conor S. Rafferty
IPC分类号： H01L31/028
CPC分类号： H01L27/14634 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L27/14632 , H01L27/14643 , H01L27/14649 , H01L31/028 , H01L2924/351
摘要： In accordance with the invention, an improved image sensor comprises an array of germanium photosensitive elements integrated with a silicon substrate and integrated with silicon readout circuits. The silicon transistors are formed first on a silicon substrate, using well known silicon wafer fabrication techniques. The germanium elements are subsequently formed overlying the silicon by epitaxial growth. The germanium elements are advantageously grown within surface openings of a dielectric cladding. Wafer fabrication techniques are applied to the elements to form isolated germanium photodiodes. Since temperatures needed for germanium processing are lower than those for silicon processing, the formation of the germanium devices need not affect the previously formed silicon devices. Insulating and metallic layers are then deposited and patterned to interconnect the silicon devices and to connect the germanium devices to the silicon circuits. The germanium elements are thus integrated to the silicon by epitaxial growth and integrated to the silicon circuitry by common metal layers.
摘要翻译：根据本发明，改进的图像传感器包括与硅衬底集成并与硅读出电路集成的锗感光元件的阵列。首先使用公知的硅晶片制造技术在硅衬底上形成硅晶体管。随后通过外延生长将锗元素覆盖在硅上。有利地，锗元素在电介质包层的表面开口内生长。将晶片制造技术应用于元件以形成分离的锗光电二极管。由于锗处理所需的温度低于硅处理所需的温度，锗器件的形成不必影响先前形成的硅器件。然后沉积和图案化绝缘和金属层以互连硅器件并将锗器件连接到硅电路。因此，锗元素通过外延生长与硅集成到一起，并通过公共金属层与硅电路集成。

6. 发明授权

US07643755B2 Optical receiver comprising a receiver photodetector integrated with an imaging array 有权
标题翻译：光接收器包括与成像阵列集成的接收器光电检测器
公开(公告)号：US07643755B2
公开(公告)日：2010-01-05
申请号：US10964266
申请日：2004-10-13
申请人： Conor S. Rafferty , Clifford Alan King
发明人： Conor S. Rafferty , Clifford Alan King
IPC分类号： H04B10/00 , H04B10/06
CPC分类号： H04B10/118
摘要： A high-speed optical communications cell is integrated at the interior of a two-dimensional imaging array. The combined receiver and imager carries out both photodetection (converting photons to electrons) and circuit functions (e.g. amplifying and integrating the signals from the photodetectors). The high-speed receiver cell comprises a photodetector and a high-speed amplification circuit, providing an electrical output which can follow a rapidly varying optical signal falling on the photodetector. The imaging array comprises an array of photodetectors and readout circuits, providing an electrical representation of the variation of light with position across the receiver surface. The presence of an imaging array surrounding the communications receiver, and in the same plane as it, allows a single optical path to be used for source acquisition and tracking as well as for data reception.
摘要翻译：高速光通信单元集成在二维成像阵列的内部。组合的接收器和成像器执行光电检测（将光子转换成电子）和电路功能（例如放大和积分来自光电检测器的信号）。高速接收器单元包括光电检测器和高速放大电路，提供可以跟随落在光电检测器上的快速变化的光信号的电输出。该成像阵列包括光电检测器和读出电路的阵列，提供了具有横跨接收器表面的位置的光的变化的电表示。存在围绕通信接收器并且与其相同的平面中的成像阵列允许将单个光路用于源获取和跟踪以及用于数据接收。

7. 发明授权

US07012314B2 Semiconductor devices with reduced active region defects and unique contacting schemes 有权
标题翻译：半导体器件具有减少的有源区缺陷和独特的接触方案
公开(公告)号：US07012314B2
公开(公告)日：2006-03-14
申请号：US10453037
申请日：2003-06-03
申请人： Jeffrey Devin Bude , Malcolm Carroll , Clifford Alan King
发明人： Jeffrey Devin Bude , Malcolm Carroll , Clifford Alan King
IPC分类号： H01L27/14 , H01L31/00 , H01L31/0232 , H01L31/0203 , H01L31/117
CPC分类号： H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L27/14649
摘要： A method of making a semiconductor device having a predetermined epitaxial region, such as an active region, with reduced defect density includes the steps of: (a) forming a dielectric cladding region on a major surface of a single crystal body of a first material; (b) forming a first opening that extends to a first depth into the cladding region; (c) forming a smaller second opening, within the first opening, that extends to a second depth greater than the first depth and that exposes an underlying portion of the major surface of the single crystal body; (d) epitaxially growing regions of a second semiconductor material in each of the openings and on the top of the cladding region; (e) controlling the dimensions of the second opening so that defects are confined to the epitaxial regions grown within the second opening and on top of the cladding region, a first predetermined region being located within the first opening and being essentially free of defects; (D planarizing the top of the device to remove all epitaxial regions that extend above the top of the cladding layer, thereby making the top of the first predetermined region grown in the second opening essentially flush with the top of the cladding region; and (g) performing additional steps to complete the fabrication of the device. Also described are unique devices, such as photodetectors and MOSFETs, fabricated by this method, as well as unique contacting configurations that enhance their performance.
摘要翻译：制造具有减小的缺陷密度的诸如有源区域的预定外延区域的半导体器件的方法包括以下步骤：（a）在第一材料的单晶体的主表面上形成介电包层区; （b）形成延伸到所述包层区域的第一深度的第一开口; （c）在所述第一开口内形成较小的第二开口，所述较小的第二开口延伸到大于所述第一深度的第二深度并且暴露所述单晶体主表面的下部; （d）在每个开口和包层区域的顶部上的第二半导体材料的外延生长区域; （e）控制第二开口的尺寸，使得缺陷被限制在在第二开口内生长并且在包层区域的顶部上的外延区域，第一预定区域位于第一开口内并且基本上没有缺陷; （D平面化器件的顶部以移除在包覆层的顶部之上延伸的所有外延区域，从而使得在第二开口中生长的第一预定区域的顶部基本上与包层区域的顶部齐平;以及（g ）执行附加步骤以完成器件的制造，还描述了通过该方法制造的独特器件，例如光电检测器和MOSFET，以及增强其性能的独特接触配置。

8. 发明申请

US20100044823A1 SEMICONDUCTOR PHOTONIC DEVICES WITH ENHANCED RESPONSIVITY AND REDUCED STRAY LIGHT 审中-公开
标题翻译：具有增强响应和降低光束的半导体光电器件
公开(公告)号：US20100044823A1
公开(公告)日：2010-02-25
申请号：US12610522
申请日：2009-11-02
申请人： Conor S. Rafferty , Clifford Alan King
发明人： Conor S. Rafferty , Clifford Alan King
IPC分类号： H01L31/10
CPC分类号： H01L27/14623 , H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L27/14685 , H01L31/02164
摘要： In accordance with the invention, a photonic device comprises a semiconductor substrate including at least one circuit component comprising a metal silicide layer and an overlying layer including at least one photoresponsive component. The metal silicide layer is disposed between the circuit component and the photoresponsive component to prevent entry into the circuit component of light that penetrates the photoresponsive component. The silicide layer advantageously reflects the light back into the photoresponsive element. In addition, the overlying layer can include one or more reflective layers to reduce entry of oblique light into the photoresponsive component. In an advantageous embodiment, the substrate comprises single-crystal silicon including one or more insulated gate field effect transistors (IGFETs), and/or capacitors, and the photoresponsive element comprises germanium and/or germanium alloy epitaxially grown from seeds on the silicon. The metal silicide layer can comprise the gate of the IGFET and/or an electrode of the capacitor.
摘要翻译：根据本发明，光子器件包括半导体衬底，其包括至少一个包括金属硅化物层的电路部件和包括至少一个光响应部件的上覆层。金属硅化物层设置在电路部件和光响应部件之间，以防止进入穿过光响应部件的光的电路部件。硅化物层有利地将光反射回光响应元件。此外，上覆层可以包括一个或多个反射层，以减少斜光进入光响应部件。在有利的实施例中，衬底包括包括一个或多个绝缘栅场效应晶体管（IGFET）和/或电容器的单晶硅，并且光响应元件包括从硅上的种子外延生长的锗和/或锗合金。金属硅化物层可以包括IGFET的栅极和/或电容器的电极。

9. 发明申请

US20090072284A1 IMAGE SENSOR COMPRISING ISOLATED GERMANIUM PHOTODETECTORS INTEGRATED WITH A SILICON SUBSTRATE AND SILICON CIRCUITRY 有权
标题翻译：包含与硅衬底和硅电路集成的隔离锗光电子的图像传感器
公开(公告)号：US20090072284A1
公开(公告)日：2009-03-19
申请号：US12271601
申请日：2008-11-14
申请人： Clifford Alan King , Conor S. Rafferty
发明人： Clifford Alan King , Conor S. Rafferty
IPC分类号： H01L31/112 , H01L31/028
CPC分类号： H01L27/14634 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L27/14632 , H01L27/14643 , H01L27/14649 , H01L31/028 , H01L2924/351
摘要： In accordance with the invention, an improved image sensor comprises an array of germanium photosensitive elements integrated with a silicon substrate and integrated with silicon readout circuits. The silicon transistors are formed first on a silicon substrate, using well known silicon wafer fabrication techniques. The germanium elements are subsequently formed overlying the silicon by epitaxial growth. The germanium elements are advantageously grown within surface openings of a dielectric cladding. Wafer fabrication techniques are applied to the elements to form isolated germanium photodiodes. Since temperatures needed for germanium processing are lower than those for silicon processing, the formation of the germanium devices need not affect the previously formed silicon devices. Insulating and metallic layers are then deposited and patterned to interconnect the silicon devices and to connect the germanium devices to the silicon circuits. The germanium elements are thus integrated to the silicon by epitaxial growth and integrated to the silicon circuitry by common metal layers.
摘要翻译：根据本发明，改进的图像传感器包括与硅衬底集成并与硅读出电路集成的锗感光元件的阵列。首先使用公知的硅晶片制造技术在硅衬底上形成硅晶体管。随后通过外延生长将锗元素覆盖在硅上。有利地，锗元素在电介质包层的表面开口内生长。将晶片制造技术应用于元件以形成分离的锗光电二极管。由于锗处理所需的温度低于硅处理所需的温度，锗器件的形成不必影响先前形成的硅器件。然后沉积和图案化绝缘和金属层以互连硅器件并将锗器件连接到硅电路。因此，锗元素通过外延生长与硅集成到一起，并通过公共金属层与硅电路集成。

10. 发明授权

US07453129B2 Image sensor comprising isolated germanium photodetectors integrated with a silicon substrate and silicon circuitry 有权
标题翻译：图像传感器包括与硅衬底和硅电路集成的孤立的锗光电探测器
公开(公告)号：US07453129B2
公开(公告)日：2008-11-18
申请号：US10964057
申请日：2004-10-13
申请人： Clifford Alan King , Conor S. Rafferty
发明人： Clifford Alan King , Conor S. Rafferty
IPC分类号： H01L27/14 , H01L29/82 , H01L29/84
CPC分类号： H01L27/14634 , H01L21/02381 , H01L21/02532 , H01L21/02639 , H01L27/14632 , H01L27/14643 , H01L27/14649 , H01L31/028 , H01L2924/351
摘要： In accordance with the invention, an improved image sensor comprises an array of germanium photosensitive elements integrated with a silicon substrate and integrated with silicon readout circuits. The silicon transistors are formed first on a silicon substrate, using well known silicon wafer fabrication techniques. The germanium elements are subsequently formed overlying the silicon by epitaxial growth. The germanium elements are advantageously grown within surface openings of a dielectric cladding. Wafer fabrication techniques are applied to the elements to form isolated germanium photodiodes. Since temperatures needed for germanium processing are lower than those for silicon processing, the formation of the germanium devices need not affect the previously formed silicon devices. Insulating and metallic layers are then deposited and patterned to interconnect the silicon devices and to connect the germanium devices to the silicon circuits. The germanium elements are thus integrated to the silicon by epitaxial growth and integrated to the silicon circuitry by common metal layers.
摘要翻译：根据本发明，改进的图像传感器包括与硅衬底集成并与硅读出电路集成的锗感光元件的阵列。首先使用公知的硅晶片制造技术在硅衬底上形成硅晶体管。随后通过外延生长将锗元素覆盖在硅上。有利地，锗元素在电介质包层的表面开口内生长。将晶片制造技术应用于元件以形成分离的锗光电二极管。由于锗处理所需的温度低于硅处理所需的温度，锗器件的形成不必影响先前形成的硅器件。然后沉积和图案化绝缘和金属层以互连硅器件并将锗器件连接到硅电路。因此，锗元素通过外延生长与硅集成到一起，并通过公共金属层与硅电路集成。

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