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1. 发明申请

US20120204190A1 Merging Result from a Parser in a Network Processor with Result from an External Coprocessor 失效
标题翻译：从具有外部协处理器结果的网络处理器中的解析器合并结果
公开(公告)号：US20120204190A1
公开(公告)日：2012-08-09
申请号：US13365778
申请日：2012-02-03
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
IPC分类号： G06F9/46
CPC分类号： G06F9/546 , G06F9/544
摘要： A mechanism is provided for merging in a network processor results from a parser and results from an external coprocessor providing processing support requested by said parser. The mechanism enqueues in a result queue both parser results needing to be merged with a coprocessor result and parser results which have no need to be merged with a coprocessor result. An additional queue is used to enqueue the addresses of the result queue where the parser results are stored. The result from the coprocessor is received in a simple response register. The coprocessor result is read by the result queue management logic from the response register and merged to the corresponding incomplete parser result read in the result queue at the address enqueued in the additional queue.
摘要翻译：提供了一种机制，用于在来自解析器的网络处理器结果和来自提供由所述解析器请求的处理支持的外部协处理器的结果中合并。结果队列中的机制排队，解析器结果需要与协处理器结果合并，并且不需要与协处理器结果合并的解析器结果。使用一个附加队列来排列存储解析器结果的结果队列的地址。协处理器的结果是在简单的响应寄存器中接收的。协处理器结果由响应寄存器的结果队列管理逻辑读取，并被合并到在附加队列中排队的地址的结果队列中读取的相应的不完整解析器结果。

2. 发明申请

US20120192190A1 Host Ethernet Adapter for Handling Both Endpoint and Network Node Communications 失效
标题翻译：用于处理端点和网络节点通信的主机以太网适配器
公开(公告)号：US20120192190A1
公开(公告)日：2012-07-26
申请号：US13011663
申请日：2011-01-21
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
IPC分类号： G06F9/46
CPC分类号： G06F15/1735
摘要： A host Ethernet adapter (HEA) and method of managing network communications is provided. The HEA includes a host interface configured for communication with a multi-core processor over a processor bus. The host interface comprises a receive processing element including a receive processor, a receive buffer and a scheduler for dispatching packets from the receive buffer to the receive processor; a send processing element including a send processor and a send buffer; and a completion queue scheduler (CQS) for dispatching completion queue elements (CQE) from the head of the completion queue (CQ) to threads of the multi-core processor in a network node mode. The method comprises operatively coupling an Ethernet adapter to a multi-core processor system via a processor bus, selectively assigning a first plurality of packets to a first queue pair for servicing in an endpoint mode, running a device driver on the multi-core processing system, the device driver controlling the servicing of the first queue pair by dispatching the first plurality of packets to only one processor core of the multi-core processor system, selectively assigning a second plurality of packets to a second queue pair for servicing in a network node mode; and the Ethernet adapter controlling the servicing of the second queue pair by dispatching the second plurality of packets to multiple processor threads.
摘要翻译：提供主机以太网适配器（HEA）和管理网络通信的方法。 HEA包括被配置为通过处理器总线与多核处理器进行通信的主机接口。所述主机接口包括接收处理元件，所述接收处理元件包括接收处理器，接收缓冲器和用于从所述接收缓冲器向所述接收处理器分发分组的调度器; 包括发送处理器和发送缓冲器的发送处理元件; 以及用于从完成队列（CQ）的头部将网络节点模式中的多核处理器的线程调度完成队列元素（CQE）的完成队列调度器（CQS）。该方法包括经由处理器总线可操作地将以太网适配器耦合到多核处理器系统，选择性地将第一多个分组分配到第一队列对以在端点模式下进行服务，在多核处理系统上运行设备驱动程序所述设备驱动程序通过将所述第一多个分组分派到所述多核处理器系统的一个处理器核心来控制所述第一队列对的服务，选择性地将第二多个分组分配给第二队列对以在网络节点中进行服务模式; 以及所述以太网适配器通过将所述第二多个分组分派到多个处理器线程来控制所述第二队列对的服务。

3. 发明授权

US07715428B2 Multicore communication processing 有权
标题翻译：多核通讯处理
公开(公告)号：US07715428B2
公开(公告)日：2010-05-11
申请号：US11669419
申请日：2007-01-31
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Herman D. Dierks, Jr. , Christoph Raisch , Jan-Bernd Themann , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Herman D. Dierks, Jr. , Christoph Raisch , Jan-Bernd Themann , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
IPC分类号： H04L12/66 , H04J3/16 , H04J3/22
CPC分类号： H04L47/50
摘要： Mechanisms for processing of communications between data processing devices are provided. With the mechanisms of the illustrative embodiments, a set of techniques that enables sustaining media speed by distributing transmit and receive-side processing over multiple processing cores is provided. In addition, these techniques also enable designing multi-threaded network interface controller (NIC) hardware that efficiently hides the latency of direct memory access (DMA) operations associated with data packet transfers over an input/output (I/O) bus. Multiple processing cores may operate concurrently using separate instances of a communication protocol stack and device drivers to process data packets for transmission with separate hardware implemented send queue managers in a network adapter processing these data packets for transmission. Multiple hardware receive packet processors in the network adapter may be used, along with a flow classification engine, to route received data packets to appropriate receive queues and processing cores for processing.
摘要翻译：提供了用于处理数据处理设备之间的通信的机制。利用说明性实施例的机制，提供了一组通过在多个处理核上分发发送和接收侧处理来维持媒体速度的技术。此外，这些技术还可以设计出多线程网络接口控制器（NIC）硬件，可有效地隐藏通过输入/输出（I / O）总线传输数据分组的直接存储器访问（DMA）操作的延迟。多个处理核心可以使用通信协议栈和设备驱动程序的单独实例同时运行，以处理用于传输的数据分组，其中单独的硬件实现了处理这些数据分组以进行传输的网络适配器中的发送队列管理器。可以使用网络适配器中的多个硬件接收分组处理器以及流分类引擎将接收到的数据分组路由到适当的接收队列和处理核心进行处理。

4. 发明授权

US07466715B2 Flexible control block format for frame description and management 失效
标题翻译：灵活的控制块格式，用于帧描述和管理
公开(公告)号：US07466715B2
公开(公告)日：2008-12-16
申请号：US11091245
申请日：2005-03-28
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Joseph F. Logan , Fabrice J. Verplanken
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Joseph F. Logan , Fabrice J. Verplanken
IPC分类号： H04L12/28
CPC分类号： H04L12/5601 , H04L49/90 , H04L2012/5642 , H04L2012/5652 , H04L2012/5658 , H04L2012/5681
摘要： A communication network used to link information handling systems together utilizes a switching network to transmit data among senders and receivers. Each individual packet of data is described and controlled by an FCB. The bandwidth associated with the storing and distribution of data is optimized by chaining the data packets in different types of queues, or operating without chaining outside a queue. When a frame is in an output queue, the third word contains an RFCBA for egress of the frame to a line port, and an MCID for ingress from an output queue to a switch port. The RFCBA and the MCID have multicast capabilities. The format does not require a third word when a frame is in an input queue.
摘要翻译：用于将信息处理系统链接在一起的通信网络利用交换网络在发送者和接收者之间传送数据。每个单独的数据包由FCB描述和控制。与存储和分发数据相关联的带宽通过将数据分组链接在不同类型的队列中进行优化，或者在不在队列外链接的情况下运行。当帧位于输出队列中时，第三个字包含用于将帧从线路端口排出的RFCBA，以及用于从输出队列进入交换机端口的MCID。 RFCBA和MCID具有多播功能。当帧在输入队列中时，格式不需要第三个字。

5. 发明授权

US09088594B2 Providing to a parser and processors in a network processor access to an external coprocessor 有权
标题翻译：向网络处理器中的解析器和处理器提供对外部协处理器的访问
公开(公告)号：US09088594B2
公开(公告)日：2015-07-21
申请号：US13365679
申请日：2012-02-03
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
IPC分类号： G06F9/30 , H04L29/06
CPC分类号： H04L69/12
摘要： A mechanism is provided for sharing a communication used by a parser (parser path) in a network adapter of a network processor for sending requests for a process to be executed by an external coprocessor. The parser path is shared by processors of the network processor (software path) to send requests to the external processor. The mechanism uses for the software path a request mailbox comprising a control address and a data field accessed by MMIO for sending two types of messages, one message type to read or write resources and one message type to trigger an external process in the coprocessor and a response mailbox for receiving response from the external coprocessor comprising a data field and a flag field. The other processors of the network poll the flag until set and get the coprocessor result in the data field.
摘要翻译：提供了一种用于共享由网络处理器的网络适配器中的解析器（解析器路径）使用的通信的机制，用于发送对要由外部协处理器执行的进程的请求。解析器路径由网络处理器（软件路径）的处理器共享，以将请求发送到外部处理器。该机制用于软件路径，包括由MMIO访问的控制地址和数据字段的请求邮箱，用于发送两种类型的消息，一种用于读取或写入资源的消息类型和一个消息类型以触发协处理器中的外部进程，用于从包括数据字段和标志字段的外部协处理器接收响应的响应邮箱。网络的其他处理器轮询该标志直到设置，并获得协处理器结果的数据字段。

6. 发明申请

US20120204002A1 Providing to a Parser and Processors in a Network Processor Access to an External Coprocessor 有权
标题翻译：提供给网络处理器中的解析器和处理器访问外部协处理器
公开(公告)号：US20120204002A1
公开(公告)日：2012-08-09
申请号：US13365679
申请日：2012-02-03
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： H04L69/12
摘要： A mechanism is provided for sharing a communication used by a parser (parser path) in a network adapter of a network processor for sending requests for a process to be executed by an external coprocessor. The parser path is shared by processors of the network processor (software path) to send requests to the external processor. The mechanism uses for the software path a request mailbox comprising a control address and a data field accessed by MMIO for sending two types of messages, one message type to read or write resources and one message type to trigger an external process in the coprocessor and a response mailbox for receiving response from the external coprocessor comprising a data field and a flag field. The other processors of the network poll the flag until set and get the coprocessor result in the data field.
摘要翻译：提供了一种用于共享由网络处理器的网络适配器中的解析器（解析器路径）使用的通信的机制，用于发送对要由外部协处理器执行的进程的请求。解析器路径由网络处理器（软件路径）的处理器共享，以将请求发送到外部处理器。该机制用于软件路径，包括由MMIO访问的控制地址和数据字段的请求邮箱，用于发送两种类型的消息，一种用于读取或写入资源的消息类型和一个消息类型以触发协处理器中的外部进程，用于从包括数据字段和标志字段的外部协处理器接收响应的响应邮箱。网络的其他处理器轮询该标志直到设置，并获得协处理器结果的数据字段。

7. 发明申请

US20110158249A1 Assignment Constraint Matrix for Assigning Work From Multiple Sources to Multiple Sinks 失效
标题翻译：分配约束矩阵用于将工作从多个来源分配到多个接收器
公开(公告)号：US20110158249A1
公开(公告)日：2011-06-30
申请号：US12650080
申请日：2009-12-30
申请人： Claude Basso , Jean L. Calvignac , Chih-Jen Chang , Hubertus Franke , Fabrice J. Verplanken , Colin B. Verrilli
发明人： Claude Basso , Jean L. Calvignac , Chih-Jen Chang , Hubertus Franke , Fabrice J. Verplanken , Colin B. Verrilli
IPC分类号： H04L12/56
CPC分类号： H04L49/9047
摘要： An assignment constraint matrix method and apparatus used in assigning work, such as data packets, from a plurality of sources, such as data queues in a network processing device, to a plurality of sinks, such as processor threads in the network processing device. The assignment constraint matrix is implemented as a plurality of qualifier matrixes adapted to operate simultaneously in parallel. Each of the plurality of qualifier matrixes is adapted to determine sources in a subset of supported sources that are qualified to provide work to a set of sinks based on assignment constraints. The determination of qualified sources may be based sink availability information that may be provided for a set of sinks on a single chip or distributed on multiple chips.
摘要翻译：一种分配约束矩阵方法和装置，用于从网络处理设备中的多个源（诸如网络处理设备中的数据队列）将诸如数据分组的工作分配给诸如网络处理设备中的处理器线程的多个接收器。分配约束矩阵被实现为适于同时并行操作的多个限定符矩阵。多个限定符矩阵中的每一个适于确定被支持的源的子集中的源，所述源被限定为基于分配约束向一组接收器提供工作。合格来源的确定可以是可以在单个芯片上提供用于一组接收器或分布在多个芯片上的接收器可用性信息。

8. 发明授权

US07929438B2 Scheduler pipeline design for hierarchical link sharing 失效
标题翻译：调度器管道设计用于分层链路共享
公开(公告)号：US07929438B2
公开(公告)日：2011-04-19
申请号：US12175479
申请日：2008-07-18
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Gordon T. Davis , Fabrice J. Verplanken
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Gordon T. Davis , Fabrice J. Verplanken
IPC分类号： H04J1/16
CPC分类号： H04L47/60 , H04L47/15 , H04L47/50 , H04L47/52 , H04L49/90
摘要： A pipeline configuration is described for use in network traffic management for the hardware scheduling of events arranged in a hierarchical linkage. The configuration reduces costs by minimizing the use of external SRAM memory devices. This results in some external memory devices being shared by different types of control blocks, such as flow queue control blocks, frame control blocks and hierarchy control blocks. Both SRAM and DRAM memory devices are used, depending on the content of the control block (Read-Modify-Write or ‘read’ only) at enqueue and dequeue, or Read-Modify-Write solely at dequeue. The scheduler utilizes time-based calendars and weighted fair queueing calendars in the egress calendar design. Control blocks that are accessed infrequently are stored in DRAM memory while those accessed frequently are stored in SRAM.
摘要翻译：描述了用于网络流量管理中的流水线配置，用于以分层链接排列的事件的硬件调度。该配置通过最小化外部SRAM存储器件的使用来降低成本。这导致一些外部存储器设备被不同类型的控制块共享，例如流队列控制块，帧控制块和层次控制块。使用SRAM和DRAM存储器件，这取决于控制块的内容（仅读取 - 修改 - 写入或仅读取）在排队和出队，或仅读出 - 修改 - 写出。调度器在出口日历设计中使用基于时间的日历和加权公平排队日历。不频繁访问的控制块存储在DRAM存储器中，而频繁访问的控制块存储在SRAM中。

9. 发明授权

US07457241B2 Structure for scheduler pipeline design for hierarchical link sharing 失效
标题翻译：用于分层链路共享的调度器流水线设计的结构
公开(公告)号：US07457241B2
公开(公告)日：2008-11-25
申请号：US10772737
申请日：2004-02-05
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Gordon T. Davis , Fabrice J. Verplanken
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Gordon T. Davis , Fabrice J. Verplanken
IPC分类号： H04J1/16
CPC分类号： H04L47/60 , H04L47/15 , H04L47/50 , H04L47/52 , H04L49/90
摘要： A pipeline configuration is described for use in network traffic management for the hardware scheduling of events arranged in a hierarchical linkage. The configuration reduces costs by minimizing the use of external SRAM memory devices. This results in some external memory devices being shared by different types of control blocks, such as flow queue control blocks, frame control blocks and hierarchy control blocks. Both SRAM and DRAM memory devices are used, depending on the content of the control block (Read-Modify-Write or ‘read’ only) at enqueue and dequeue, or Read-Modify-Write solely at dequeue. The scheduler utilizes time-based calendars and weighted fair queueing calendars in the egress calendar design. Control blocks that are accessed infrequently are stored in DRAM memory while those accessed frequently are stored in SRAM.
摘要翻译：描述了用于网络流量管理中的流水线配置，用于以分层链接排列的事件的硬件调度。该配置通过最小化外部SRAM存储器件的使用来降低成本。这导致一些外部存储器设备被不同类型的控制块共享，例如流队列控制块，帧控制块和层次控制块。使用SRAM和DRAM存储器件，这取决于控制块的内容（仅读取 - 修改 - 写入或仅读取）在排队和出队，或仅读出 - 修改 - 写出。调度器在出口日历设计中使用基于时间的日历和加权公平排队日历。不频繁访问的控制块存储在DRAM存储器中，而频繁访问的控制块存储在SRAM中。

10. 发明授权

US07406080B2 Method and structure for enqueuing data packets for processing 失效
标题翻译：排队处理数据包的方法和结构
公开(公告)号：US07406080B2
公开(公告)日：2008-07-29
申请号：US10868725
申请日：2004-06-15
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Gordon T. Davis , Fabrice J. Verplanken
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Gordon T. Davis , Fabrice J. Verplanken
IPC分类号： H04L12/56
CPC分类号： H04L49/90 , H04L49/9042 , H04L49/9073 , H04L69/22
摘要： A method and structure is provided for buffering data packets having a header and a remainder in a network processor system. The network processor system has a processor on a chip and at least one buffer on the chip. Each buffer on the chip is configured to buffer the header of the packets in a preselected order before execution in the processor, and the remainder of the packet is stored in an external buffer apart from the chip. The method comprises utilizing the header information to identify the location and extent of the remainder of the packet. The entire selected packet is stored in the external buffer when the buffer of the stored header of the given packet is full, and moving only the header of a selected packet stored in the external buffer to the buffer on the chip when the buffer on the chip has space therefor.
摘要翻译：提供了一种在网络处理器系统中缓冲具有报头和余数的数据分组的方法和结构。网络处理器系统在芯片上具有处理器和芯片上的至少一个缓冲器。芯片上的每个缓冲器被配置为在处理器中执行之前以预先选择的顺序缓冲数据包的报头，并且数据包的剩余部分存储在与芯片分离的外部缓冲器中。该方法包括利用报头信息来识别分组的其余部分的位置和范围。当给定分组的存储报头的缓冲器已满时，整个所选分组被存储在外部缓冲器中，并且当芯片上的缓冲器仅将存储在外部缓冲器中的选定分组的报头移动到芯片上的缓冲器时有空间。

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