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1. 发明授权

US07336543B2 Non-volatile memory device with page buffer having dual registers and methods using the same 失效
标题翻译：具有双缓存器的页缓冲器的非易失性存储器件和使用其的方法
公开(公告)号：US07336543B2
公开(公告)日：2008-02-26
申请号：US11358767
申请日：2006-02-21
申请人： Chung Zen Chen , Jo Yu Wang
发明人： Chung Zen Chen , Jo Yu Wang
IPC分类号： G11C7/10 , G11C16/04
CPC分类号： G11C8/10 , G11C7/1042 , G11C16/0483 , G11C16/10 , G11C16/102 , G11C16/105 , G11C16/26 , G11C2216/14
摘要： A non-volatile memory device with a page buffer having dual registers includes a memory cell array, a selector circuit and a page buffer circuit, the selector circuit being coupled to an exterior data line, the page buffer circuit including a first register and a second register being coupled between the memory cell array and the selector circuit, and the first register and second register being commonly coupled through a sense node. The first and second registers alternately write data to the memory cell array for programming. As one of the first and second registers performs programming, the other register stores data from the data line concurrently. In other words, the second register stores data from the data line when the first register is in programming, whereas the first register stores data from the data line when the second register is in programming.
摘要翻译：具有双寄存器的页缓冲器的非易失性存储器件包括存储单元阵列，选择器电路和页缓冲电路，选择器电路耦合到外部数据线，该页缓冲电路包括第一寄存器和第二寄存器寄存器耦合在存储单元阵列和选择器电路之间，并且第一寄存器和第二寄存器通常通过感测节点耦合。第一和第二寄存器交替地将数据写入存储单元阵列用于编程。作为第一和第二寄存器之一执行编程，其他寄存器同时存储来自数据线的数据。换句话说，当第一寄存器处于编程时，第二寄存器存储来自数据线的数据，而当第二寄存器处于编程时，第一寄存器存储来自数据线的数据。

2. 发明申请

US20080008008A1 METHODS FOR PROGRAMMING AND READING NAND FLASH MEMORY DEVICE AND PAGE BUFFER PERFORMING THE SAME 有权
标题翻译：编程和读取NAND闪存存储器器件和执行其的页缓冲器的方法
公开(公告)号：US20080008008A1
公开(公告)日：2008-01-10
申请号：US11481022
申请日：2006-07-06
申请人： Chung Zen Chen , Jo Yu Wang , Fu An Wu
发明人： Chung Zen Chen , Jo Yu Wang , Fu An Wu
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C16/24 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/12 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5642
摘要： Methods for programming and reading a multi-level-cell NAND flash memory device having plural memory cells are disclosed to reduce the programming time and the reading time. The program method comprises the steps of: (a) programming the zero state memory cells, the first state memory cells, the second state memory cells and the third state memory cells to a zero state, (b) programming the second state memory cells from the zero state to a second state by switching the MSBs of the second state memory cells, and (c) programming the first state memory cells from the zero state to a first state by switching the LSBs of the first state memory cells and simultaneously programming the third state memory cells from the second state to a third state by switching the LSBs of the third state memory cells. The read method comprises the steps of: (d) reading the MSBs of the zero state memory cells, the first state memory cells, the second state memory cells, and the third state memory cells by a first verify signal and a second verify signal, and (e) reading the LSBs of the zero state memory cells, the first state memory cells, the second state memory cells, and the third state memory cells by the first verify signal and a third verify signal. A page buffer is also disclosed to perform the methods for programming and reading a multi-level-cell NAND flash memory device.
摘要翻译：公开了用于编程和读取具有多个存储器单元的多电平单元NAND闪速存储器件的方法，以减少编程时间和读取时间。程序方法包括以下步骤：（a）将零状态存储单元，第一状态存储单元，第二状态存储单元和第三状态存储单元编程为零状态，（b）将第二状态存储单元从通过切换第二状态存储单元的MSB来将零状态转换到第二状态，以及（c）通过切换第一状态存储单元的LSB并将第一状态存储单元的零状态编程为零，将第一状态存储单元从零状态编程为第一状态通过切换第三状态存储单元的LSB，从第二状态到第三状态的第三状态存储单元。读取方法包括以下步骤：（d）通过第一验证信号和第二验证信号读取零状态存储器单元，第一状态存储器单元，第二状态存储器单元和第三状态存储器单元的MSB，以及（e）通过第一验证信号和第三验证信号读取零状态存储器单元，第一状态存储器单元，第二状态存储器单元和第三状态存储器单元的LSB。还公开了一种页缓冲器来执行用于编程和读取多电平单元NAND闪存器件的方法。

3. 发明授权

US07359248B2 Methods for programming and reading NAND flash memory device and page buffer performing the same 有权
标题翻译：用于编程和读取NAND闪存器件和执行相同操作的页面缓冲器的方法
公开(公告)号：US07359248B2
公开(公告)日：2008-04-15
申请号：US11481022
申请日：2006-07-06
申请人： Chung Zen Chen , Jo Yu Wang , Fu An Wu
发明人： Chung Zen Chen , Jo Yu Wang , Fu An Wu
IPC分类号： G11C11/34
CPC分类号： G11C16/24 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/12 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5642
摘要： Methods for programming and reading a multi-level-cell NAND flash memory device having plural memory cells are disclosed to reduce the programming time and the reading time. The program method comprises the steps of: (a) programming the zero state memory cells, the first state memory cells, the second state memory cells and the third state memory cells to a zero state, (b) programming the second state memory cells from the zero state to a second state by switching the MSBs of the second state memory cells, and (c) programming the first state memory cells from the zero state to a first state by switching the LSBs of the first state memory cells and simultaneously programming the third state memory cells from the second state to a third state by switching the LSBs of the third state memory cells. The read method comprises the steps of: (d) reading the MSBs of the zero state memory cells, the first state memory cells, the second state memory cells, and the third state memory cells by a first verify signal and a second verify signal, and (e) reading the LSBs of the zero state memory cells, the first state memory cells, the second state memory cells, and the third state memory cells by the first verify signal and a third verify signal. A page buffer is also disclosed to perform the methods for programming and reading a multi-level-cell NAND flash memory device.
摘要翻译：公开了用于编程和读取具有多个存储器单元的多电平单元NAND闪速存储器件的方法，以减少编程时间和读取时间。程序方法包括以下步骤：（a）将零状态存储单元，第一状态存储单元，第二状态存储单元和第三状态存储单元编程为零状态，（b）将第二状态存储单元从通过切换第二状态存储单元的MSB来将零状态转换到第二状态，以及（c）通过切换第一状态存储单元的LSB并将第一状态存储单元的零状态编程为零，将第一状态存储单元从零状态编程为第一状态通过切换第三状态存储单元的LSB，从第二状态到第三状态的第三状态存储单元。读取方法包括以下步骤：（d）通过第一验证信号和第二验证信号读取零状态存储器单元，第一状态存储器单元，第二状态存储器单元和第三状态存储器单元的MSB，以及（e）通过第一验证信号和第三验证信号读取零状态存储器单元，第一状态存储器单元，第二状态存储器单元和第三状态存储器单元的LSB。还公开了一种页缓冲器来执行用于编程和读取多电平单元NAND闪存器件的方法。

4. 发明授权

US08194491B2 Power-up circuit 有权
标题翻译：上电电路
公开(公告)号：US08194491B2
公开(公告)日：2012-06-05
申请号：US12728508
申请日：2010-03-22
申请人： Chung Zen Chen
发明人： Chung Zen Chen
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C5/143
摘要： A power-up circuit comprises an external supply voltage potential detector, a first internal supply voltage potential detector, a second internal supply voltage potential detector, and a logic circuit. The external supply voltage potential detector is configured to detect a supply voltage that is external to the memory device and to generate a first detection signal indicating whether a voltage potential of the external supply voltage reaches a first predetermined value. The first internal supply voltage potential detector is configured to detect a first internal supply voltage that is internal to the memory device and to generate a second detection signal indicating whether a voltage potential of the first internal supply voltage reaches a second predetermined value. The second internal supply voltage potential detector is configured to detect a second internal supply voltage that is internal to the memory device and to receive the first detection signal and an output voltage of the first internal supply voltage potential detector for generating a third detection signal indicating whether the voltage potentials of the external supply voltage and the first and second internal supply voltages reach the first, second, and third predetermined values respectively. The logic circuit is configured to receive the third detection signal and to generate a power-up signal.
摘要翻译：上电电路包括外部电源电压检测器，第一内部电源电压检测器，第二内部电源电压电位检测器和逻辑电路。外部电源电压检测器被配置为检测存储器件外部的电源电压并产生指示外部电源电压的电压电位是否达到第一预定值的第一检测信号。第一内部电源电压检测器被配置为检测存储器件内部的第一内部电源电压并产生指示第一内部电源电压的电压电压是否达到第二预定值的第二检测信号。第二内部电源电压检测器被配置为检测存储器件内部的第二内部电源电压并且接收第一内部电源电压检测器的第一检测信号和第一内部电源电压检测器的输出电压，以产生指示是否外部电源电压和第一和第二内部电源电压的电压电位分别达到第一，第二和第三预定值。逻辑电路被配置为接收第三检测信号并产生上电信号。

5. 发明授权

US08107315B2 Double data rate memory device having data selection circuit and data paths 有权
标题翻译：具有数据选择电路和数据路径的双数据速率存储器件
公开(公告)号：US08107315B2
公开(公告)日：2012-01-31
申请号：US12728601
申请日：2010-03-22
申请人： Chung Zen Chen
发明人： Chung Zen Chen
IPC分类号： G11C8/00
CPC分类号： G11C7/1051 , G11C7/1045 , G11C7/1048 , G11C7/106 , G11C7/1069 , G11C2207/107 , G11C2207/2272
摘要： A double data rate memory device comprises first and second sense amplifiers, a data selection circuit, and a data processing circuit. The first sense amplifier is configured to provide even data loaded on a first input and output data line, and the second sense amplifier is configured to provide odd data loaded on a second input and output data line. The data selection circuit is connected to the first and second sense amplifiers and is configured to provide output data loaded on a single data line, and the data processing circuit connected to the data selection circuit and configured to transfer the even data and the odd data in first and second data paths. The even data and the odd data are combined into the output data of the data selection circuit, and the data selection circuit selects the output data in response to a least significant bit of a column address and transfers the selected data on the single data line in response to a clock signal.
摘要翻译：双数据速率存储器件包括第一和第二读出放大器，数据选择电路和数据处理电路。第一读出放大器被配置为提供加载在第一输入和输出数据线上的均匀数据，并且第二读出放大器被配置为提供加载在第二输入和输出数据线上的奇数数据。数据选择电路连接到第一和第二读出放大器，并且被配置为提供加载在单个数据线上的输出数据，以及数据处理电路，连接到数据选择电路并被配置为将偶数数据和奇数数据传送到第一和第二数据路径。偶数据和奇数据被组合到数据选择电路的输出数据中，并且数据选择电路响应于列地址的最低有效位选择输出数据，并将所选择的数据在单个数据线上传送响应时钟信号。

6. 发明申请

US20120002497A1 Circuit and method for controlling standby leakage current in random access memory devices 有权
公开(公告)号：US20120002497A1
公开(公告)日：2012-01-05
申请号：US12801944
申请日：2010-07-02
申请人： Chung Zen Chen
发明人： Chung Zen Chen
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/4094 , G11C2211/4065 , G11C2211/4067
摘要： A method for controlling standby current coming from bit line leakage in random access memory devices comprises the steps of: continuously deactivating a pre-charge equalization circuit providing a pre-charge voltage to a pair of complementary bit lines of a memory cell if the memory cell is in a self-refresh mode, a standby mode or an active mode; temporarily activating the pre-charge equalization circuit before the memory cell is refreshed if the memory cell is in a self-refresh mode or a standby mode; and temporarily activating the pre-charge equalization circuit before the memory cell is refreshed or accessed if the memory cell is in an active mode.

7. 发明申请

US20120001231A1 Electrical Fuse 审中-公开
标题翻译：电保险丝
公开(公告)号：US20120001231A1
公开(公告)日：2012-01-05
申请号：US12827326
申请日：2010-06-30
申请人： Chung Zen Chen
发明人： Chung Zen Chen
IPC分类号： H01L27/088 , H01L23/525
CPC分类号： H01L27/088 , H01L21/823462 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An electrical fuse comprises first, second, and third thick oxide NMOS transistors and a thin oxide NMOS transistor. The first thick oxide NMOS transistor has a gate connected to a first input signal, and the thin oxide NMOS transistor has a drain connected to the source of the first thick oxide NMOS transistor and a gate shorted to its source. The second thick oxide transistor has a gate connected to a power up signal, a drain connected to the source of the thin oxide NMOS transistor, and a source connected to a reference voltage. The third thick oxide transistor has a gate connected to the second input signal, a drain connected to a high voltage, and a source connected to the drain of the thin oxide NMOS transistor. The first input signal and the second input signal are complementary.
摘要翻译：电熔丝包括第一，第二和第三厚氧化物NMOS晶体管和薄氧化物NMOS晶体管。第一厚氧化物NMOS晶体管具有连接到第一输入信号的栅极，并且薄氧化物NMOS晶体管具有连接到第一厚氧化物NMOS晶体管的源极的漏极和短路到其源极的栅极。第二厚氧化物晶体管具有连接到上电信号的栅极，连接到薄氧化物NMOS晶体管的源极的漏极和连接到参考电压的源极。第三厚氧化物晶体管具有连接到第二输入信号的栅极，连接到高电压的漏极和连接到薄氧化物NMOS晶体管的漏极的源极。第一输入信号和第二输入信号是互补的。

8. 发明申请

US20080316844A1 SELECTION METHOD OF BIT LINE REDUNDANCY REPAIR AND APPARATUS PERFORMING THE SAME 有权
标题翻译：位线冗余维修选择方法及其实施方法
公开(公告)号：US20080316844A1
公开(公告)日：2008-12-25
申请号：US11767154
申请日：2007-06-22
申请人： Chung Zen Chen
发明人： Chung Zen Chen
IPC分类号： G11C7/00
CPC分类号： G11C29/785 , G11C29/812 , G11C29/846
摘要： A selection method of bit line redundancy repair includes the steps of providing a plurality of logical addresses of memory blocks in the normal cell array, generating a plurality of extra fuse signals, generating a code based on states of the extra fuse signals, the code matching a defective type of the memory blocks, and selecting a plurality of redundancy blocks in the redundancy cell array to replace the memory blocks according to the code. The apparatus includes a redundancy repair enable circuit for generating a redundancy enable signal based on logical addresses of the memory blocks, a controlling fuse circuit for sending a code matching a defective type of the memory blocks, and a redundancy decoder circuit for receiving the redundancy enable signal and the code to replace a plurality of memory blocks in the normal cell array with redundancy blocks.
摘要翻译：位线冗余修复的选择方法包括以下步骤：在正常单元阵列中提供存储块的多个逻辑地址，产生多个额外的熔丝信号，基于额外的熔丝信号的状态生成代码，代码匹配存储块的缺陷类型，以及在冗余单元阵列中选择多个冗余块以根据代码替换存储块。该装置包括：冗余修复使能电路，用于基于存储块的逻辑地址生成冗余使能信号;控制熔丝电路，用于发送与缺陷类型的存储块相匹配的代码;以及冗余解码器电路，用于接收冗余使能信号和用冗余块替换正常单元阵列中的多个存储块的代码。

9. 发明授权

US07305513B2 Circuit for preventing nonvolatile memory from over-erase 有权
标题翻译：防止非易失性存储器过度擦除的电路
公开(公告)号：US07305513B2
公开(公告)日：2007-12-04
申请号：US10940987
申请日：2004-09-14
申请人： Chung Zen Chen
发明人： Chung Zen Chen
IPC分类号： G06F12/00 , G11C16/14
CPC分类号： G11C16/3468 , G11C16/3477
摘要： A method for preventing the over-erase in a nonvolatile memory comprises the following steps. First, at least one normal cell of the nonvolatile memory and at least one reference cell that corresponds to the at least one normal cell are provided with a constant current. Second, the erasing threshold voltage of the at least one normal cell is determined, and then the at least one normal cell is erased to be of the erasing threshold voltage. By virtue of adding the constant current, the higher erasing threshold voltage can be acquired, and in consequence over-erase can be avoided.
摘要翻译：一种用于防止非易失性存储器中的过度擦除的方法包括以下步骤。首先，非易失性存储器的至少一个正常单元和对应于至少一个正常单元的至少一个参考单元被提供有恒定电流。其次，确定至少一个正常单元的擦除阈值电压，然后将至少一个正常单元擦除为擦除阈值电压。通过添加恒定电流，可以获得更高的擦除阈值电压，并且因此可以避免过度擦除。

10. 发明授权

US08649236B2 Circuit and method for controlling leakage current in random access memory devices 有权
标题翻译：用于控制随机存取存储器件中的漏电流的电路和方法
公开(公告)号：US08649236B2
公开(公告)日：2014-02-11
申请号：US13105274
申请日：2011-05-11
申请人： Chung Zen Chen , Ying Wei Jan , Jian Shiang Liang
发明人： Chung Zen Chen , Ying Wei Jan , Jian Shiang Liang
IPC分类号： G11C7/00
CPC分类号： G11C11/40615 , G11C11/4094
摘要： A circuit for controlling leakage current in random access memory devices comprises a pre-charge equalization circuit. The pre-charge equalization circuit provides a pre-charge voltage to a pair of complementary bit lines of a memory cell of a random access memory device in accordance with a pre-charge signal. When the memory cell is in a self-refresh mode, the pre-charge signal is activated by a periodically triggered pre-charge request and also activated before and after the memory cell is self-refreshed.
摘要翻译：用于控制随机存取存储器件中的漏电流的电路包括预充电均衡电路。预充电均衡电路根据预充电信号向随机存取存储器件的存储单元的一对互补位线提供预充电电压。当存储器单元处于自刷新模式时，预充电信号由周期性触发的预充电请求激活，并且还在存储器单元被自刷新之前和之后激活。

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