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1. 发明申请

US20080017961A1 CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：芯片包装结构及其制造方法
公开(公告)号：US20080017961A1
公开(公告)日：2008-01-24
申请号：US11530165
申请日：2006-09-08
申请人： Chun-Hung Lin , Shih-Wen Chou , Yu-Tang Pan
发明人： Chun-Hung Lin , Shih-Wen Chou , Yu-Tang Pan
IPC分类号： H01L21/00
CPC分类号： H01L23/49816 , H01L21/561 , H01L23/3128 , H01L24/48 , H01L24/97 , H01L2224/32225 , H01L2224/48091 , H01L2224/4824 , H01L2224/73215 , H01L2224/92147 , H01L2224/97 , H01L2924/00014 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/15311 , H01L2924/181 , H01L2224/85 , H01L2224/83 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A manufacturing method of a chip package structure is provided. A circuit substrate having a first surface, a second surface, and a through hole connecting the first surface and the second surface is provided. A chip having an active surface and bonding pads disposed on the active surface is provided. The chip is fixed on the circuit substrate, wherein the second surface is opposite to the active surface and the bonding pads are exposed to the through hole. Bonding wires connecting the bonding pads and the first surface are formed through the through hole. A film having an opening is formed on the first surface. The bonding wires, the bonding pads, the through hole, and part of the first surface are exposed by the opening. An encapsulant is formed to encapsulate part of the active surface, the bonding wires, and part of the first surface. The film is removed.
摘要翻译：提供了一种芯片封装结构的制造方法。提供具有第一表面，第二表面和连接第一表面和第二表面的通孔的电路基板。提供具有有源表面的芯片和设置在有源表面上的接合焊盘。芯片固定在电路基板上，其中第二表面与有源表面相对，并且焊盘暴露于通孔。通过通孔形成连接接合焊盘和第一表面的接合线。具有开口的膜形成在第一表面上。接合线，接合焊盘，通孔和第一表面的一部分由开口露出。形成密封剂以封装部分活性表面，接合线和第一表面的一部分。电影被删除。

2. 发明申请

US20070228581A1 UNIVERSAL CHIP PACKAGE STRUCTURE 审中-公开
标题翻译：通用芯片包装结构
公开(公告)号：US20070228581A1
公开(公告)日：2007-10-04
申请号：US11761299
申请日：2007-06-11
申请人： Shih-Wen Chou , Chun-Hung Lin , Wu-Chang Tu , Yu-Tang Pan
发明人： Shih-Wen Chou , Chun-Hung Lin , Wu-Chang Tu , Yu-Tang Pan
IPC分类号： H01L23/52
CPC分类号： H01L23/13 , H01L23/3114 , H01L23/49816 , H01L24/10 , H01L24/45 , H01L24/48 , H01L2224/06135 , H01L2224/06136 , H01L2224/32225 , H01L2224/45144 , H01L2224/4824 , H01L2224/73215 , H01L2224/85186 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A universal chip package structure including a carrier, a chip, a plurality of bonding wires, and a molding compound is provided. The carrier has a plurality of through holes, a carrying surface, and a back surface corresponding to the carrying surface. The back surface has a plurality of contacts around the through holes. The chip with an active surface and a plurality of bonding pads on the active surface is disposed on the carrying surface. The active surface is attached to the carrying surface and the through holes expose the bonding pads. The bonding wires go through the through holes to electrically connect with the bonding pads and the contacts. In addition, the shape and size of the molding compound can be adjusted for covering the chip, the contacts, and the bonding wires.
摘要翻译：提供了包括载体，芯片，多个接合线和模塑料的通用芯片封装结构。载体具有多个通孔，承载表面和对应于承载表面的后表面。后表面具有围绕通孔的多个触点。具有活性表面的芯片和有源表面上的多个接合焊盘设置在承载表面上。活性表面附着在承载表面上，通孔露出接合垫。接合线穿过通孔，以与接合焊盘和触点电连接。此外，可以调整模塑料的形状和尺寸以覆盖芯片，触点和接合线。

3. 发明授权

US07514299B2 Chip package structure and manufacturing method thereof 有权
标题翻译：芯片封装结构及其制造方法
公开(公告)号：US07514299B2
公开(公告)日：2009-04-07
申请号：US11530165
申请日：2006-09-08
申请人： Chun-Hung Lin , Shih-Wen Chou , Yu-Tang Pan
发明人： Chun-Hung Lin , Shih-Wen Chou , Yu-Tang Pan
IPC分类号： H01L21/44 , H01L21/48
CPC分类号： H01L23/49816 , H01L21/561 , H01L23/3128 , H01L24/48 , H01L24/97 , H01L2224/32225 , H01L2224/48091 , H01L2224/4824 , H01L2224/73215 , H01L2224/92147 , H01L2224/97 , H01L2924/00014 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/15311 , H01L2924/181 , H01L2224/85 , H01L2224/83 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A manufacturing method of a chip package structure is provided. A circuit substrate having a first surface, a second surface, and a through hole connecting the first surface and the second surface is provided. A chip having an active surface and bonding pads disposed on the active surface is provided. The chip is fixed on the circuit substrate, wherein the second surface is opposite to the active surface and the bonding pads are exposed to the through hole. Bonding wires connecting the bonding pads and the first surface are formed through the through hole. A film having an opening is formed on the first surface. The bonding wires, the bonding pads, the through hole, and part of the first surface are exposed by the opening. An encapsulant is formed to encapsulate part of the active surface, the bonding wires, and part of the first surface. The film is removed.
摘要翻译：提供了一种芯片封装结构的制造方法。提供具有第一表面，第二表面和连接第一表面和第二表面的通孔的电路基板。提供具有有源表面的芯片和设置在有源表面上的接合焊盘。芯片固定在电路基板上，其中第二表面与有源表面相对，并且焊盘暴露于通孔。通过通孔形成连接接合焊盘和第一表面的接合线。具有开口的膜形成在第一表面上。接合线，接合焊盘，通孔和第一表面的一部分由开口露出。形成密封剂以封装部分活性表面，接合线和第一表面的一部分。电影被删除。

4. 发明申请

US20080283981A1 Chip-On-Lead and Lead-On-Chip Stacked Structure 审中-公开
标题翻译：芯片上芯片和芯片上堆叠结构
公开(公告)号：US20080283981A1
公开(公告)日：2008-11-20
申请号：US12108470
申请日：2008-04-23
申请人： Shih-Wen CHOU , Yu-Tang Pan , Chun-Hung Lin
发明人： Shih-Wen CHOU , Yu-Tang Pan , Chun-Hung Lin
IPC分类号： H01L23/495 , H01L21/98
CPC分类号： H01L23/49575 , H01L23/4951 , H01L23/49513 , H01L24/32 , H01L24/45 , H01L24/48 , H01L2224/32245 , H01L2224/451 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/73215 , H01L2224/73265 , H01L2224/8592 , H01L2924/00014 , H01L2924/01005 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2224/05599 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A chip-stacked package structure comprises a lead frame, a first chip, and a second chip. The led frame is composed of a plurality of inner leads and a plurality of outer leads. The plurality of inner leads comprises a plurality of first inner leads in parallel and a plurality of second inner leads in parallel, wherein the ends of first inner leads and the ends of second inner leads are arranged in rows facing each other at a distance. The active surface of first chip is fixedly connected to the lower surface of first inner leads and second inner leads via a first adhesive layer. A plurality of metal pads is provided near the central area of the active surface of first chip and is exposed. A second adhesive layer is formed on the back surface of second chip for fixedly connecting the back surface of second chip and the upper surface of first inner leads and second inner leads. The gap formed by the thickness of second adhesive layer prevents the bonding wires connecting the first chip from contacting the back surface of second chip.
摘要翻译：芯片堆叠封装结构包括引线框，第一芯片和第二芯片。引线框架由多个内引线和多个外引线构成。所述多个内部引线包括平行的多个第一内部引线和平行的多个第二内部引线，其中所述第一内部引线的端部和所述第二内部引线的端部被布置成彼此相隔一定距离的列。第一芯片的有源表面通过第一粘合剂层固定地连接到第一内引线和第二内引线的下表面。在第一芯片的有源表面的中心区域附近设置多个金属焊盘，并露出。在第二芯片的后表面上形成第二粘合剂层，用于固定连接第二芯片的后表面和第一内引线的上表面和第二内引线。由第二粘合剂层的厚度形成的间隙防止了连接第一芯片的接合线与第二芯片的背面接触。

5. 发明申请

US20070080466A1 Universal chip package structure 审中-公开
标题翻译：通用芯片封装结构
公开(公告)号：US20070080466A1
公开(公告)日：2007-04-12
申请号：US11326789
申请日：2006-01-05
申请人： Shih-Wen Chou , Chun-Hung Lin , Wu-Chang Tu , Yu-Tang Pan
发明人： Shih-Wen Chou , Chun-Hung Lin , Wu-Chang Tu , Yu-Tang Pan
IPC分类号： H01L23/52
CPC分类号： H01L23/13 , H01L23/3114 , H01L23/49816 , H01L24/10 , H01L24/45 , H01L24/48 , H01L2224/06135 , H01L2224/06136 , H01L2224/32225 , H01L2224/45144 , H01L2224/4824 , H01L2224/73215 , H01L2224/85186 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A universal chip package structure including a carrier, a chip, a plurality of bonding wires, and a molding compound is provided. The carrier has a plurality of through holes, a carrying surface, and a back surface corresponding to the carrying surface. The back surface has a plurality of contacts around the through holes. The chip with an active surface and a plurality of bonding pads on the active surface is disposed on the carrying surface. The active surface is attached to the carrying surface and the through holes expose the bonding pads. The bonding wires go through the through holes to electrically connect with the bonding pads and the contacts. In addition, the shape and size of the molding compound can be adjusted for covering the chip, the contacts, and the bonding wires.
摘要翻译：提供了包括载体，芯片，多个接合线和模塑料的通用芯片封装结构。载体具有多个通孔，承载表面和对应于承载表面的后表面。后表面具有围绕通孔的多个触点。具有活性表面的芯片和有源表面上的多个接合焊盘设置在承载表面上。活性表面附着在承载表面上，通孔露出接合垫。接合线穿过通孔，以与接合焊盘和触点电连接。此外，可以调整模塑料的形状和尺寸以覆盖芯片，触点和接合线。

6. 再颁专利

USRE42349E1 Wafer treating method for making adhesive dies 有权
标题翻译：用于制造粘合剂模具的晶片处理方法
公开(公告)号：USRE42349E1
公开(公告)日：2011-05-10
申请号：US11371307
申请日：2006-03-07
申请人： Chun-Hung Lin , Jesse Huang , Kuang-Hui Chen , Shih-Wen Chou
发明人： Chun-Hung Lin , Jesse Huang , Kuang-Hui Chen , Shih-Wen Chou
IPC分类号： B05D5/10 , B05D3/12 , H01L21/00
CPC分类号： H01L24/27 , H01L21/6836 , H01L23/3114 , H01L23/3128 , H01L23/4951 , H01L23/49513 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/83 , H01L25/0657 , H01L25/50 , H01L2221/68327 , H01L2224/05599 , H01L2224/06135 , H01L2224/06136 , H01L2224/274 , H01L2224/29101 , H01L2224/32014 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L2224/4824 , H01L2224/48247 , H01L2224/4826 , H01L2224/484 , H01L2224/73215 , H01L2224/73265 , H01L2224/83191 , H01L2224/83855 , H01L2224/83856 , H01L2224/85399 , H01L2224/92147 , H01L2225/0651 , H01L2225/06575 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01047 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2224/45099
摘要： A wafer treating method for making adhesive dies is provided. A liquid adhesive with two-stage property is coated on a surface of a wafer. Then, the wafer is pre-cured to make the liquid adhesive transform a thermo-bonding adhesive film having B-stage property which has a glass transition temperature not less than 40° C. for handling without adhesive under room temperature. After positioning the wafer, the wafer is singulated to form a plurality of dies with adhesive for die-to-die stacking, die-to-substrate or die-to-leadframe attaching.
摘要翻译：提供了一种用于制造粘合剂模具的晶片处理方法。具有两级特性的液体粘合剂涂覆在晶片的表面上。然后，将晶片预固化，使液体粘合剂转变具有玻璃化转变温度不低于40℃的B阶特性的热粘合粘合剂膜，以在室温下无粘合剂进行处理。在定位晶片之后，将晶片单片化以形成具有用于管芯到管芯堆叠，管芯到衬底或管芯到引线框架附接的粘合剂的多个管芯。

7. 发明申请

US20070020816A1 Manufacturing process for chip package without core 有权
标题翻译：无核心芯片封装的制造工艺
公开(公告)号：US20070020816A1
公开(公告)日：2007-01-25
申请号：US11326749
申请日：2006-01-05
申请人： Yu-Tang Pan , Geng-Shin Shen , Chun-Hung Lin
发明人： Yu-Tang Pan , Geng-Shin Shen , Chun-Hung Lin
IPC分类号： H01L21/00
CPC分类号： H01L23/3128 , H01L21/4857 , H01L24/45 , H01L24/48 , H01L25/105 , H01L2224/0401 , H01L2224/06136 , H01L2224/16225 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/4824 , H01L2224/73204 , H01L2224/73215 , H01L2224/92147 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H01L2924/15312 , H01L2924/15321 , H01L2924/15331 , H01L2924/18165 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： A manufacturing process for chip package without core is disclosed. First of all, a conductive layer with a first surface and a second surface is provided. A first film is formed onto the first surface, and the conductive layer is patterned to form a patterned circuit layer. A solder resistance layer is formed on the patterned circuit layer and then patterned to expose parts of the patterned circuit layer. After a second film is formed on the solder resistance layer and the first film is removed, a chip is disposed on the first surface and electrically connected to the patterned circuit layer. A molding compound is formed to cover the patterned circuit layer and fix the chip onto the patterned circuit layer. After that, the second film is removed.
摘要翻译：公开了一种无芯片封装的制造工艺。首先，提供具有第一表面和第二表面的导电层。第一膜形成在第一表面上，并且导电层被图案化以形成图案化的电路层。在图案化电路层上形成阻焊层，然后将其图案化以暴露图案化电路层的部分。在阻焊层上形成第二膜并且去除第一膜之后，在第一表面上设置芯片并与图案化电路层电连接。形成模塑料以覆盖图案化电路层并将芯片固定在图案化电路层上。之后，第二个膜被去除。

8. 发明授权

US07560306B2 Manufacturing process for chip package without core 有权
标题翻译：无核心芯片封装的制造工艺
公开(公告)号：US07560306B2
公开(公告)日：2009-07-14
申请号：US11326749
申请日：2006-01-05
申请人： Yu-Tang Pan , Geng-Shin Shen , Chun-Hung Lin
发明人： Yu-Tang Pan , Geng-Shin Shen , Chun-Hung Lin
IPC分类号： H01L21/50 , H01L21/48
CPC分类号： H01L23/3128 , H01L21/4857 , H01L24/45 , H01L24/48 , H01L25/105 , H01L2224/0401 , H01L2224/06136 , H01L2224/16225 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/4824 , H01L2224/73204 , H01L2224/73215 , H01L2224/92147 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H01L2924/15312 , H01L2924/15321 , H01L2924/15331 , H01L2924/18165 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： A manufacturing process for chip package without core is disclosed. First of all, a conductive layer with a first surface and a second surface is provided. A first film is formed onto the first surface, and the conductive layer is patterned to form a patterned circuit layer. A solder resistance layer is formed on the patterned circuit layer and then patterned to expose parts of the patterned circuit layer. After a second film is formed on the solder resistance layer and the first film is removed, a chip is disposed on the first surface and electrically connected to the patterned circuit layer. A molding compound is formed to cover the patterned circuit layer and fix the chip onto the patterned circuit layer. After that, the second film is removed.
摘要翻译：公开了一种无芯片封装的制造工艺。首先，提供具有第一表面和第二表面的导电层。第一膜形成在第一表面上，并且导电层被图案化以形成图案化的电路层。在图案化电路层上形成阻焊层，然后将其图案化以暴露图案化电路层的部分。在阻焊层上形成第二膜并且去除第一膜之后，在第一表面上设置芯片并与图案化电路层电连接。形成模塑料以覆盖图案化电路层并将芯片固定在图案化电路层上。之后，第二个膜被去除。

9. 发明授权

US08927314B2 Method of manufacturing solar cell with two exposed surfaces of arc layer disposed at different levels 有权
标题翻译：制造太阳能电池的方法，其具有设置在不同水平的弧形层的两个暴露表面
公开(公告)号：US08927314B2
公开(公告)日：2015-01-06
申请号：US13549814
申请日：2012-07-16
申请人： Sheng Yung Liu , Chin-Tien Yang , Chun-Hung Lin
发明人： Sheng Yung Liu , Chin-Tien Yang , Chun-Hung Lin
IPC分类号： H01L21/00 , H01L31/0224 , H01L31/0216
CPC分类号： H01L31/022433 , H01L31/02168 , Y02E10/50 , Y02E10/52
摘要： A method of manufacturing a solar cell includes the steps of: providing a substrate having a front side, a back side and a doped region; forming a conductor layer on the front side; firing the conductor layer at a temperature such that the conductor layer is formed with a first portion embedded into the doped region and a second portion other than the first portion; forming an anti-reflection coating (ARC) layer on the front side and the second portion, wherein the ARC layer covers the conductor layer so that the second portion of the conductor layer is disposed in the ARC layer; and removing the ARC layer on the conductor layer so that the conductor layer has an exposed surface exposed out of the ARC layer, wherein the exposed surface of the conductor layer is substantially flush with a first exposed surface of the ARC layer.
摘要翻译：一种制造太阳能电池的方法包括以下步骤：提供具有正面，背面和掺杂区域的基板; 在前侧形成导体层; 在使得导体层形成有嵌入掺杂区域的第一部分和除了第一部分之外的第二部分的温度下烧制导体层; 在前侧和第二部分形成防反射涂层（ARC）层，其中ARC层覆盖导体层，使得导体层的第二部分设置在ARC层中; 以及去除所述导体层上的所述ARC层，使得所述导体层具有暴露在所述ARC层外部的暴露表面，其中所述导体层的所述暴露表面基本上与所述ARC层的第一暴露表面齐平。

10. 发明授权

US08728851B2 Method of manufacturing solar cell with upper and lower conductor layers stacked together 有权
标题翻译：具有层叠在一起的上下导体层的太阳能电池的制造方法
公开(公告)号：US08728851B2
公开(公告)日：2014-05-20
申请号：US13549877
申请日：2012-07-16
申请人： Sheng Yung Liu , Chin-Tien Yang , Chun-Hung Lin
发明人： Sheng Yung Liu , Chin-Tien Yang , Chun-Hung Lin
IPC分类号： H01L31/18
CPC分类号： H01L31/022433 , H01L31/02168 , Y02E10/50 , Y02E10/52
摘要： A method of manufacturing a solar cell comprises the steps of: forming a lower conductor layer on a front side of a substrate; firing the lower conductor layer at a first temperature to form a first portion embedded into a doped region of the substrate and a second portion; forming an anti-reflection coating (ARC) layer on the front side and the second portion, wherein the ARC layer covers the lower conductor layer such that the second portion is disposed in the ARC layer; forming an upper conductor layer, corresponding to the lower conductor layer and electrically connected to the lower conductor layer, on the ARC layer; and firing the upper conductor layer at a second temperature to form a first portion embedded into the ARC layer and a second portion, which is exposed out of the ARC layer.
摘要翻译：一种制造太阳能电池的方法包括以下步骤：在基板的正面形成下导体层; 在第一温度下焙烧下导体层以形成嵌入衬底的掺杂区域中的第一部分和第二部分; 在前侧和第二部分形成防反射涂层（ARC）层，其中ARC层覆盖下导体层，使得第二部分设置在ARC层中; 在ARC层上形成对应于下导体层并电连接到下导体层的上导体层; 以及在第二温度下烧制所述上导体层以形成嵌入到所述ARC层中的第一部分和暴露在所述ARC层外的第二部分。

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