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1. 发明授权

US07724230B2 Driving circuit of liquid crystal display device and method for driving the same 有权
标题翻译：液晶显示装置的驱动电路及其驱动方法
公开(公告)号：US07724230B2
公开(公告)日：2010-05-25
申请号：US11375035
申请日：2006-03-15
申请人： Sun Young Kim , Chul Sang Jang , Jong Hoon Kim
发明人： Sun Young Kim , Chul Sang Jang , Jong Hoon Kim
IPC分类号： G09G3/36
CPC分类号： G09G3/2003 , G09G3/3648 , G09G2300/0426 , G09G2310/0218
摘要： A driving circuit of a display device includes a timing controller for combining p first digital data signals (p being a positive integer greater than 1) corresponding to colors for displaying images to generate q second digital data signals and for supplying the q second digital data signals to first to qth data transmission lines (q being a positive integer smaller than p), and a plurality of data driver integrated circuits for processing the q second digital data signals from the timing controller to restore the p first digital data signals, converting the p restored digital data signals into analog data signals, and supplying the analog data signals to a display panel.
摘要翻译：显示装置的驱动电路包括：时序控制器，用于组合对应于用于显示图像的颜色的p个第一数字数据信号（p是大于1的正整数）以产生q个第二数字数据信号，并用于提供q个第二数字数据信号到第一至第q数据传输线（q是小于p的正整数）和多个数据驱动器集成电路，用于处理来自定时控制器的q个第二数字数据信号以恢复p个第一数字数据信号，转换p 将数字数据信号恢复为模拟数据信号，并将模拟数据信号提供给显示面板。

2. 发明授权

US07629956B2 Apparatus and method for driving image display device 有权
标题翻译：用于驱动图像显示装置的装置和方法
公开(公告)号：US07629956B2
公开(公告)日：2009-12-08
申请号：US11301948
申请日：2005-12-13
申请人： Chul Sang Jang , Jong Hoon Kim
发明人： Chul Sang Jang , Jong Hoon Kim
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G3/3648 , G09G2300/0876 , G09G2310/027 , G09G2330/021 , G09G2330/06
摘要： An apparatus and method for driving an image display device is disclosed, in which data signals are transmitted in a multilevel to reduce transmission frequencies, power consumption and transmission lines. The apparatus for driving an image display device includes a display panel including an image display unit for displaying images, a plurality of data driver integrated circuits supplying image signals to the image display unit, and a timing controller converting externally supplied i bit digital source data (i is a positive number) to a plurality of voltage levels to supply the converted voltage levels to the respective data driver integrated circuits and controlling the data driver integrated circuits.
摘要翻译：公开了一种用于驱动图像显示装置的装置和方法，其中数据信号以多级传输以减少传输频率，功耗和传输线。用于驱动图像显示装置的装置包括：显示面板，包括用于显示图像的图像显示单元，向图像显示单元提供图像信号的多个数据驱动器集成电路;以及转换外部提供的i位数字源数据的定时控制器 i是正数）到多个电压电平，以将转换的电压电平提供给各个数据驱动器集成电路并控制数据驱动器集成电路。

3. 发明授权

US07834836B2 Flat display apparatus and picture quality controlling method thereof 有权
标题翻译：平面显示装置及其图像质量控制方法
公开(公告)号：US07834836B2
公开(公告)日：2010-11-16
申请号：US11477386
申请日：2006-06-30
申请人： In Jae Chung , Chul Sang Jang , Sung Hak Jo , Deuk Su Lee , Jong Hoon Kim , Jong Hee Hwang
发明人： In Jae Chung , Chul Sang Jang , Sung Hak Jo , Deuk Su Lee , Jong Hoon Kim , Jong Hee Hwang
IPC分类号： G09G3/36
CPC分类号： G09G3/20 , G09G3/2011 , G09G3/3648 , G09G2300/0452 , G09G2320/0285 , G09G2330/10 , G09G2370/047
摘要： A flat panel display device includes a display panel, a memory storing a compensation value that corresponds to a panel defect location, the panel defect location being where any one of a brightness and a color difference exists compared to other part of the display panel, a compensating unit to adjust image data to be displayed in the panel defect location using the compensation value, and a driver to apply the adjusted image data from the compensating unit to the display panel.
摘要翻译：平板显示装置包括显示面板，存储对应于面板缺陷位置的补偿值的存储器，面板缺陷位置与显示面板的其他部分相比存在亮度和色差中的任何一个，其中，补偿单元，用于使用补偿值来调整要在面板缺陷位置显示的图像数据;以及驱动器，用于将来自补偿单元的经调整的图像数据应用于显示面板。

4. 发明授权

US08847377B2 Stacked wafer level package having a reduced size 有权
标题翻译：具有减小尺寸的堆叠晶片级封装
公开(公告)号：US08847377B2
公开(公告)日：2014-09-30
申请号：US13569600
申请日：2012-08-08
申请人： Jong Hoon Kim , Min Suk Suh , Seung Taek Yang , Seung Hyun Lee , Tae Min Kang
发明人： Jong Hoon Kim , Min Suk Suh , Seung Taek Yang , Seung Hyun Lee , Tae Min Kang
IPC分类号： H01L23/02 , H01L21/683 , H01L21/56 , H01L23/538 , H01L25/00 , H01L25/065 , H01L23/31 , H01L23/00 , H01L25/18
CPC分类号： H01L25/0652 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L23/3114 , H01L23/5389 , H01L24/13 , H01L24/19 , H01L24/20 , H01L24/96 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2221/68345 , H01L2224/12105 , H01L2224/13024 , H01L2224/131 , H01L2224/2105 , H01L2224/221 , H01L2224/97 , H01L2225/06562 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01059 , H01L2924/01078 , H01L2924/014 , H01L2924/15311 , H01L2924/15788 , H01L2924/18161 , H01L2224/19 , H01L2924/00
摘要： A stacked wafer level package includes a first semiconductor chip having a first bonding pad and a second semiconductor chip having a second bonding pad. Both bonding pads of the semiconductor chips face the same direction. The second semiconductor chip is disposed in parallel to the first semiconductor chip. A third semiconductor chip is disposed over the first and second semiconductor chips acting as a supporting substrate. The third semiconductor chip has a third bonding pad that is exposed between the first and the second semiconductor chips upon attachment. Finally, a redistribution structure is electrically connected to the first, second, and third bonding pads.
摘要翻译：堆叠的晶片级封装包括具有第一焊盘的第一半导体芯片和具有第二焊盘的第二半导体芯片。半导体芯片的两个接合焊盘面向相同的方向。第二半导体芯片与第一半导体芯片平行设置。第三半导体芯片设置在用作支撑衬底的第一和第二半导体芯片上。第三半导体芯片具有在附接时在第一和第二半导体芯片之间露出的第三焊盘。最后，再分布结构电连接到第一，第二和第三键合焊盘。

5. 发明授权

US08804305B2 Multilayer ceramic condenser and method for manufacturing the same 有权
标题翻译：多层陶瓷电容器及其制造方法
公开(公告)号：US08804305B2
公开(公告)日：2014-08-12
申请号：US13191890
申请日：2011-07-27
申请人： Hyung Joon Kim , Jong Hoon Kim
发明人： Hyung Joon Kim , Jong Hoon Kim
IPC分类号： H01G4/06
CPC分类号： H01G4/1227 , H01G4/008 , H01G4/012 , H01G4/232 , H01G4/2325 , H01G4/30 , Y10T29/435
摘要： Disclosed are a multilayer ceramic condenser and a method for manufacturing the same. There is provided a multilayer ceramic condenser including: a multilayer main body in which a plurality of dielectric layers including a first side, a second side, a third side, and a fourth side are stacked; a first cover layer and a second cover layer forming the plurality of dielectric layers; a first dielectric layer disposed between the first cover layer and the second cover layer and printed with a first inner electrode pattern drawn to the first side; a second dielectric layer alternately stacked with the first dielectric layer and printed with a second inner electrode pattern drawn to the third side; and a first side portion and a second side portion each formed on the second side and the fourth side opposite to each other.
摘要翻译：公开了一种多层陶瓷电容器及其制造方法。提供了一种多层陶瓷电容器，包括：多层主体，其中堆叠包括第一侧，第二侧，第三侧和第四侧的多个电介质层; 形成所述多个电介质层的第一覆盖层和第二覆盖层; 第一电介质层，设置在第一覆盖层和第二覆盖层之间，并印刷有第一内部电极图案，其被绘制到第一侧; 第二电介质层，与所述第一电介质层交替堆叠并且印刷有第二内部电极图案，所述第二内部电极图案被绘制到所述第三侧; 以及分别形成在彼此相对的第二侧和第四侧上的第一侧部和第二侧部。

6. 发明申请

US20120114535A1 COMPOUND FOR INHIBITING ACTIVITY OF RIBONUCLEASE, AND CONTAINER FOR STORING NUCLEIC ACID CONTAINING THE SAME 有权
标题翻译：用于抑制RIBONUCLEASE活性的化合物和用于储存含有其的核酸的容器
公开(公告)号：US20120114535A1
公开(公告)日：2012-05-10
申请号：US13377377
申请日：2009-06-12
申请人： Jong Hoon Kim , Hwangseo Park , Han Oh Park
发明人： Jong Hoon Kim , Hwangseo Park , Han Oh Park
IPC分类号： B01L3/00 , C07D403/06 , C07D405/12 , C07D405/06
CPC分类号： C07D403/06 , C07D231/38 , C07D403/12 , C07D405/06
摘要： Provided are an RNase activity inhibitory compound to effectively control the activity of the RNase promoting degradation of extracted RNAs and, in addition, a sample storage container including the same. The RNase activity inhibitory compound and the sample storage container according to the present invention may be effectively used to store RNAs during RNA extraction or the extracted RNAs.
摘要翻译：提供了一种RNase活性抑制化合物，用于有效控制RNA酶的活性，促进提取的RNA的降解，另外还含有包含其的样品储存容器。根据本发明的RNA酶活性抑制化合物和样品储存容器可以有效地用于在RNA提取期间或所提取的RNA中存储RNA。

7. 发明授权

US08026586B2 Semiconductor package 有权
标题翻译：半导体封装
公开(公告)号：US08026586B2
公开(公告)日：2011-09-27
申请号：US12647640
申请日：2009-12-28
申请人： Jong Hoon Kim
发明人： Jong Hoon Kim
IPC分类号： H01L23/02
CPC分类号： H01L23/13 , H01L23/3128 , H01L23/481 , H01L23/49816 , H01L24/45 , H01L24/48 , H01L25/0657 , H01L25/50 , H01L2224/32225 , H01L2224/451 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/73215 , H01L2224/73265 , H01L2225/0651 , H01L2225/06541 , H01L2225/06555 , H01L2225/06562 , H01L2225/06596 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/00015 , H01L2224/05599 , H01L2924/00012 , H01L2924/00
摘要： A semiconductor package comprises a substrate having bond fingers on an upper surface thereof and ball lands on a lower surface thereof; at least two chip modules stacked on the upper surface of the substrate, each of the at least two chip modules including a plurality of semiconductor chips having first connection members and stacked in a manner such that the first connection members of the semiconductor chips are connected to one another, the chip modules being stacked in a zigzag pattern such that connection parts of the chip modules project sideward; and second connection members electrically connecting the connection parts of the respective chip modules to the bond fingers of the substrate.
摘要翻译：半导体封装包括在其上表面上具有键合指状物的衬底，并且在其下表面上具有焊盘; 至少两个芯片模块堆叠在所述基板的上表面上，所述至少两个芯片模块中的每一个包括多个半导体芯片，所述多个半导体芯片具有第一连接构件，并且以使得所述半导体芯片的所述第一连接构件连接到另一方面，芯片模块以锯齿形图案堆叠，使得芯片模块的连接部分向侧面投射; 以及第二连接构件，其将各个芯片模块的连接部分电连接到基板的键合指状物。

8. 发明授权

US07745439B2 Indene derivatives and process for the preparation thereof 失效
标题翻译：茚衍生物及其制备方法
公开(公告)号：US07745439B2
公开(公告)日：2010-06-29
申请号：US10599913
申请日：2005-04-12
申请人： Hyae Gyeong Cheon , Sung-Eun Yoo , Sung Soo Kim , Sung-Don Yang , Kwang-Rok Kim , Sang Dal Rhee , Jin Hee Ahn , Seung Kyu Kang , Won Hoon Jung , Sung Dae Park , Nam Gee Kim , Sun Mee Kim , Kil Woong Mo , Jae Mok Lee , Hye Jung Kang , Koun Ho Lee , Jong Hoon Kim , Jeong-Hyung Lee , Seung Jun Kim
发明人： Hyae Gyeong Cheon , Sung-Eun Yoo , Sung Soo Kim , Sung-Don Yang , Kwang-Rok Kim , Sang Dal Rhee , Jin Hee Ahn , Seung Kyu Kang , Won Hoon Jung , Sung Dae Park , Nam Gee Kim , Sun Mee Kim , Kil Woong Mo , Jae Mok Lee , Hye Jung Kang , Koun Ho Lee , Jong Hoon Kim , Jeong-Hyung Lee , Seung Jun Kim
IPC分类号： A61K31/216 , A61K31/4402 , A61K31/5375 , C07C69/753 , C07D211/70 , C07D265/32
CPC分类号： C07D295/088 , C07C65/26 , C07C69/757 , C07C229/50 , C07C233/52 , C07C255/47 , C07C2601/14 , C07C2602/08 , C07D295/155
摘要： The inventive indene derivatives of formula (I) are capable of selectively modulating the activities of peroxisome proliferator activated receptors (PPARs), causing no adverse side effects, and thus, they are useful for the treatment and prevention of disorders modulated by PPARs, i.e., metabolic syndromes such as diabetes, obesity, arteriosclerosis, hyperlipidemia, hyperinsulinism and hypertension, inflammatory diseases such as osteoporosis, liver cirrhosis and asthma, and cancer.
摘要翻译：式（I）的本发明的茚衍生物能够选择性调节过氧化物酶体增殖物激活受体（PPAR）的活性，不引起副作用，因此它们可用于治疗和预防由PPARs调节的病症，糖尿病，肥胖，动脉硬化，高脂血症，高胰岛素血症和高血压等代谢综合征，骨质疏松症，肝硬化和哮喘等炎性疾病和癌症。

9. 发明授权

US07495340B2 Metal layer structure of semiconductor device 有权
标题翻译：半导体器件的金属层结构
公开(公告)号：US07495340B2
公开(公告)日：2009-02-24
申请号：US11646698
申请日：2006-12-28
申请人： Jong Hoon Kim
发明人： Jong Hoon Kim
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L23/528 , H01L27/0207 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： A metal layer structure of a semiconductor memory device is disclosed. The metal layer structure includes: a first metal layer to be connected to a contact plug; and a plurality of a second metal layers that are formed in parallel at a second spaced distance around the first metal layer, wherein a spaced distance of the second metal layers nearest the first metal layer maintains the second spaced distance which is wider than a first spaced distance of the second metal layers around the contact plug, and the spaced distance of the second metal layer next to the first metal layer maintains a third spaced distance, which is narrower than the second spaced distance, and the spaced distance between adjacent second metal layers gradually decreases to eventually be equal to the first spaced distance, for the second metal layers farthest from the first metal layer. Accordingly, an alignment margin can be ensured without requiring more area, and the contact plug can be connected to the next metal layer, even if an alignment error is produced.
摘要翻译：公开了一种半导体存储器件的金属层结构。金属层结构包括：要连接到接触插塞的第一金属层; 以及多个第二金属层，所述多个第二金属层以围绕所述第一金属层的第二间隔距离平行地形成，其中所述第二金属层与所述第一金属层最近的间隔距离保持第二间隔距离，第二金属层围绕接触塞的距离以及与第一金属层相邻的第二金属层的间隔距离保持比第二间隔距离窄的第三间隔距离，并且相邻的第二金属层之间的间隔距离对于距离第一金属层最远的第二金属层，逐渐减小以最终等于第一间隔距离。因此，即使产生对准误差，也可以确保对准余量而不需要更多的面积，并且可以将接触插塞连接到下一个金属层。

10. 发明授权

US07473700B2 1,2,4-triazole derivatives, processes for the preparation thereof, and pharmaceutical compositions containing the same 失效
标题翻译： 1,2,4-三唑衍生物，其制备方法和含有它们的药物组合物
公开(公告)号：US07473700B2
公开(公告)日：2009-01-06
申请号：US10536408
申请日：2003-11-26
申请人： Il Hwan Cho , Dong Hyun Ko , Myeong Yun Chae , In Ki Min , Young Hoon Kim , Kyu Jeong Yeon , Jong Hoon Kim , Sung Hak Jung , Sang Wook Park , Il Hwan Kim , Hyung Chul Ryu , Ji Young Noh , Hyun Jung Park , Jie Eun Park , Young Mee Chung
发明人： Il Hwan Cho , Dong Hyun Ko , Myeong Yun Chae , In Ki Min , Young Hoon Kim , Kyu Jeong Yeon , Jong Hoon Kim , Sung Hak Jung , Sang Wook Park , Il Hwan Kim , Hyung Chul Ryu , Ji Young Noh , Hyun Jung Park , Jie Eun Park , Young Mee Chung
IPC分类号： A61K31/41 , C07D249/08
CPC分类号： C07D249/12 , C07D249/10
摘要： A 1,2,4-triazole derivative of formula 1 or a non-toxic salt thereof, a preparation method thereof, and a pharmaceutical composition containing the derivative or the salt as an active ingredient are provided.
摘要翻译：提供式1的1,2,4-三唑衍生物或其无毒盐，其制备方法和含有该衍生物或盐作为有效成分的药物组合物。

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