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1. 发明授权

US07371629B2 N/PMOS saturation current, HCE, and Vt stability by contact etch stop film modifications 有权
标题翻译： N / PMOS饱和电流，HCE和Vt稳定性通过接触蚀刻停止膜修改
公开(公告)号：US07371629B2
公开(公告)日：2008-05-13
申请号：US10314689
申请日：2002-12-09
申请人： Chu-Yun Fu , Chi-Hsun Hsieh , Yi-Ming Sheu , Syun-Ming Jang
发明人： Chu-Yun Fu , Chi-Hsun Hsieh , Yi-Ming Sheu , Syun-Ming Jang
IPC分类号： H01L21/8237
CPC分类号： H01L21/0217 , H01L21/02274 , H01L21/28247 , H01L21/3185 , H01L21/823814 , H01L21/823835
摘要： A method is provided for improving Idsat in NMOS and PMOS transistors. A silicon nitride etch stop layer is deposited by a PECVD technique on STI and silicide regions and on sidewall spacers during a MOSFET manufacturing scheme. A dielectric layer is formed on the nitride and then contact holes are fabricated through the dielectric layer and nitride layer to silicide regions and are filled with a metal. For NMOS transistors, silane and NH3 flow rates and a 400° C. temperature are critical in improving NMOS short channel Idsat. Hydrogen content in the nitride is increased by higher NH3 and SiH4 flow rates but does not significantly degrade HCE and Vt. With PMOS transistors, deposition temperature is increased to 550° C. to reduce hydrogen content and improve HCE and Vt stability.
摘要翻译：提供了一种用于改善NMOS和PMOS晶体管中的Idsat的方法。在MOSFET制造方案中，通过PECVD技术在STI和硅化物区域和侧壁间隔物上沉积氮化硅蚀刻停止层。在氮化物上形成介电层，然后通过电介质层和氮化物层到硅化物区域制造接触孔，并填充金属。对于NMOS晶体管，硅烷和NH 3 3流速和400℃的温度对于改善NMOS短沟道Idsat至关重要。氮化物中的氢含量通过较高的NH 3和SiH 4 O 3流速而增加，但不会显着降低HCE和Vt。使用PMOS晶体管，沉积温度增加到550° C.降低氢含量，提高HCE和Vt稳定性。

2. 发明申请

US20050133830A1 Method for fabricating a recessed channel filed effect transistor (FET) device 失效
标题翻译：凹陷通道场效应晶体管（FET）器件的制造方法
公开(公告)号：US20050133830A1
公开(公告)日：2005-06-23
申请号：US10739476
申请日：2003-12-17
申请人： Carlos Diaz , Yi-Ming Sheu , Syun-Ming Jang , Hun-Jan Tao , Fu-Liang Yang
发明人： Carlos Diaz , Yi-Ming Sheu , Syun-Ming Jang , Hun-Jan Tao , Fu-Liang Yang
IPC分类号： H01L21/336 , H01L29/786 , H01L21/8234 , H01L29/76 , H01L31/113
CPC分类号： H01L29/66772 , H01L29/66545 , H01L29/66621 , H01L29/78621 , H01L29/78654
摘要： A method for forming a field effect transistor device employs a self-aligned etching of a semiconductor substrate to form a recessed channel region in conjunction with a pair of raised source/drain regions. The method also provides for forming and thermally annealing the pair of source/drain regions prior to forming a pair of lightly doped extension regions within the field effect transistor device. In accord with the foregoing features, the field effect transistor device is fabricated with enhanced performance.
摘要翻译：用于形成场效应晶体管器件的方法采用半导体衬底的自对准蚀刻以与一对凸起的源极/漏极区域结合形成凹陷沟道区域。该方法还提供了在场效应晶体管器件内形成一对轻掺杂的延伸区域之前，对成对的源/漏区进行形成和热退火。根据上述特征，以增强的性能制造场效应晶体管器件。

3. 发明授权

US07429769B2 Recessed channel field effect transistor (FET) device 有权
标题翻译：嵌入式沟道场效应晶体管（FET）器件
公开(公告)号：US07429769B2
公开(公告)日：2008-09-30
申请号：US11255389
申请日：2005-10-21
申请人： Carlos H. Diaz , Yi-Ming Sheu , Syun-Ming Jang , Hun-Jan Tao , Fu-Liang Yang
发明人： Carlos H. Diaz , Yi-Ming Sheu , Syun-Ming Jang , Hun-Jan Tao , Fu-Liang Yang
IPC分类号： H01L29/78
CPC分类号： H01L29/66772 , H01L29/66545 , H01L29/66621 , H01L29/78621 , H01L29/78654
摘要： A method for forming a field effect transistor device employs a self-aligned etching of a semiconductor substrate to form a recessed channel region in conjunction with a pair of raised source/drain regions. The method also provides for forming and thermally annealing the pair of source/drain regions prior to forming a pair of lightly doped extension regions within the field effect transistor device. In accord with the foregoing features, the field effect transistor device is fabricated with enhanced performance.
摘要翻译：用于形成场效应晶体管器件的方法采用半导体衬底的自对准蚀刻以与一对凸起的源极/漏极区域结合形成凹陷沟道区域。该方法还提供了在场效应晶体管器件内形成一对轻掺杂的延伸区域之前，对成对的源/漏区进行形成和热退火。根据上述特征，以增强的性能制造场效应晶体管器件。

4. 发明授权

US06974730B2 Method for fabricating a recessed channel field effect transistor (FET) device 失效
标题翻译：凹陷通道场效应晶体管（FET）器件的制造方法
公开(公告)号：US06974730B2
公开(公告)日：2005-12-13
申请号：US10739476
申请日：2003-12-17
申请人： Carlos H. Diaz , Yi-Ming Sheu , Syun-Ming Jang , Hun-Jan Tao , Fu-Liang Yang
发明人： Carlos H. Diaz , Yi-Ming Sheu , Syun-Ming Jang , Hun-Jan Tao , Fu-Liang Yang
IPC分类号： H01L21/336 , H01L29/786
CPC分类号： H01L29/66772 , H01L29/66545 , H01L29/66621 , H01L29/78621 , H01L29/78654
摘要： A method for forming a field effect transistor device employs a self-aligned etching of a semiconductor substrate to form a recessed channel region in conjunction with a pair of raised source/drain regions. The method also provides for forming and thermally annealing the pair of source/drain regions prior to forming a pair of lightly doped extension regions within the field effect transistor device. In accord with the foregoing features, the field effect transistor device is fabricated with enhanced performance.
摘要翻译：用于形成场效应晶体管器件的方法采用半导体衬底的自对准蚀刻以与一对凸起的源极/漏极区域结合形成凹陷沟道区域。该方法还提供了在场效应晶体管器件内形成一对轻掺杂的延伸区域之前，对成对的源/漏区进行形成和热退火。根据上述特征，以增强的性能制造场效应晶体管器件。

5. 发明申请

US20060033158A1 Method for fabricating a recessed channel field effect transistor (FET) device 有权
标题翻译：凹陷通道场效应晶体管（FET）器件的制造方法
公开(公告)号：US20060033158A1
公开(公告)日：2006-02-16
申请号：US11255389
申请日：2005-10-21
申请人： Carlos Diaz , Yi-Ming Sheu , Syun-Ming Jang , Hun-Jan Tao , Fu-Liang Yang
发明人： Carlos Diaz , Yi-Ming Sheu , Syun-Ming Jang , Hun-Jan Tao , Fu-Liang Yang
IPC分类号： H01L29/78
CPC分类号： H01L29/66772 , H01L29/66545 , H01L29/66621 , H01L29/78621 , H01L29/78654
摘要： A method for forming a field effect transistor device employs a self-aligned etching of a semiconductor substrate to form a recessed channel region in conjunction with a pair of raised source/drain regions. The method also provides for forming and thermally annealing the pair of source/drain regions prior to forming a pair of lightly doped extension regions within the field effect transistor device. In accord with the foregoing features, the field effect transistor device is fabricated with enhanced performance.
摘要翻译：用于形成场效应晶体管器件的方法采用半导体衬底的自对准蚀刻以与一对凸起的源极/漏极区域结合形成凹陷沟道区域。该方法还提供了在场效应晶体管器件内形成一对轻掺杂的延伸区域之前，对成对的源/漏区进行形成和热退火。根据上述特征，以增强的性能制造场效应晶体管器件。

6. 发明授权

US06670226B2 Planarizing method for fabricating gate electrodes 有权
公开(公告)号：US06670226B2
公开(公告)日：2003-12-30
申请号：US10094460
申请日：2002-03-08
申请人： Yo-Sheng Lin , Yi-Ming Sheu , Da-Wen Lin , Chi-Hsun Hsieh
发明人： Yo-Sheng Lin , Yi-Ming Sheu , Da-Wen Lin , Chi-Hsun Hsieh
IPC分类号： H01L218238
CPC分类号： H01L21/823842 , H01L21/32115 , H01L21/3212
摘要： Within a method for fabricating a semiconductor integrated circuit microelectronic fabrication, there is employed a planarizing method for forming, in a self aligned fashion, a patterned second gate electrode material layer laterally adjacent but not over a patterned first gate electrode material layer, such that upon further patterning of the patterned first gate electrode material layer and the patterned second gate electrode material layer there may be formed a first gate electrode over a first active region of a semiconductor substrate and a second gate electrode over a laterally adjacent second active region of the semiconductor substrate. The method is particularly useful within the context of complementary metal oxide semiconductor (CMOS) semiconductor integrated circuit microelectronic fabrications.

7. 发明授权

US08354718B2 Semiconductor device including an arrangement for suppressing short channel effects 有权
标题翻译：包括用于抑制短信道效应的装置的半导体装置
公开(公告)号：US08354718B2
公开(公告)日：2013-01-15
申请号：US11751959
申请日：2007-05-22
申请人： Chih-Chiang Wang , Yi-Ming Sheu , Ying-Shiou Lin
发明人： Chih-Chiang Wang , Yi-Ming Sheu , Ying-Shiou Lin
IPC分类号： H01L21/02
CPC分类号： H01L29/1083 , H01L29/66636
摘要： An apparatus comprising a substrate of first dopant type and first dopant concentration; pocket regions in the substrate and having the first dopant type and a second dopant concentration greater than the first dopant concentration; a gate stack over the substrate and laterally between the pocket regions; first and second source/drain regions on opposing sides of the gate stack and vertically between the gate stack and the pocket regions, the first and second source/drain regions having a second dopant type opposite the first dopant type and a third dopant concentration; and third and fourth source/drain regions having the second dopant type and a fourth dopant concentration that is greater than the third dopant concentration, wherein the pocket regions are between the third and fourth source/drain regions, and the third and fourth source/drain regions are vertically between the first and second source/drain regions and a bulk portion of the substrate.
摘要翻译：一种装置，包括第一掺杂剂型和第一掺杂剂浓度的衬底; 并且具有大于第一掺杂剂浓度的第一掺杂剂类型和第二掺杂剂浓度; 在所述衬底上方的栅堆叠，并且在所述袋区域之间横向; 第一和第二源极/漏极区域在栅极堆叠的相对侧上并且垂直地在栅极堆叠层与凹穴区域之间，第一和第二源极/漏极区域具有与第一掺杂剂类型相反的第二掺杂剂类型和第三掺杂剂浓度; 以及具有大于第三掺杂剂浓度的第二掺杂剂类型和第四掺杂剂浓度的第三和第四源极/漏极区域，其中所述穴状区域在第三和第四源极/漏极区域之间，并且第三和第四源极/漏极区域在第一和第二源极/漏极区域之间以及基板的主体部分之间是垂直的。

8. 发明授权

US06703187B2 Method of forming a self-aligned twin well structure with a single mask 失效
标题翻译：用单一掩模形成自对准双阱结构的方法
公开(公告)号：US06703187B2
公开(公告)日：2004-03-09
申请号：US10043861
申请日：2002-01-09
申请人： Yi-Ming Sheu , Fu-Liang Yang
发明人： Yi-Ming Sheu , Fu-Liang Yang
IPC分类号： G03F726
CPC分类号： H01L21/823892 , H01L21/823878
摘要： An improved method for forming a self-aligned twin well structure for use in a CMOS semiconductor device including providing a substrate for forming a twin well structure therein; forming an implant masking layer over the substrate to include a process surface said masking layer patterned to expose a first portion of the process surface for implanting ions; subjecting the first portion of the process surface to a first ion implantation process to form a first doped region included in the substrate; forming an implant blocking layer including a material that is selectively etchable to the implant masking layer over the first portion of the process surface; removing the implant masking layer to expose a second portion of the process surface; and, subjecting the second portion of the process surface to a second ion implantation process to form a second doped region disposed adjacent to the first doped region.
摘要翻译：一种用于形成用于CMOS半导体器件的自对准双阱结构的改进方法，包括提供用于在其中形成双阱结构的衬底; 在所述衬底上形成注入掩模层以包括工艺表面，所述掩模层被图案化以暴露所述工艺表面的第一部分以用于注入离子; 使处理表面的第一部分经受第一离子注入工艺以形成包括在衬底中的第一掺杂区; 形成植入阻挡层，所述植入物阻挡层包括在所述过程表面的所述第一部分上可选择地蚀刻到所述植入物掩模层的材料; 去除所述植入物掩模层以暴露所述工艺表面的第二部分; 以及对所述工艺表面的第二部分进行第二离子注入工艺以形成邻近所述第一掺杂区域设置的第二掺杂区域。

9. 发明授权

US07598130B2 Method for reducing layout-dependent variations in semiconductor devices 有权
标题翻译：减少半导体器件中与布局有关的变化的方法
公开(公告)号：US07598130B2
公开(公告)日：2009-10-06
申请号：US11529091
申请日：2006-09-28
申请人： Chung-Heng Yang , Yi-Ming Sheu , Sheng-Jier Yang
发明人： Chung-Heng Yang , Yi-Ming Sheu , Sheng-Jier Yang
IPC分类号： H01L21/00
CPC分类号： H01L21/823493 , H01L21/2652 , H01L21/823892
摘要： A method for forming an integrated circuit includes providing a semiconductor substrate, forming a re-implantation blocking layer over the semiconductor substrate, forming a mask over the re-implantation blocking layer, patterning the mask to form an opening, wherein a portion of the re-implantation blocking layer is exposed through the opening, performing an implantation to introduce an impurity into a portion of the semiconductor substrate underlying the opening to form a well region, removing the mask, and removing the re-implantation blocking layer.
摘要翻译：一种用于形成集成电路的方法包括提供半导体衬底，在半导体衬底上形成再注入阻挡层，在重新注入阻挡层上形成掩模，图案化掩模以形成开口，其中一部分re 通过开口暴露植入阻挡层，进行注入以将杂质引入到开口下方的半导体衬底的一部分中以形成阱区，去除掩模，以及去除重新注入阻挡层。

10. 发明授权

US07545001B2 Semiconductor device having high drive current and method of manufacture therefor 有权
标题翻译：具有高驱动电流的半导体器件及其制造方法
公开(公告)号：US07545001B2
公开(公告)日：2009-06-09
申请号：US10722218
申请日：2003-11-25
申请人： Shui-Ming Cheng , Ka-Hing Fung , Kuan Lun Cheng , Yi-Ming Sheu
发明人： Shui-Ming Cheng , Ka-Hing Fung , Kuan Lun Cheng , Yi-Ming Sheu
IPC分类号： H01L23/62
CPC分类号： H01L29/7843 , H01L21/823814 , H01L21/823835 , H01L29/66636 , H01L29/7848
摘要： A semiconductor device including an isolation region located in a substrate, an NMOS device located partially over a surface of the substrate, and a PMOS device isolated from the NMOS device by the isolation region and located partially over the surface. A first one of the NMOS and PMOS devices includes one of: (1) first source/drain regions recessed within the surface; and (2) first source/drain regions extending from the surface. A second one of the NMOS and PMOS devices includes one of: (1) second source/drain regions recessed within the surface wherein the first source/drain regions extend from the surface; (2) second source/drain regions extending from the surface wherein the first source/drain regions are recessed within the surface; and (3) second source/drain regions substantially coplanar with the surface.
摘要翻译：包括位于衬底中的隔离区域的半导体器件，部分地位于衬底的表面上的NMOS器件以及通过隔离区域与NMOS器件隔离并且部分地位于表面上的PMOS器件。 NMOS和PMOS器件中的第一个包括以下之一：（1）凹陷在表面内的第一源极/漏极区域; 和（2）从表面延伸的第一源极/漏极区域。 NMOS和PMOS器件中的第二个包括以下之一：（1）凹陷在表面内的第二源极/漏极区域，其中第一源极/漏极区域从表面延伸; （2）从表面延伸的第二源极/漏极区域，其中第一源极/漏极区域在表面内凹陷; 和（3）基本上与表面共面的第二源极/漏极区域。

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