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1. 发明授权

US08361854B2 Fin field-effect transistor structure and manufacturing process thereof 有权
标题翻译：鳍场效应晶体管结构及其制造工艺
公开(公告)号：US08361854B2
公开(公告)日：2013-01-29
申请号：US13052338
申请日：2011-03-21
申请人： Teng-Chun Tsai , Chun-Yuan Wu , Chin-Fu Lin , Chih-Chien Liu , Chin-Cheng Chien
发明人： Teng-Chun Tsai , Chun-Yuan Wu , Chin-Fu Lin , Chih-Chien Liu , Chin-Cheng Chien
IPC分类号： H01L21/8238
CPC分类号： H01L29/78 , H01L29/66545 , H01L29/66795 , H01L29/7833
摘要： A fin field-effect transistor structure includes a substrate, a fin channel and a high-k metal gate. The high-k metal gate is formed on the substrate and the fin channel. A process of manufacturing the fin field-effect transistor structure includes the following steps. Firstly, a polysilicon pseudo gate structure is formed on the substrate and a surface of the fin channel. By using the polysilicon pseudo gate structure as a mask, a source/drain region is formed in the fin channel. After the polysilicon pseudo gate structure is removed, a high-k dielectric layer and a metal gate layer are successively formed. Afterwards, a planarization process is performed on the substrate having the metal gate layer until the first dielectric layer is exposed, so that a high-k metal gate is produced.
摘要翻译：鳍状场效应晶体管结构包括衬底，鳍状沟道和高k金属栅极。高k金属栅极形成在基板和鳍状通道上。制造鳍式场效应晶体管结构的工艺包括以下步骤。首先，在基板和散热片通道的表面上形成多晶硅伪栅极结构。通过使用多晶硅伪栅极结构作为掩模，在鳍式沟道中形成源/漏区。在去除多晶硅伪栅极结构之后，依次形成高k电介质层和金属栅极层。然后，在具有金属栅极层的基板上进行平坦化处理，直到第一介电层露出为止，从而产生高k金属栅极。

2. 发明申请

US20120322260A1 THROUGH-SILICON VIA FORMING METHOD 有权
标题翻译：通过形成方法的硅
公开(公告)号：US20120322260A1
公开(公告)日：2012-12-20
申请号：US13161849
申请日：2011-06-16
申请人： Teng-Chun Tsai , Chun-Yuan Wu , Chin-Fu Lin , Chih-Chien Liu , Chin-Cheng Chien
发明人： Teng-Chun Tsai , Chun-Yuan Wu , Chin-Fu Lin , Chih-Chien Liu , Chin-Cheng Chien
IPC分类号： H01L21/283
CPC分类号： H01L21/76898 , H01L21/76883
摘要： A through-silicon via forming method includes the following steps. Firstly, a semiconductor substrate is provided. Then, a through-silicon via conductor is formed in the semiconductor substrate, and a topside of the through-silicon via conductor is allowed to be at the same level as a surface of the semiconductor substrate. Afterwards, a portion of the through-silicon via conductor is removed, and the topside of the through-silicon via conductor is allowed to be at a level lower than the surface of the semiconductor substrate, so that a recess is formed over the through-silicon via conductor.
摘要翻译：通硅通孔形成方法包括以下步骤。首先，提供半导体衬底。然后，在半导体衬底中形成贯通硅通孔导体，并且使贯通硅通孔导体的上侧与半导体衬底的表面处于相同的水平。然后，去除一部分通硅导通导体，使贯通硅通孔导体的顶面位于比半导体衬底的表面低的水平面上，硅通孔导体。

3. 发明申请

US20120115284A1 METHOD FOR MANUFACTURING MULTI-GATE TRANSISTOR DEVICE 有权
标题翻译：制造多栅极晶体管器件的方法
公开(公告)号：US20120115284A1
公开(公告)日：2012-05-10
申请号：US12943015
申请日：2010-11-10
申请人： Chin-Cheng Chien , Chun-Yuan Wu , Chih-Chien Liu , Chin-Fu Lin , Teng-Chun Tsai
发明人： Chin-Cheng Chien , Chun-Yuan Wu , Chih-Chien Liu , Chin-Fu Lin , Teng-Chun Tsai
IPC分类号： H01L21/336
CPC分类号： H01L29/66795
摘要： A method for manufacturing a multi-gate transistor device includes providing a semiconductor substrate having a first patterned semiconductor layer formed thereon, sequentially forming a gate dielectric layer and a gate layer covering a portion of the first patterned semiconductor layer on the semiconductor substrate, removing a portion of the first patterned semiconductor layer to form a second patterned semiconductor layer, and performing a selective epitaxial growth process to form an epitaxial layer on a surface of the second patterned semiconductor layer.
摘要翻译：一种制造多栅极晶体管器件的方法包括：提供其上形成有第一图案化半导体层的半导体衬底，顺序地形成栅极电介质层和覆盖半导体衬底上的第一图案化半导体层的一部分的栅极层，以形成第二图案化半导体层，并且执行选择性外延生长工艺以在第二图案化半导体层的表面上形成外延层。

4. 发明授权

US08551829B2 Method for manufacturing multi-gate transistor device 有权
标题翻译：多栅极晶体管器件制造方法
公开(公告)号：US08551829B2
公开(公告)日：2013-10-08
申请号：US12943015
申请日：2010-11-10
申请人： Chin-Cheng Chien , Chun-Yuan Wu , Chih-Chien Liu , Chin-Fu Lin , Teng-Chun Tsai
发明人： Chin-Cheng Chien , Chun-Yuan Wu , Chih-Chien Liu , Chin-Fu Lin , Teng-Chun Tsai
IPC分类号： H01L21/00 , H01L21/84 , H01L21/70
CPC分类号： H01L29/66795
摘要： A method for manufacturing a multi-gate transistor device includes providing a semiconductor substrate having a first patterned semiconductor layer formed thereon, sequentially forming a gate dielectric layer and a gate layer covering a portion of the first patterned semiconductor layer on the semiconductor substrate, removing a portion of the first patterned semiconductor layer to form a second patterned semiconductor layer, and performing a selective epitaxial growth process to form an epitaxial layer on a surface of the second patterned semiconductor layer.
摘要翻译：一种制造多栅极晶体管器件的方法包括：提供其上形成有第一图案化半导体层的半导体衬底，顺序地形成栅极电介质层和覆盖半导体衬底上的第一图案化半导体层的一部分的栅极层，以形成第二图案化半导体层，并且执行选择性外延生长工艺以在第二图案化半导体层的表面上形成外延层。

5. 发明申请

US20130193585A1 Fabrication method and structure of through silicon via 有权
公开(公告)号：US20130193585A1
公开(公告)日：2013-08-01
申请号：US13363390
申请日：2012-02-01
申请人： Chin-Fu Lin , Chun-Yuan Wu , Chih-Chien Liu , Teng-Chun Tsai , Chin-Cheng Chien
发明人： Chin-Fu Lin , Chun-Yuan Wu , Chih-Chien Liu , Teng-Chun Tsai , Chin-Cheng Chien
IPC分类号： H01L23/48 , H01L21/302
CPC分类号： H01L21/3085 , H01L21/3086 , H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a through silicon via (TSV) structure, in which, a patterned mask is formed on a substrate, the patterned mask has an opening, a spacer-shaped structure is formed on a sidewall of the opening, and a via hole having a relatively enlarged opening is formed by etching the spacer-shaped structure and the substrate through the opening after the spacer-shaped structure is formed. A TSV structure, in which, a via hole has an opening portion and a body portion, the opening portion is a relatively enlarged opening and has a tapered shape having an opening size of an upper portion greater than an opening size of a lower portion.

6. 发明申请

US20130078780A1 SEMICONDUCTOR PROCESS 审中-公开
标题翻译：半导体工艺
公开(公告)号：US20130078780A1
公开(公告)日：2013-03-28
申请号：US13241188
申请日：2011-09-22
申请人： Chin-Fu Lin , Chih-Chien Liu , Teng-Chun Tsai , Chin-Cheng Chien , Chun-Yuan Wu
发明人： Chin-Fu Lin , Chih-Chien Liu , Teng-Chun Tsai , Chin-Cheng Chien , Chun-Yuan Wu
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L21/28229 , H01L29/517 , H01L29/78
摘要： A semiconductor process includes the following steps. An interlayer is formed on a substrate. A first metallic oxide layer is formed on the interlayer. A reduction process is performed to reduce the first metallic oxide layer into a metal layer. A high temperature process is performed to transform the metal layer to a second metallic oxide layer.
摘要翻译：半导体工艺包括以下步骤。在基板上形成中间层。在中间层上形成第一金属氧化物层。进行还原处理以将第一金属氧化物层还原成金属层。执行高温处理以将金属层转变为第二金属氧化物层。

7. 发明授权

US09184100B2 Semiconductor device having strained fin structure and method of making the same 有权
标题翻译：具有应变翅片结构的半导体器件及其制造方法
公开(公告)号：US09184100B2
公开(公告)日：2015-11-10
申请号：US13206533
申请日：2011-08-10
申请人： Teng-Chun Tsai , Chun-Yuan Wu , Chih-Chien Liu , Chin-Cheng Chien , Chin-Fu Lin
发明人： Teng-Chun Tsai , Chun-Yuan Wu , Chih-Chien Liu , Chin-Cheng Chien , Chin-Fu Lin
IPC分类号： H01L27/092 , H01L21/84 , H01L21/8238 , H01L27/12 , H01L29/10
CPC分类号： H01L21/845 , H01L21/823821 , H01L27/0924 , H01L27/1211 , H01L29/1054 , H01L29/165
摘要： A semiconductor device includes a semiconductor substrate, at least a first fin structure, at least a second fin structure, a first gate, a second gate, a first source/drain region and a second source/drain region. The semiconductor substrate has at least a first active region to dispose the first fin structure and at least a second active region to dispose the second fin structure. The first/second fin structure partially overlapped by the first/second gate has a first/second stress, and the first stress and the second stress are different from each other. The first/second source/drain region is disposed in the first/second fin structure at two sides of the first/second gate.
摘要翻译：半导体器件包括半导体衬底，至少第一鳍结构，至少第二鳍结构，第一栅极，第二栅极，第一源极/漏极区域和第二源极/漏极区域。半导体衬底至少具有第一有源区以配置第一鳍结构和至少第二有源区以配置第二鳍结构。与第一/第二栅极部分重叠的第一/第二鳍结构具有第一/第二应力，第一应力和第二应力彼此不同。第一/第二源极/漏极区域设置在第一/第二栅极的两侧的第一/第二鳍结构中。

8. 发明授权

US08822336B2 Through-silicon via forming method 有权
标题翻译：通硅成型方法
公开(公告)号：US08822336B2
公开(公告)日：2014-09-02
申请号：US13161849
申请日：2011-06-16
申请人： Teng-Chun Tsai , Chun-Yuan Wu , Chin-Fu Lin , Chih-Chien Liu , Chin-Cheng Chien
发明人： Teng-Chun Tsai , Chun-Yuan Wu , Chin-Fu Lin , Chih-Chien Liu , Chin-Cheng Chien
IPC分类号： H01L21/283
CPC分类号： H01L21/76898 , H01L21/76883
摘要： A through-silicon via forming method includes the following steps. Firstly, a semiconductor substrate is provided. Then, a through-silicon via conductor is formed in the semiconductor substrate, and a topside of the through-silicon via conductor is allowed to be at the same level as a surface of the semiconductor substrate. Afterwards, a portion of the through-silicon via conductor is removed, and the topside of the through-silicon via conductor is allowed to be at a level lower than the surface of the semiconductor substrate, so that a recess is formed over the through-silicon via conductor.
摘要翻译：通硅通孔形成方法包括以下步骤。首先，提供半导体衬底。然后，在半导体衬底中形成贯通硅通孔导体，并且使贯通硅通孔导体的上侧与半导体衬底的表面处于相同的水平。然后，去除一部分通硅导通导体，使贯通硅通孔导体的顶面位于比半导体衬底的表面低的水平面上，硅通孔导体。

9. 发明申请

US20130078778A1 SEMICONDUCTOR PROCESS 有权
标题翻译：半导体工艺
公开(公告)号：US20130078778A1
公开(公告)日：2013-03-28
申请号：US13243485
申请日：2011-09-23
申请人： Chin-Cheng Chien , Chun-Yuan Wu , Chih-Chien Liu , Chin-Fu Lin , Teng-Chun Tsai
发明人： Chin-Cheng Chien , Chun-Yuan Wu , Chih-Chien Liu , Chin-Fu Lin , Teng-Chun Tsai
IPC分类号： H01L21/336
CPC分类号： H01L29/66795
摘要： A semiconductor process is described as follows. A plurality of dummy patterns is formed on a substrate. A mask material layer is conformally formed on the substrate, so as to cover the dummy patterns. The mask material layer has an etching rate different from that of the dummy patterns. A portion of the mask material layer is removed, so as to form a mask layer on respective sidewalls of each dummy pattern. An upper surface of the mask layer and an upper surface of each dummy pattern are substantially coplanar. The dummy patterns are removed. A portion of the substrate is removed using the mask layer as a mask, so as to form a plurality of fin structures and a plurality of trenches alternately arranged in the substrate. The mask layer is removed.
摘要翻译：半导体工艺描述如下。在基板上形成多个虚设图案。在基板上共形形成掩模材料层，以覆盖虚设图案。掩模材料层具有与虚拟图案不同的蚀刻速率。除去掩模材料层的一部分，以便在每个虚设图案的各个侧壁上形成掩模层。掩模层的上表面和每个虚拟图案的上表面基本上共面。虚拟图案被去除。使用掩模层作为掩模去除衬底的一部分，以便形成多个翅片结构和交替布置在衬底中的多个沟槽。去除掩模层。

10. 发明申请

US20130056827A1 NON-PLANAR SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF 有权
标题翻译：非平面半导体结构及其制造方法
公开(公告)号：US20130056827A1
公开(公告)日：2013-03-07
申请号：US13224344
申请日：2011-09-02
申请人： Shih-Hung Tsai , Chien-Ting Lin , Chin-Cheng Chien , Chin-Fu Lin , Chih-Chien Liu , Teng-Chun Tsai , Chun-Yuan Wu
发明人： Shih-Hung Tsai , Chien-Ting Lin , Chin-Cheng Chien , Chin-Fu Lin , Chih-Chien Liu , Teng-Chun Tsai , Chun-Yuan Wu
IPC分类号： H01L21/84 , H01L27/12 , H01L21/336 , H01L29/78
CPC分类号： H01L29/785 , H01L29/66795
摘要： A non-planar semiconductor structure includes a substrate, at least two fin-shaped structures, at least an isolation structure, and a plurality of epitaxial layers. The fin-shaped structures are located on the substrate. The isolation structure is located between the fin-shaped structures, and the isolation structure has a nitrogen-containing layer. The epitaxial layers respectively cover a part of the fin-shaped structures and are located on the nitrogen-containing layer. A non-planar semiconductor process is also provided for forming the semiconductor structure.
摘要翻译：非平面半导体结构包括衬底，至少两个鳍状结构，至少一个隔离结构和多个外延层。鳍状结构位于基底上。隔离结构位于鳍状结构之间，隔离结构具有含氮层。外延层分别覆盖了鳍状结构的一部分并且位于含氮层上。还提供了用于形成半导体结构的非平面半导体工艺。

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