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1. 发明申请

US20110149286A1 LIQUID CORE WAVEGUIDE ASSEMBLY AND DETECTING SYSTEM INCLUDING THE SAME 审中-公开
标题翻译：液体波导组件和包括其的检测系统
公开(公告)号：US20110149286A1
公开(公告)日：2011-06-23
申请号：US12642640
申请日：2009-12-18
申请人： Chih-Wei Wu , Ting-I Wu , Wei-Han Chen
发明人： Chih-Wei Wu , Ting-I Wu , Wei-Han Chen
IPC分类号： G01N21/00 , G02B6/032 , G02B6/10
CPC分类号： G02B6/032 , G01N21/0303 , G01N21/05 , G01N21/31 , G01N21/78 , G01N2021/0325 , G01N2021/0346 , G01N2021/052 , G01N2201/062 , G01N2201/08 , G02B6/10
摘要： A liquid core waveguide assembly includes: a waveguide-forming body formed with a waveguide channel and first and second fiber channels, transparent first and second partition walls, and a liquid inlet in fluid communication with the waveguide channel, the waveguide channel having a first end spaced apart from the first fiber channel by the first partition wall, and a second end spaced apart from the second fiber channel by the second partition wall; and at least one first optical fiber and at least one second optical fiber extending into the first and second fiber channels, respectively. A detecting system including the liquid core waveguide assembly is also disclosed.
摘要翻译：液芯波导组件包括：形成有波导通道和第一和第二光纤通道的波导形成体，透明的第一和第二分隔壁以及与波导通道流体连通的液体入口，波导通道具有第一端通过第一分隔壁与第一纤维通道间隔开，以及通过第二分隔壁与第二纤维通道间隔开的第二端; 以及分别延伸到第一和第二光纤通道中的至少一个第一光纤和至少一个第二光纤。还公开了一种包括液芯波导组件的检测系统。

2. 发明申请

US20170168208A1 FLUORESCENT LED BACKLIGHT PLATE ASSEMBLY 审中-公开
公开(公告)号：US20170168208A1
公开(公告)日：2017-06-15
申请号：US14967347
申请日：2015-12-13
申请人： Chih-Wei Wu
发明人： Chih-Wei Wu
IPC分类号： F21V8/00
CPC分类号： G02B6/005 , G02B6/0003 , G02B6/0055 , G02B6/0068
摘要： A fluorescent LED backlight plate assembly includes: at least one LED bar containing blue LED light sources; a light guide plate aside the LED light bar; a light reflecting sheet below the light guide plate; a light processing module located above the light guide plate; the light processing module containing a plurality of light processing plates and a fluorescent plate containing green and red fluorescent material. When red fluorescent and green fluorescent materials are stimulated, they emit red and green lights, so that light intensity is enhanced. Thus, when these light further passes through an LCD panel, they will present high light intensity and saturation. In another embodiment, no fluorescent plate is used, while fluorescent materials are added to the light guide plate or the light processing plates. The fluorescent materials contain red and green fluorescent materials.

3. 发明授权

US08580683B2 Apparatus and methods for molding die on wafer interposers 有权
标题翻译：用于在晶片插入件上成型模具的装置和方法
公开(公告)号：US08580683B2
公开(公告)日：2013-11-12
申请号：US13246556
申请日：2011-09-27
申请人： Chung Yu Wang , Chih-Wei Wu , Szu Wei Lu , Jing-Cheng Lin
发明人： Chung Yu Wang , Chih-Wei Wu , Szu Wei Lu , Jing-Cheng Lin
IPC分类号： H01L23/28
CPC分类号： H01L21/78 , H01L21/561 , H01L23/16 , H01L23/3128 , H01L23/562 , H01L24/13 , H01L24/16 , H01L25/0655 , H01L2224/13111 , H01L2224/16238 , H01L2224/32225 , H01L2224/73204 , H01L2224/81191 , H01L2224/81815 , H01L2924/01322 , H01L2924/12042 , H01L2924/15311 , H01L2924/157 , H01L2924/18161 , H01L2924/3511 , H01L2224/16225 , H01L2924/00012 , H01L2924/00 , H01L2924/00014 , H01L2924/01047 , H01L2924/01029
摘要： Methods and apparatus for performing molding on die on wafer interposers. A method includes receiving an interposer assembly having a die side and an opposite side including two or more integrated circuit dies mounted on the die side of the interposer, the interposer assembly having spaces formed on the die side of the interposer between the two or more integrated circuit dies; mounting at least one stress relief feature on the die side of the interposer assembly in one of the spaces between the two or more integrated circuit dies; and molding the integrated circuit dies using a mold compound, the mold compound surrounding the two or more integrated circuit dies and the at least one stress relief feature. An apparatus is disclosed having integrated circuits mounted on a die side of an interposer, stress relief features between the integrated circuits and mold compound over the integrated circuits.
摘要翻译：用于在晶片插入件上的模具上进行模制的方法和装置。一种方法包括接收具有管芯侧面和相对侧的插入件组件，所述插入件组件包括安装在所述插入件的裸片侧上的两个或多个集成电路管芯，所述插入器组件具有形成在所述插入件的裸片侧上的两个或更多个集成电路模具; 在所述两个或更多个集成电路管芯之间的空间之一中在所述插入器组件的管芯侧上安装至少一个应力释放特征; 以及使用模具化合物模制所述集成电路模具，围绕所述两个或更多个集成电路管芯的所述模具化合物以及所述至少一个应力释放特征。公开了一种装置，其集成电路安装在插入件的裸片侧，集成电路之间的应力消除特征和集成电路上的模具化合物。

4. 发明授权

US08501590B2 Apparatus and methods for dicing interposer assembly 有权
标题翻译：用于切割插件组件的装置和方法
公开(公告)号：US08501590B2
公开(公告)日：2013-08-06
申请号：US13176606
申请日：2011-07-05
申请人： Chung Yu Wang , Kung-Chen Yeh , Chih-Wei Wu , Szu Wei Lu , Jing-Cheng Lin
发明人： Chung Yu Wang , Kung-Chen Yeh , Chih-Wei Wu , Szu Wei Lu , Jing-Cheng Lin
IPC分类号： H01L21/78
CPC分类号： H01L23/58 , H01L21/486 , H01L21/673 , H01L21/6835 , H01L21/6836 , H01L23/147 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/5384 , H01L24/97 , H01L25/0655 , H01L2221/68331 , H01L2221/68381 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/97 , H01L2924/01322 , H01L2924/15311 , H01L2924/157 , H01L2924/15787 , H01L2924/15788 , H01L2924/351 , H01L2224/81 , H01L2224/83 , H01L2924/00
摘要： Methods and apparatus for performing dicing of die on wafer interposers. Methods are disclosed that include receiving an interposer assembly including one or more integrated circuit dies mounted on a die side of an interposer substrate and having scribe areas defined in spaces between the integrated circuit dies, the interposer having an opposite side for receiving external connectors; mounting the die side of the interposer assembly to a tape assembly, the tape assembly comprising an adhesive tape and preformed spacers disposed between and filling gaps between the integrated circuit dies; and sawing the interposer assembly by cutting the opposite side of the interposer in the scribe areas to make cuts through the interposer, the cuts separating the interposer into one or more die on wafer assemblies. Apparatuses are disclosed for use with the methods.
摘要翻译：用于在晶片插入件上进行裸片切割的方法和装置。公开了包括接收包括安装在插入器基板的裸片侧上的一个或多个集成电路管芯并且在集成电路管芯之间的空间中限定的划线区域的插入件组件的方法，所述插入器具有用于接收外部连接器的相对侧; 将所述插入器组件的模具侧安装到带组件上，所述带组件包括粘合带和设置在所述集成电路管芯之间的填充间隙之间的预成型间隔件; 以及通过在所述划线区域中切割所述插入件的相对侧来切割所述插入件组件，以切割所述插入件，所述切口将所述插入件分离成晶片组件上的一个或多个模具。公开了与该方法一起使用的装置。

5. 发明授权

US07851895B2 Semiconductor structure and semiconductor manufacturing method 有权
标题翻译：半导体结构和半导体制造方法
公开(公告)号：US07851895B2
公开(公告)日：2010-12-14
申请号：US12222200
申请日：2008-08-05
申请人： Chih Yi Huang , Chih-Wei Wu
发明人： Chih Yi Huang , Chih-Wei Wu
IPC分类号： H01L29/40 , H01L23/04 , H01L23/12 , H01L21/4763
CPC分类号： H01L23/66 , H01L24/48 , H01L2223/6616 , H01L2223/6627 , H01L2224/48235 , H01L2924/00014 , H01L2924/1903 , H01L2924/19041 , H01L2924/3025 , H01P3/08 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor structure comprising a first signal layer, a second signal layer, a wiring layer and at least one via is provided. The wiring layer is formed between the first signal layer and the second signal layer. A conducting wire is disposed between a first terminal and a second terminal on the wiring layer. At least one via is used to conduct the first signal layer and the second signal layer. The at least one via is disposed adjacent to the first terminal and the second terminal.
摘要翻译：提供包括第一信号层，第二信号层，布线层和至少一个通孔的半导体结构。布线层形成在第一信号层和第二信号层之间。导线布置在布线层上的第一端子和第二端子之间。使用至少一个通孔来传导第一信号层和第二信号层。所述至少一个通孔设置成与所述第一端子和所述第二端子相邻。

6. 发明申请

US20080265389A1 Substrate for multi-chip stacking, multi-chip stack package utilizing the substrate and its applications 失效
标题翻译：用于多芯片堆叠的基板，利用基板的多芯片堆叠封装及其应用
公开(公告)号：US20080265389A1
公开(公告)日：2008-10-30
申请号：US11790826
申请日：2007-04-27
申请人： Hung-Hsin Hsu , Chih-Wei Wu
发明人： Hung-Hsin Hsu , Chih-Wei Wu
IPC分类号： H01L23/02
CPC分类号： H01L23/49838 , H01L23/3121 , H01L23/5382 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0657 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48095 , H01L2224/48195 , H01L2224/48227 , H01L2224/48228 , H01L2224/49113 , H01L2224/73265 , H01L2225/0651 , H01L2225/06527 , H01L2225/06575 , H01L2924/00014 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599
摘要： A substrate for multi-chip stacking and a multi-chip stack package utilizing the substrate and its applications are disclosed. The substrate comprises a first wire-bonding finger, a second wire-bonding finger, a trace configured for electrical transmission and a loop wiring on a same surface. The first wire-bonding finger and the second wire-bonding finger are adjacent each other and to a die-attaching area of the substrate. The loop wiring connects the first wire-bonding finger with the second wire-bonding finger in series and connected to the trace. The loop wiring can be selectively broken or not when at least two chips are stacked on the die-attaching area and electrically connected to the first and second wire-bonding fingers respectively. Accordingly, the chips can operate respectively and independently without mutual interference if one of the chips is fail. Moreover, there is merit to apply the multi-chip stack package utilizing the substrate because it can be repaired after molding and without removing any bonding wire during semiconductor packaging processes.
摘要翻译：公开了一种用于多芯片堆叠的基板和利用该基板及其应用的多芯片堆叠封装。基板包括第一引线接合指状物，第二引线键合指状物，构造成用于电传输的迹线和在同一表面上的环形布线。第一引线接合指和第二引线接合指彼此相邻并且与基板的管芯附接区相邻。环路布线将第一引线接合指状物与第二引线键合指针串联连接并连接至迹线。当至少两个芯片堆叠在芯片安装区域上并且分别电连接到第一和第二引线键合手指时，环路布线可以选择性地断开。因此，如果其中一个芯片发生故障，则芯片可以分别且独立地操作而没有相互干扰。此外，由于可以在模制之后修复并且在半导体封装工艺期间不去除任何接合线，所以应用使用基板的多芯片堆叠封装是有价值的。

7. 发明申请

US20080218961A1 HEAT DISSIPATION MODULE AND DESKTOP HOST USING THE SAME 审中-公开
标题翻译：散热模块和桌面使用相同
公开(公告)号：US20080218961A1
公开(公告)日：2008-09-11
申请号：US11747232
申请日：2007-05-11
申请人： Chih-Wei Wu , Chia-Yi Chang
发明人： Chih-Wei Wu , Chia-Yi Chang
IPC分类号： H05K7/20
CPC分类号： G06F1/20 , G06F2200/201
摘要： A heat dissipation module suitable for a desktop host includes a case, a power supply with a fan, and a mother board. The power supply and the mother board are disposed in the case. The mother board includes a work components. The heat dissipation module includes a first heat sink, a second heat sink and a heat pipe. The first heat sink is disposed on the work components. The second heat sink is disposed outside the case and at the outlet port of the fan. The heat pipe is connected between the first heat sink and the second heat sink. Hence, the heat dissipation module can dissipate the heat generated by the work component.
摘要翻译：适用于桌面主机的散热模块包括外壳，带风扇的电源和母板。电源和母板设置在外壳中。母板包括一个工作部件。散热模块包括第一散热器，第二散热器和热管。第一散热器设置在工件上。第二散热器设置在壳体外部和风扇的出口处。热管连接在第一散热器和第二散热器之间。因此，散热模块可以消散由工件所产生的热量。

8. 发明申请

US20080099175A1 Method for in-gas micro/nanoimprinting of bulk metallic glass 审中-公开
标题翻译：散装金属玻璃的气体微/纳米压印方法
公开(公告)号：US20080099175A1
公开(公告)日：2008-05-01
申请号：US11790860
申请日：2007-04-27
申请人： Jinn P. Chu , Hadi Wijaya , Chun-Ling Chiang , Chih-Wei Wu
发明人： Jinn P. Chu , Hadi Wijaya , Chun-Ling Chiang , Chih-Wei Wu
IPC分类号： B22D25/02
CPC分类号： B22D17/2245 , B22D21/00 , C22C45/00
摘要： A method for in-gas micro/nanoimprinting of bulk metallic glass includes steps of preparing a die, heating the bulk metallic glass and in-gas micro/nanoimprinting of the bulk metallic glass. In the step of preparing a die, the die has a micro/nano structure having multiple depressions and a flow channel connected to the depressions. In the step of heating the bulk metallic glass, the bulk metallic glass is heated to a temperature between a glass transition temperature and a crystallization temperature of the bulk metallic glass. In the step of in-gas micro/nanoimprinting, the bulk metallic glass is forced into the die in presence of gas to imprint a complementing micro/nano structure on the bulk metallic glass. Because the die has a flow channel to allow air or gas to escape from the micro/nano structure of the die, the micro/nanoimprinting can be performed in presence of air or gas.
摘要翻译：本体金属玻璃的气体微/纳米压印的方法包括制备模具，加热块体金属玻璃和散装金属玻璃的气体微/纳米压印的步骤。在制备模具的步骤中，模头具有具有多个凹陷的微/纳米结构和与凹陷相连的流动通道。在加热块状金属玻璃的步骤中，将块状金属玻璃加热至玻璃化转变温度和块状金属玻璃的结晶温度之间的温度。在气体微/纳米压印的步骤中，在存在气体的情况下将大块金属玻璃强制进入模具，以在体金属玻璃上印刷互补的微/纳米结构。因为模具具有允许空气或气体从模具的微/纳米结构逸出的流动通道，所以微/纳米压印可以在存在空气或气体的情况下进行。

9. 发明申请

US20050179659A1 Mouse device 审中-公开
标题翻译：鼠标设备
公开(公告)号：US20050179659A1
公开(公告)日：2005-08-18
申请号：US11060115
申请日：2005-02-17
申请人： Chun-Hsiung Yin , Hsun-Li Huang , Chih-Wei Wu
发明人： Chun-Hsiung Yin , Hsun-Li Huang , Chih-Wei Wu
IPC分类号： G06F3/033 , G09G5/08
CPC分类号： G06F3/03543 , G06F2203/0333
摘要： A mouse device includes a mouse body and a scrolling wheel. The mouse body has a front curved surface, a rear curved surface and a bottom. The bevel and a rear edge of the front curved surface are respectively connected to the bottom and the rear curved surface. The included angle of the front curved surface and the bottom is between 45 and 70 degrees. The scrolling wheel is disposed on the bevel. When operating the mouse device, the user uses an index finger and a portion connecting the index finger and the palm to form an arch atop of the front curved surface and the rear curved surface, thus the mouse body is largely under the index finger. The user can tilt the mouse body for the first scrolling wheel to contact with a working surface and scroll a monitor's screen frame.
摘要翻译：鼠标装置包括鼠标主体和滚动轮。鼠标体具有前弯曲表面，后曲面和底部。前曲面的斜面和后边缘分别连接到底部和后部曲面。前曲面和底部的夹角在45度和70度之间。滚动轮设置在斜面上。当操作鼠标装置时，用户使用食指和连接食指和手掌的部分在前曲面和后曲面的顶部形成拱形，因此鼠标主体在食指之下。用户可以使第一滚动滚轮的鼠标主体倾斜以与工作表面接触并滚动显示器的屏幕框架。

10. 发明授权

US08541883B2 Semiconductor device having shielded conductive vias 有权
标题翻译：具有屏蔽导电通孔的半导体器件
公开(公告)号：US08541883B2
公开(公告)日：2013-09-24
申请号：US13306762
申请日：2011-11-29
申请人： Hung-Hsiang Cheng , Tzu-Chih Lin , Chang-Ying Hung , Chih-Wei Wu
发明人： Hung-Hsiang Cheng , Tzu-Chih Lin , Chang-Ying Hung , Chih-Wei Wu
IPC分类号： H01L29/40
CPC分类号： H01L21/76898 , H01L23/147 , H01L23/3192 , H01L23/481 , H01L23/49816 , H01L23/49827 , H01L23/66 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/14 , H01L24/16 , H01L2224/02372 , H01L2224/0401 , H01L2224/05008 , H01L2224/05569 , H01L2224/05572 , H01L2224/05599 , H01L2224/06181 , H01L2224/13022 , H01L2224/13099 , H01L2224/14181 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2924/00013 , H01L2924/00014 , H01L2224/05099 , H01L2224/05552
摘要： The present invention relates to a semiconductor device having a shielding layer. The semiconductor device includes a substrate, an inner metal layer, a shielding layer, an insulation material, a metal layer, a passivation layer and a redistribution layer. The inner metal layer is disposed in a through hole of the substrate. The shielding layer surrounds the inner annular metal. The insulation material is disposed between the inner metal layer and the shielding layer. The metal layer is disposed on a surface of the substrate, contacts the shielding layer and does not contact the inner metal layer. The redistribution layer is disposed in an opening of the passivation layer so as to contact the inner metal layer.
摘要翻译：本发明涉及一种具有屏蔽层的半导体器件。半导体器件包括衬底，内金属层，屏蔽层，绝缘材料，金属层，钝化层和再分配层。内金属层设置在基板的通孔中。屏蔽层围绕内环形金属。绝缘材料设置在内金属层和屏蔽层之间。金属层设置在基板的表面上，与屏蔽层接触并且不接触内部金属层。再分配层设置在钝化层的开口中以与内金属层接触。

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