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1. 发明申请

US20120195139A1 MULTI-POWER DOMAIN DESIGN 有权
标题翻译：多功能域设计
公开(公告)号：US20120195139A1
公开(公告)日：2012-08-02
申请号：US13443619
申请日：2012-04-10
申请人： Hsu-Shun CHEN , Cheng Hung LEE , Chung-Ji LU , Hong-Chen CHENG , Chung-Yi WU , Chih-Chieh CHIU
发明人： Hsu-Shun CHEN , Cheng Hung LEE , Chung-Ji LU , Hong-Chen CHENG , Chung-Yi WU , Chih-Chieh CHIU
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G11C7/1048 , G11C5/14
摘要： In some embodiments related to a memory array, a sense amplifier (SA) uses a first power supply, e.g., voltage VDDA, while other circuitry, e.g., signal output logic, uses a second power supply, e.g., voltage VDDB. Various embodiments place the SA and a pair of transferring devices at a local IO row, and a voltage keeper at the main IO section of the same memory array. The SA, the transferring devices, and the voltage keeper, when appropriate, operate together so that the data logic of the circuitry provided by voltage VDDB is the same as the data logic of the circuitry provided by voltage VDDA.
摘要翻译：在与存储器阵列相关的一些实施例中，读出放大器（SA）使用第一电源，例如电压VDDA，而其它电路（例如，信号输出逻辑）使用第二电源，例如电压VDDB。各种实施例将SA和一对传送装置放置在本地IO行上，并将电压保持器放置在同一存储器阵列的主IO部分。 SA，传输装置和电压保持器在适当的情况下一起工作，使得由电压VDDB提供的电路的数据逻辑与由电压VDDA提供的电路的数据逻辑相同。

2. 发明申请

US20110090753A1 POWER MANAGEMENT 有权
标题翻译：能源管理
公开(公告)号：US20110090753A1
公开(公告)日：2011-04-21
申请号：US12885826
申请日：2010-09-20
申请人： Cheng Hung LEE , Chung-Yi WU , Hsu-Shun CHEN , Chung-Ji LU
发明人： Cheng Hung LEE , Chung-Yi WU , Hsu-Shun CHEN , Chung-Ji LU
IPC分类号： G11C5/14
CPC分类号： G11C11/413
摘要： An SRAM includes circuitry configured for the SRAM to operate at different operation modes using different voltage levels wherein the voltage level and thus the supply current leakage is regulated based on the operation mode. For example, the SRAM, in a normal operation mode, consumes power as other SRAMs. In a deep sleep mode the supply voltage (e.g., VDDI) for the bit cell in the SRAM macro is lowered by about 20-40% of the SRAM supply voltage (e.g., VDD), sufficient to retain the data in the bit cell. When access to the SRAM is not needed, the SRAM operates in the sleep mode, consuming little or no power.
摘要翻译： SRAM包括被配置用于使用不同的电压电平在不同的操作模式下工作的电路，其中基于操作模式调节电压电平和因此的电流泄漏。例如，在正常工作模式下，SRAM将作为其他SRAM消耗电力。在深度睡眠模式下，SRAM宏中的位单元的电源电压（例如，VDDI）降低SRAM电源电压（例如VDD）的约20-40％，足以将数据保留在位单元中。当不需要访问SRAM时，SRAM在睡眠模式下运行，消耗很少或没有电源。

3. 发明申请

US20120106286A1 MEMORY CIRCUIT HAVING DECODING CIRCUITS AND METHOD OF OPERATING THE SAME 有权
标题翻译：具有解码电路的存储器电路及其操作方法
公开(公告)号：US20120106286A1
公开(公告)日：2012-05-03
申请号：US12912971
申请日：2010-10-27
申请人： Cheng Hung LEE , Hsu-Shun CHEN
发明人： Cheng Hung LEE , Hsu-Shun CHEN
IPC分类号： G11C8/10 , G11C8/06 , G11C8/12
CPC分类号： G11C8/10 , G11C11/418
摘要： The present application discloses a memory circuit having a first decoder coupled to a first memory bank and configured to receive a plurality of address control signals and to generate a first plurality of cell selection signals responsive to the plurality of address control signals and a second decoder coupled to a second memory bank and configured to receive a plurality of inverted address control signals and to generate a second plurality of cell selection signals responsive to the plurality of inverted address control signals. The memory circuit also has an address control signal buffer coupled to the second decoder and configured to convert the plurality of address control signals into the plurality of inverted address control signals.
摘要翻译：本申请公开了一种存储器电路，其具有耦合到第一存储体并被配置为接收多个地址控制信号并且响应于多个地址控制信号产生第一多个小区选择信号的第一解码器，耦合到第二存储体并且被配置为接收多个反相地址控制信号，并响应于所述多个反相地址控制信号产生第二多个单元选择信号。存储器电路还具有耦合到第二解码器的地址控制信号缓冲器，并且被配置为将多个地址控制信号转换成多个反相地址控制信号。

4. 发明申请

US20140269110A1 ASYMMETRIC SENSING AMPLIFIER, MEMORY DEVICE AND DESIGNING METHOD 有权
标题翻译：不对称感应放大器，存储器件和设计方法
公开(公告)号：US20140269110A1
公开(公告)日：2014-09-18
申请号：US13837614
申请日：2013-03-15
申请人： Jung-Ping YANG , Chia-En HUANG , Fu-An WU , Chih-Chieh CHIU , Cheng Hung LEE
发明人： Jung-Ping YANG , Chia-En HUANG , Fu-An WU , Chih-Chieh CHIU , Cheng Hung LEE
IPC分类号： G11C7/06 , G06F17/50
CPC分类号： G11C7/065 , G06F17/5063 , G06F17/5081 , G11C7/1048 , G11C7/12 , G11C11/419
摘要： A sensing amplifier for a memory device includes first and second nodes, an input device and an output device. The memory device includes first and second bit lines, and at least one memory cell coupled to the bit lines. The first and second nodes are coupled to the first and second bit lines, respectively. The input device is coupled to the first and second nodes and generates a first current pulling the first node toward a predetermined voltage in response to a first datum read out from the memory cell, and to generate a second current pulling the second node toward the predetermined voltage in response to a second datum read out from the memory cell. The output device is coupled to the first node to output the first or second datum read out from the memory cell. The first current is greater than the second current.
摘要翻译：用于存储器件的感测放大器包括第一和第二节点，输入设备和输出设备。存储器件包括第一和第二位线，以及耦合到位线的至少一个存储器单元。第一和第二节点分别耦合到第一和第二位线。输入设备耦合到第一和第二节点，并且响应于从存储器单元读出的第一数据产生第一电流将第一节点拉向预定电压，并且产生将第二节点拉向预定的第二电流的第二电流响应于从存储器单元读出的第二数据的电压。输出设备耦合到第一节点以输出从存储器单元读出的第一或第二数据。第一个电流大于第二个电流。

5. 发明申请

US20130208533A1 MEMORY HAVING READ ASSIST DEVICE AND METHOD OF OPERATING THE SAME 有权
标题翻译：具有读取辅助装置的存储器及其操作方法
公开(公告)号：US20130208533A1
公开(公告)日：2013-08-15
申请号：US13372099
申请日：2012-02-13
申请人： Jung-Ping YANG , Hong-Chen CHENG , Chih-Chieh CHIU , Chia-En HUANG , Cheng Hung LEE
发明人： Jung-Ping YANG , Hong-Chen CHENG , Chih-Chieh CHIU , Chia-En HUANG , Cheng Hung LEE
IPC分类号： G11C11/40 , G11C7/12 , G11C7/00
CPC分类号： G11C11/4094 , G11C11/419
摘要： A memory includes a first bit line, a memory cell coupled to the first bit line, and a read assist device coupled to the first bit line. The read assist device is configured to pull a first voltage on the first bit line toward a predetermined voltage in response to a first datum being read out from the memory cell. The read assist device includes a first circuit configured to establish a first current path between the first bit line and a node of the predetermined voltage during a first stage. The read assist device further includes a second circuit configured to establish a second current path between the first bit line and the node of the predetermined voltage during a second, subsequent stage.
摘要翻译：存储器包括第一位线，耦合到第一位线的存储器单元和耦合到第一位线的读取辅助器件。读取辅助装置被配置为响应于从存储器单元读出的第一数据，将第一位线上的第一电压拉向预定电压。读取辅助装置包括第一电路，其被配置为在第一阶段期间在第一位线和预定电压的节点之间建立第一电流路径。读取辅助装置还包括第二电路，其被配置为在第二后续阶段期间在第一位线和预定电压的节点之间建立第二电流路径。

6. 发明申请

US20130194877A1 MEMORY AND METHOD OF OPERATING THE SAME 有权
标题翻译：存储器及其操作方法
公开(公告)号：US20130194877A1
公开(公告)日：2013-08-01
申请号：US13362847
申请日：2012-01-31
申请人： Jung-Ping YANG , Hong-Chen CHENG , Chih-Chieh CHIU , Chia-En HUANG , Cheng Hung LEE
发明人： Jung-Ping YANG , Hong-Chen CHENG , Chih-Chieh CHIU , Chia-En HUANG , Cheng Hung LEE
IPC分类号： G11C7/06 , G11C7/10
CPC分类号： G11C7/12 , G11C7/106 , G11C7/1087 , G11C7/18 , G11C11/419 , G11C2207/005
摘要： A memory includes a plurality of memory blocks, a plurality of global bit lines, a common pre-charging circuit, and a selection circuit. Each memory block includes a pair of bit lines, and a plurality of memory cells coupled to the pair of bit lines. Each global bit line is coupled to at least one of the memory blocks. The pre-charging circuit is configured to pre-charge the global bit lines, one at a time, to a pre-charge voltage. The selection circuit is coupled between the pre-charging circuit and the global bit lines, and configured to couple the global bit lines, one at a time, to the pre-charging circuit.
摘要翻译：存储器包括多个存储器块，多个全局位线，公共预充电电路和选择电路。每个存储块包括一对位线和耦合到该对位线的多个存储器单元。每个全局位线耦合到至少一个存储器块。预充电电路被配置为将全局位线一次一个地预充电到预充电电压。选择电路耦合在预充电电路和全局位线之间，并且被配置为将全局位线一次一个地耦合到预充电电路。

7. 发明申请

US20120243363A1 POWER LINE LAYOUT TECHNIQUES FOR INTEGRATED CIRCUITS HAVING MODULAR CELLS 有权
标题翻译：用于具有模块化电池的集成电路的功率线路布线技术
公开(公告)号：US20120243363A1
公开(公告)日：2012-09-27
申请号：US13492469
申请日：2012-06-08
申请人： Cheng Hung LEE
发明人： Cheng Hung LEE
IPC分类号： G11C5/14
CPC分类号： H01L27/0207 , H01L27/105
摘要： An integrated circuit (IC) chip includes a first memory cell array block having a first metal layer containing at least two power lines, and a second memory cell array block containing at least two power lines independent of each other, wherein all the power lines on the first metal layer serving the first memory cell array block do not extend into the second memory cell array block, and all the power lines on the first metal layer serving the second memory cell array block do not extend into the first memory cell array block.
摘要翻译：集成电路（IC）芯片包括具有包含至少两条电源线的第一金属层的第一存储单元阵列块和包含彼此独立的至少两条电源线的第二存储单元阵列块，其中所有电源线在服务于第一存储单元阵列块的第一金属层不延伸到第二存储单元阵列块中，并且服务于第二存储单元阵列块的第一金属层上的所有电力线不延伸到第一存储单元阵列块中。

8. 发明申请

US20120106269A1 MEMORY CIRCUIT AND METHOD OF OPERATING THE SAME 有权
标题翻译：存储器电路及其操作方法
公开(公告)号：US20120106269A1
公开(公告)日：2012-05-03
申请号：US12913087
申请日：2010-10-27
申请人： Cheng Hung LEE , Jung-Ping YANG
发明人： Cheng Hung LEE , Jung-Ping YANG
IPC分类号： G11C7/12
CPC分类号： G11C7/12 , G11C7/067
摘要： The present application discloses a memory circuit having a first data line configured to carry a first data line signal and a second data line configured to carry a second data line signal. Further, a first driver is coupled to the first data line and the second data line and configured to establish a first current path for the first data line responsive to the second data line signal. Similarly, a second driver is coupled to the first data line and the second data line and configured to establish a second current path for the second data line responsive to the first data line signal. The memory circuit further has a first driver enabling line configured to selectively enable the first driver and a second driver enabling line configured to selectively enable the second driver.
摘要翻译：本申请公开了一种具有配置成承载第一数据线信号的第一数据线和被配置为承载第二数据线信号的第二数据线的存储器电路。此外，第一驱动器耦合到第一数据线和第二数据线，并且被配置为响应于第二数据线信号建立用于第一数据线的第一电流路径。类似地，第二驱动器耦合到第一数据线和第二数据线，并且被配置为响应于第一数据线信号为第二数据线建立第二电流路径。存储器电路还具有第一驱动器使能线，其被配置为选择性地使第一驱动器和第二驱动器使能线被配置为选择性地启用第二驱动器。

9. 发明申请

US20130010560A1 GENERATING AND AMPLIFYING DIFFERENTIAL SIGNALS 有权
标题翻译：生成和放大差分信号
公开(公告)号：US20130010560A1
公开(公告)日：2013-01-10
申请号：US13535075
申请日：2012-06-27
申请人： Chung-Ji LU , Hung-Jen LIAO , Cheng Hung LEE , Derek C. TAO , Annie-Li-Keow LUM , Hong-Chen CHENG
发明人： Chung-Ji LU , Hung-Jen LIAO , Cheng Hung LEE , Derek C. TAO , Annie-Li-Keow LUM , Hong-Chen CHENG
IPC分类号： H03F3/45 , G11C7/06
CPC分类号： G11C7/067 , G11C7/065
摘要： A circuit includes a first node, a second node, a first current mirror circuit, and a second current minor circuit. The first current mirror circuit has a reference end and a mirrored end. The reference end of the first current minor circuit is coupled to the first node, and the mirrored end of the first current minor circuit is coupled to the second node. The second current minor circuit has a reference end and a mirrored end. The reference end of the second current minor circuit is coupled to the second node, and the mirrored end of the second current minor circuit is coupled to the first node.
摘要翻译：电路包括第一节点，第二节点，第一电流镜电路和第二电流次要电路。第一电流镜电路具有参考端和镜像端。第一当前次要电路的参考端耦合到第一节点，并且第一当前次要电路的镜像端耦合到第二节点。第二个当前次级电路具有参考端和镜像端。第二电流次级电路的参考端耦合到第二节点，并且第二电流次级电路的镜像端耦合到第一节点。

10. 发明申请

US20130003445A1 SRAM CELLS, MEMORY CIRCUITS, SYSTEMS, AND FABRICATION METHODS THEREOF 有权
标题翻译： SRAM电池，存储器电路，系统及其制造方法
公开(公告)号：US20130003445A1
公开(公告)日：2013-01-03
申请号：US13609930
申请日：2012-09-11
申请人： Cheng Hung LEE , Hung-Jen LIAO
发明人： Cheng Hung LEE , Hung-Jen LIAO
IPC分类号： G11C11/40 , H01L21/8244
CPC分类号： G11C11/412
摘要： A static random access memory (SRAM) cell includes a pair of cross-coupled inverters having a first node and a second node. A first transistor is coupled between the first node and a first bit line. A second transistor is coupled between the second node and a second bit line. A third transistor is coupled with the first node. The third transistor has a threshold voltage that is higher than that of a fourth transistor of the pair of cross-coupled inverters by about 10% or more. A fifth transistor is coupled between the third transistor and a third bit line
摘要翻译：静态随机存取存储器（SRAM）单元包括具有第一节点和第二节点的一对交叉耦合的反相器。第一晶体管耦合在第一节点和第一位线之间。第二晶体管耦合在第二节点和第二位线之间。第三晶体管与第一节点耦合。第三晶体管具有比该对交叉耦合的反相器对的第四晶体管的阈值电压高约10％以上的阈值电压。第五晶体管耦合在第三晶体管和第三位线之间

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