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1. 发明授权

US07484138B2 Method and system for improving reliability of memory device 有权
标题翻译：提高存储器件可靠性的方法和系统
公开(公告)号：US07484138B2
公开(公告)日：2009-01-27
申请号：US11450535
申请日：2006-06-09
申请人： Chen-Hui Hsieh , Kun Lung Chen , Shine Chien Chung , Grigori Grigoriev
发明人： Chen-Hui Hsieh , Kun Lung Chen , Shine Chien Chung , Grigori Grigoriev
IPC分类号： G11C29/00 , G01R31/28
CPC分类号： G11C29/24 , G11C29/26 , G11C29/4401 , G11C29/802
摘要： A system for improving reliability of a memory device includes one or more memory banks, each of which has one or more regular memory cell rows and one or more redundant memory cell rows. At least one built-in-self-test (BIST) unit is coupled to the memory banks for testing the redundant memory cell rows to determine their respective quality standards, and testing the regular memory cell rows to identify the regular memory cell row that fails to pass a predetermined quality standard. At least one built-in-self-repair (BISR) unit is coupled to the BIST unit for replacing the failed regular memory cell row with the redundant memory cell row having a quality standard equal to or higher than the predetermined quality standard. The BIST unit repeatedly tests the regular memory cell rows a number of times, with each time applying a different quality standard.
摘要翻译：一种用于提高存储器件的可靠性的系统包括一个或多个存储体，每个存储体具有一个或多个常规存储单元行和一个或多个冗余存储单元行。至少一个内置自检（BIST）单元耦合到存储体，用于测试冗余存储单元行以确定其相应的质量标准，并测试常规存储单元行以识别出错的常规存储单元行通过一个预定的质量标准。至少一个内置自修复（BISR）单元耦合到BIST单元，以用具有等于或高于预定质量标准的质量标准的冗余存储单元行替换故障的常规存储单元行。 BIST单元反复测试常规存储单元行多次，每次应用不同的质量标准。

2. 发明申请

US20070291560A1 Method and system for improving reliability of memory device 有权
标题翻译：提高存储器件可靠性的方法和系统
公开(公告)号：US20070291560A1
公开(公告)日：2007-12-20
申请号：US11450535
申请日：2006-06-09
申请人： Chen-Hui Hsieh , Kun Lung Chen , Shine Chien Chung , Grigori Grigoriev
发明人： Chen-Hui Hsieh , Kun Lung Chen , Shine Chien Chung , Grigori Grigoriev
IPC分类号： G06F11/00 , G11C29/00 , G11C7/00
CPC分类号： G11C29/24 , G11C29/26 , G11C29/4401 , G11C29/802
摘要： A system for improving reliability of a memory device includes one or more memory banks, each of which has one or more regular memory cell rows and one or more redundant memory cell rows. At least one built-in-self-test (BIST) unit is coupled to the memory banks for testing the redundant memory cell rows to determine their respective quality standards, and testing the regular memory cell rows to identify the regular memory cell row that fails to pass a predetermined quality standard. At least one built-in-self-repair (BISR) unit is coupled to the BIST unit for replacing the failed regular memory cell row with the redundant memory cell row having a quality standard equal to or higher than the predetermined quality standard. The BIST unit repeatedly tests the regular memory cell rows a number of times, with each time applying a different quality standard.
摘要翻译：一种用于提高存储器件的可靠性的系统包括一个或多个存储体，每个存储体具有一个或多个常规存储单元行和一个或多个冗余存储单元行。至少一个内置自检（BIST）单元耦合到存储体，用于测试冗余存储单元行以确定其相应的质量标准，并测试常规存储单元行以识别出错的常规存储单元行通过一个预定的质量标准。至少一个内置自修复（BISR）单元耦合到BIST单元，以用具有等于或高于预定质量标准的质量标准的冗余存储单元行替换故障的常规存储单元行。 BIST单元反复测试常规存储单元行多次，每次应用不同的质量标准。

3. 发明授权

US08261219B2 System on chip development with reconfigurable multi-project wafer technology 有权
标题翻译：系统片上开发与可重构多项目晶圆技术
公开(公告)号：US08261219B2
公开(公告)日：2012-09-04
申请号：US12133323
申请日：2008-06-04
申请人： Kun-Lung Chen , Shine Chien Chung , Yung-Chin Hou , Yu-Chun Wu
发明人： Kun-Lung Chen , Shine Chien Chung , Yung-Chin Hou , Yu-Chun Wu
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method is disclosed for designing a semiconductor circuit on a multi-project wafer (MPW). One or more standard modules designed by one or more vendors with verified functions are first identified. Some of the standard modules are charged based on usage. At least one reconfigurable module of the MPW is programmed by making one or more connections through one or more connection layers. The standard modules are further connected with the programmed reconfigurable module according to the predetermined design of the circuit. The completed circuit is then verified for final uses.
摘要翻译：公开了一种在多工程晶片（MPW）上设计半导体电路的方法。首先确定由具有验证功能的一个或多个供应商设计的一个或多个标准模块。一些标准模块根据用途收费。通过使一个或多个连接通过一个或多个连接层来编程MPW的至少一个可重新配置的模块。根据电路的预定设计，标准模块还与编程的可重配置模块进一步连接。完成的电路然后被验证用于最终用途。

4. 发明授权

US07797646B2 Method for using mixed multi-Vt devices in a cell-based design 有权
标题翻译：在基于单元的设计中使用混合多Vt设备的方法
公开(公告)号：US07797646B2
公开(公告)日：2010-09-14
申请号：US11844698
申请日：2007-08-24
申请人： Shine Chien Chung , Cliff Hou , Kun-Lung Chen , Lee-Chung Lu
发明人： Shine Chien Chung , Cliff Hou , Kun-Lung Chen , Lee-Chung Lu
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method is disclosed for utilizing mixed low threshold voltage (low-Vt) and high threshold voltage (high-Vt) devices in a cell-based design such that a tradeoff of both the circuit speed and power performance may be achieved. Using cells having non-uniform threshold devices for designing circuit, the speed or/and power optimization is comparable to fully custom designs.
摘要翻译：公开了一种在基于单元的设计中利用混合的低阈值电压（低Vt）和高阈值电压（高Vt）装置的方法，从而可以实现电路速度和功率性能的折衷。使用具有不均匀阈值器件的电池来设计电路，速度或/和功率优化与完全定制的设计相当。

5. 发明申请

US20080235635A1 SYSTEM ON CHIP DEVELOPMENT WITH RECONFIGURABLE MULTI-PROJECT WAFER TECHNOLOGY 有权
标题翻译：利用可重构多工程技术的芯片开发系统
公开(公告)号：US20080235635A1
公开(公告)日：2008-09-25
申请号：US12133323
申请日：2008-06-04
申请人： Kun-Lung Chen , Shine Chien Chung , Yung-Chin Hou , Yu-Chun Wu
发明人： Kun-Lung Chen , Shine Chien Chung , Yung-Chin Hou , Yu-Chun Wu
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method is disclosed for designing a semiconductor circuit on a multi-project wafer (MPW). One or more standard modules designed by one or more vendors with verified functions are first identified. Some of the standard modules are charged based on usage. At least one reconfigurable module of the MPW is programmed by making one or more connections through one or more connection layers. The standard modules are further connected with the programmed reconfigurable module according to the predetermined design of the circuit. The completed circuit is then verified for final uses.
摘要翻译：公开了一种在多工程晶片（MPW）上设计半导体电路的方法。首先确定由具有验证功能的一个或多个供应商设计的一个或多个标准模块。一些标准模块根据用途收费。通过使一个或多个连接通过一个或多个连接层来编程MPW的至少一个可重新配置的模块。根据电路的预定设计，标准模块还与编程的可重配置模块进一步连接。完成的电路然后被验证用于最终用途。

6. 发明授权

US07401302B2 System on chip development with reconfigurable multi-project wafer technology 有权
标题翻译：系统片上开发与可重构多项目晶圆技术
公开(公告)号：US07401302B2
公开(公告)日：2008-07-15
申请号：US11119086
申请日：2005-04-29
申请人： Kun-Lung Chen , Shine Chien Chung , Yung-Chin Hou , Yu-Chun Wu
发明人： Kun-Lung Chen , Shine Chien Chung , Yung-Chin Hou , Yu-Chun Wu
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method is disclosed for designing a semiconductor circuit on a multi-project wafer (MPW). One or more standard modules designed by one or more vendors with verified functions are first identified. Some of the standard modules are charged based on usage. At least one reconfigurable module of the MPW is programmed by making one or more connections through one or more connection layers. The standard modules are further connected with the programmed reconfigurable module according to the predetermined design of the circuit. The completed circuit is then verified for final uses.
摘要翻译：公开了一种在多工程晶片（MPW）上设计半导体电路的方法。首先确定由具有验证功能的一个或多个供应商设计的一个或多个标准模块。一些标准模块根据用途收费。通过使一个或多个连接通过一个或多个连接层来编程MPW的至少一个可重新配置的模块。根据电路的预定设计，标准模块还与编程的可重配置模块进一步连接。完成的电路然后被验证用于最终用途。

7. 发明授权

US07350177B2 Configurable logic and memory devices 有权
标题翻译：可配置的逻辑和存储设备
公开(公告)号：US07350177B2
公开(公告)日：2008-03-25
申请号：US11180936
申请日：2005-07-13
申请人： Shine Chien Chung , Yung-Chin Hou , Kun Lung Chen , Yu-Chun Wu
发明人： Shine Chien Chung , Yung-Chin Hou , Kun Lung Chen , Yu-Chun Wu
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , H03K19/17728 , H03K19/1776 , H03K19/17796
摘要： A configurable logic and memory block (CLMB) and a configurable logic device are disclosed. The CLMB includes one or more static random access memory (SRAM) cells, a first output module for generating a first output by reading at least one SRAM cell when the CLMB functions as an SRAM, a second output module for generating a second output by reading at least one SRAM cell when the CLMB functions as a program logic device (PLD), wherein data on one or more bitlines coupled to the SRAM cells are controllably feeding into the first and second output modules. The configurable logic device can provide various Boolean logic functions using pass gates.
摘要翻译：公开了可配置逻辑和存储器块（CLMB）和可配置逻辑器件。 CLMB包括一个或多个静态随机存取存储器（SRAM）单元，用于当CLMB用作SRAM时通过读取至少一个SRAM单元来产生第一输出的第一输出模块，用于通过读取产生第二输出的第二输出模块当CLMB用作程序逻辑器件（PLD）时，至少一个SRAM单元，其中耦合到SRAM单元的一个或多个位线上的数据被可控地馈送到第一和第二输出模块中。可配置逻辑器件可以使用传输门提供各种布尔逻辑功能。

8. 发明授权

US07281230B2 Method of using mixed multi-Vt devices in a cell-based design 有权
标题翻译：在基于单元的设计中使用混合多Vt设备的方法
公开(公告)号：US07281230B2
公开(公告)日：2007-10-09
申请号：US11111281
申请日：2005-04-20
申请人： Shine Chien Chung , Cliff Hou , Kun-Lung Chen , Lee-Chung Lu
发明人： Shine Chien Chung , Cliff Hou , Kun-Lung Chen , Lee-Chung Lu
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method is disclosed for utilizing mixed low threshold voltage (low-Vt) and high threshold voltage (high-Vt) devices in a cell-based design such that a tradeoff of both the circuit speed and power performance may be achieved. Using cells having non-uniform threshold devices for designing circuit, the speed or/and power optimization is comparable to fully custom designs.
摘要翻译：公开了一种在基于单元的设计中利用混合的低阈值电压（低Vt）和高阈值电压（高Vt）装置的方法，从而可以实现电路速度和功率性能的折衷。使用具有不均匀阈值器件的电池来设计电路，速度或/和功率优化与完全定制的设计相当。

9. 发明授权

US07495979B2 Method and system for in-situ parametric SRAM diagnosis 有权
标题翻译：原位参数化SRAM诊断方法与系统
公开(公告)号：US07495979B2
公开(公告)日：2009-02-24
申请号：US11089975
申请日：2005-03-25
申请人： Shine Chien Chung
发明人： Shine Chien Chung
IPC分类号： G11C7/00
CPC分类号： G11C29/48 , G11C29/1201 , G11C2029/1204 , G11C2029/5004
摘要： This invention is about a system for diagnosing memory cells in a memory module. A first multiplexer module selectively connects a diagnosis signal in response to a multiplexer control signal to a data line associated with a predetermined memory cell. A second multiplexer module connects the data line to the predetermined memory cell via the bit line in response to a bit selection signals. Similarly, a complement diagnosis signal may be connected to a predetermined memory cell via the complement data line and bit line through the same control and bit select signals. A pair of access pads are provided for passing the diagnosis signal and the complement diagnosis signal for external accessing.
摘要翻译：本发明涉及用于诊断存储器模块中的存储器单元的系统。第一复用器模块响应于多路复用器控制信号选择性地将诊断信号连接到与预定存储器单元相关联的数据线。第二多路复用器模块响应于位选择信号经由位线将数据线连接到预定的存储器单元。类似地，补码诊断信号可以经由补码数据线和位线通过相同的控制和比特选择信号连接到预定的存储器单元。提供一对通路用于传递用于外部访问的诊断信号和补码诊断信号。

10. 发明授权

US07523366B2 Storage efficient memory system with integrated BIST function 有权
标题翻译：具有集成BIST功能的存储高效存储系统
公开(公告)号：US07523366B2
公开(公告)日：2009-04-21
申请号：US11298127
申请日：2005-12-09
申请人： Shine Chien Chung
发明人： Shine Chien Chung
IPC分类号： G11C29/00 , G11C7/02 , G01R31/28
CPC分类号： G11C29/44 , G11C2029/1208
摘要： A method and system conduct built-in-self-test (BIST) in a circuit under test. After allocating at least one memory segment with a predetermined size in at least one memory module as a test result module, the built-in-self-test is conducted for the circuit under test without testing the test result module. The test results are stored in the test result module.
摘要翻译：一种方法和系统在被测电路中进行内置自检（BIST）。在作为测试结果模块的至少一个存储器模块中分配具有预定大小的至少一个存储器段之后，对被测电路进行内置自检，而不测试测试结果模块。测试结果存储在测试结果模块中。

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