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1. 发明授权

US08179695B2 Mirror image shielding structure 有权
标题翻译：镜像屏蔽结构
公开(公告)号：US08179695B2
公开(公告)日：2012-05-15
申请号：US12783478
申请日：2010-05-19
申请人： Uei-Ming Jow , Chin-Sun Shyu , Chang-Sheng Chen , Min-Lin Lee , Shinn-Juh Lai
发明人： Uei-Ming Jow , Chin-Sun Shyu , Chang-Sheng Chen , Min-Lin Lee , Shinn-Juh Lai
IPC分类号： H05K9/00
CPC分类号： H05K1/0218 , H05K1/0224 , H05K1/0237 , H05K1/025 , H05K1/162 , H05K1/165 , H05K1/167 , H05K2201/0792 , H05K2201/09672
摘要： A mirror image shielding structure is provided, which includes an electronic element and a ground shielding plane below the electronic element. The shape of the ground shielding plane is identical to the projection shape of the electronic element, and the horizontal size of the ground shielding plane is greater than or equal to that of the electronic element. Thus, the parasitic effect between the electronic element and the ground shielding plane is effectively reduced, and the vertical coupling effect between electronic elements is also reduced. Furthermore, the vertical impact on the signal integrity of the embedded elements caused by the layout of the transmission lines is prevented.
摘要翻译：提供一种镜像屏蔽结构，其包括电子元件和电子元件下方的接地屏蔽平面。接地屏蔽面的形状与电子元件的突出形状相同，接地屏蔽面的水平尺寸大于或等于电子元件的尺寸。因此，有效地减小了电子元件与接地屏蔽层之间的寄生效应，并且电子元件之间的垂直耦合效应也降低。此外，防止了由传输线的布局引起的对嵌入元件的信号完整性的垂直影响。

2. 发明授权

US08058956B2 High frequency and wide band impedance matching via 有权
标题翻译：高频和宽带阻抗匹配通孔
公开(公告)号：US08058956B2
公开(公告)日：2011-11-15
申请号：US12801673
申请日：2010-06-21
申请人： Uei-Ming Jow , Ching-Liang Weng , Ying-Jiunn Lai , Chang-Sheng Chen
发明人： Uei-Ming Jow , Ching-Liang Weng , Ying-Jiunn Lai , Chang-Sheng Chen
IPC分类号： H03H7/38 , H01P1/04
CPC分类号： H05K1/0251 , H01L23/66 , H01L2223/6616 , H01L2223/6638 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H01P5/02 , H05K1/0222 , H05K1/0245 , H05K1/115 , H05K1/116 , H05K3/429 , H05K2201/09236 , H05K2201/09454 , H05K2201/09618 , H05K2201/09627 , H05K2201/09809 , H05K2201/09845 , H01L2924/00
摘要： A high frequency and wide band impedance matching via is provided, applicable to multi-layer printed circuit boards, for example. The multi-layer circuit board may include several signal transmission traces, several ground layers, signal transmission vias and ground vias. The signal transmission traces and the ground layers may be sited on different circuit layers, and each signal transmission trace may be opposite to one of the ground layers. The signal transmission vias may be connected between the signal transmission traces. The ground vias may be connected between the ground layers. The ground vias may be opposite to the signal transmission vias, and the ground vias corresponding to the signal transmission vias may be sited to stabilize the characteristic impedance of the transmission traces.
摘要翻译：提供了高频和宽带阻抗匹配通孔，例如适用于多层印刷电路板。多层电路板可以包括几个信号传输迹线，几个接地层，信号传输通路和接地通孔。信号传输迹线和接地层可以位于不同的电路层上，并且每个信号传输迹线可以与一个接地层相反。信号传输通孔可以连接在信号传输迹线之间。接地通孔可以连接在接地层之间。接地通孔可能与信号传输通孔相反，并且可能选择对应于信号传输通孔的接地通孔来稳定传输迹线的特性阻抗。

3. 发明申请

US20110169597A1 INDUCTOR DEVICES 有权
标题翻译：电感器件
公开(公告)号：US20110169597A1
公开(公告)日：2011-07-14
申请号：US13009432
申请日：2011-01-19
申请人： Chang-Lin Wei , Kuo-Chiang Chin , Cheng-Hua Tsai , Chin-Sun Shyu , Chang-Sheng Chen
发明人： Chang-Lin Wei , Kuo-Chiang Chin , Cheng-Hua Tsai , Chin-Sun Shyu , Chang-Sheng Chen
IPC分类号： H01F5/00
CPC分类号： H01F17/0013 , H01F17/02 , H01F30/08 , H01F2017/002 , H01F2017/0046
摘要： An inductor device comprising a first conductive pattern on a first layer of a substrate, a second conductive pattern on a second layer of the substrate, and a first region between the first layer and the second layer through which at least one hole is coupled between the first dielectric layer and the second dielectric layer, wherein a magnetic field induced by at least one of the first conductive pattern or the second conductive pattern at the first region is more intensive than that induced by at least one of the first conductive pattern or the second conductive pattern at a second region between the first conductive layer and the second conductive layer.
摘要翻译：一种电感器装置，包括在衬底的第一层上的第一导电图案，在衬底的第二层上的第二导电图案，以及在第一层和第二层之间的第一区域，至少一个孔通过该第一区耦合在第一电介质层和第二介电层，其中由第一区域中的第一导电图案或第二导电图案中的至少一个感应的磁场比由第一导电图案或第二介电层中的至少一个所诱发的磁场更加密集导电图案在第一导电层和第二导电层之间的第二区域。

4. 发明授权

US07948355B2 Embedded resistor devices 失效
标题翻译：嵌入式电阻器件
公开(公告)号：US07948355B2
公开(公告)日：2011-05-24
申请号：US11852244
申请日：2007-09-07
申请人： Chang-Lin Wei , Chang-Sheng Chen , Cheng-Hua Tsai , Syun Yu , Chin-Sun Shyu
发明人： Chang-Lin Wei , Chang-Sheng Chen , Cheng-Hua Tsai , Syun Yu , Chin-Sun Shyu
IPC分类号： H01C1/012
CPC分类号： H05K1/167 , H05K1/0237 , H05K1/0298 , H05K2201/09781
摘要： An embedded resistor device includes a resistor, a ground plane located near a first side of the resistor and electrically coupled to a first end of the resistor, at the ground plane a hole is provided, a first dielectric layer exists between the resistor and the ground plane, a conductive wire, which is electrically coupled to a second end of the resistor different from the first end of the resistor and partially surrounds the resistor, is used as an auxiliary for supporting a resistor-coating process of the resistor and to provide a terminal of the embedded resistor device at the conductive wire, a conductive region located near a second side of the ground plane different from the first side of the resistor, a second dielectric layer exists between the ground plane and the conductive region, and a conductive path to electrically couple the conductive wire to the conductive region through the hole.
摘要翻译：嵌入式电阻器件包括电阻器，接地平面位于电阻器的第一侧附近并电耦合到电阻器的第一端，在接地平面处设有一个孔，第一电介质层位于电阻器和地之间平面，电耦合到电阻器的不同于电阻器的第一端并部分地围绕电阻器的第二端的导线被用作支持电阻器的电阻器涂覆工艺的辅助件，并且提供在导电线处的嵌入式电阻器件的端子，位于接地平面的与电阻器的第一侧不同的第二侧附近的导电区域，在接地平面和导电区域之间存在第二介电层，并且导电路径以通过该孔将导线电连接到导电区域。

5. 发明授权

US07868727B2 Inter-helix inductor devices 有权
标题翻译：螺旋电感器件
公开(公告)号：US07868727B2
公开(公告)日：2011-01-11
申请号：US12133717
申请日：2008-06-05
申请人： Wei-Ting Chen , Chang-Sheng Chen , Chin-Sun Shyu , Chang-Lin Wei
发明人： Wei-Ting Chen , Chang-Sheng Chen , Chin-Sun Shyu , Chang-Lin Wei
IPC分类号： H01F5/00 , H01F27/29 , H01F27/28
CPC分类号： H01F17/0013 , H01F2017/002 , H01F2017/004
摘要： The invention is directed to inter-helix inductor devices. The inter-helix inductor device includes a dielectric substrate. An input end is disposed on the first surface of the dielectric substrate. A clockwise winding coil has one end connecting to the input end and at least one winding turn through the dielectric substrate. A counter clockwise winding coil includes at least one winding turn through the dielectric substrate, wherein the clockwise and counter clockwise winding coils are connected by an interconnection. An output end is disposed on the dielectric substrate, connects one end of the counter clockwise winding coil, and is adjacent to the input end.
摘要翻译：本发明涉及螺旋间电感器件。螺旋间电感器件包括电介质基片。输入端设置在电介质基板的第一表面上。顺时针缠绕线圈的一端连接到输入端，并且至少一个绕组转过电介质基片。逆时针绕组线圈包括穿过电介质基板的至少一个绕组匝，其中顺时针和逆时针绕组线圈通过互连连接。输出端设置在电介质基板上，连接逆时针绕组线圈的一端，并与输入端相邻。

6. 发明申请

US20090225224A1 System and method for processing a television picture-out-picture 有权
标题翻译：用于处理电视机画面的系统和方法
公开(公告)号：US20090225224A1
公开(公告)日：2009-09-10
申请号：US12285720
申请日：2008-10-14
申请人： Yu-Yu Sung , Chang-Sheng Chen , Chiung-Sui Liu
发明人： Yu-Yu Sung , Chang-Sheng Chen , Chiung-Sui Liu
IPC分类号： H04N5/44
CPC分类号： H04N5/45 , H04N21/4307 , H04N21/4316 , H04N21/4347 , H04N21/440263
摘要： A system for processing a television (TV) picture-out-picture (POP) includes a line buffer, a first multiplexer, an image processing engine, a scaling engine and a timing generator. The line buffer receives partial pixels of a first picture and partial pixels of a second picture. The first multiplexer selects the partial pixels of the first and second picture as an output. The image processing engine performs an image processing on the partial pixels output by the first multiplexer to thereby produce processed pixels. The scaling engine performs a scaling operation on the processed pixels to thereby produce scaled pixels. The timing generator produces a timing signal for the image processing engine and the scaling engine and produces enable signals respectively for the first picture and the second picture. The image processing engine and the scaling engine process the partial pixels of the first or second picture in multiplexing.
摘要翻译：一种用于处理电视（TV）画面显示（POP）的系统包括行缓冲器，第一多路复用器，图像处理引擎，缩放引擎和定时发生器。行缓冲器接收第一图像的部分像素和第二图像的部分像素。第一多路复用器选择第一和第二图像的部分像素作为输出。图像处理引擎对由第一多路复用器输出的部分像素执行图像处理，从而产生经处理的像素。缩放引擎对经处理的像素执行缩放操作，从而产生缩放的像素。定时发生器产生用于图像处理引擎和缩放引擎的定时信号，并分别为第一图像和第二图像产生使能信号。图像处理引擎和缩放引擎在多路复用中处理第一或第二图像的部分像素。

7. 发明授权

US07529103B2 Multi-layered printed circuit board embedded with filter 失效
标题翻译：多层印刷电路板嵌入式滤波器
公开(公告)号：US07529103B2
公开(公告)日：2009-05-05
申请号：US11438363
申请日：2006-05-23
申请人： Chang-Sheng Chen , Uei-Ming Jow , Ying-Jiunn Lai , Chin-Sun Shyu
发明人： Chang-Sheng Chen , Uei-Ming Jow , Ying-Jiunn Lai , Chin-Sun Shyu
IPC分类号： H05K1/14
CPC分类号： H05K1/162 , H03H7/09 , H03H7/1775 , H03H2001/0085 , H05K3/4626 , H05K3/4688 , H05K2201/09236 , H05K2201/09672
摘要： A multi-layered printed circuit board embedded with a filter, the multi-layered printed circuit board using a composite multi-layered printed circuit board formed of at least a high dielectric material stacked with at least a low dielectric material. A plurality of serial or parallel capacitors are disposed in the composite multi-layered printed circuit board so as to form a filter. At least one capacitor is an interdigital capacitor disposed on a low dielectric material. Metal electrodes of the interdigital capacitor are located on the same plane such that the area of the metal electrodes or the spacing between the metal electrodes can be adjusted in advance to precisely control the electrical properties such as the center frequency and the transmission loss of the filter. Problems resulting from alignment errors caused in manufacturing the composite multi-layered printed circuit board can also be prevented.
摘要翻译：嵌入滤光器的多层印刷电路板，使用由至少由至少低介电材料层叠的高介电材料形成的复合多层印刷电路板的多层印刷电路板。多个串联或并联电容器设置在复合多层印刷电路板中以形成滤波器。至少一个电容器是设置在低电介质材料上的叉指电容器。叉指电容器的金属电极位于同一平面上，使得金属电极的面积或金属电极之间的间隔可以预先调整以精确地控制诸如滤波器的中心频率和传输损耗之类的电气特性。也可以防止在制造复合多层印刷电路板时引起的对准误差所引起的问题。

8. 发明授权

US07446995B2 Symmetrical capacitor 有权
标题翻译：对称电容器
公开(公告)号：US07446995B2
公开(公告)日：2008-11-04
申请号：US11362115
申请日：2006-02-27
申请人： Uei-Ming Jow , Ying-Jiunn Lai , Chang-Sheng Chen , Ching-Liang Weng
发明人： Uei-Ming Jow , Ying-Jiunn Lai , Chang-Sheng Chen , Ching-Liang Weng
IPC分类号： H01G4/005 , H01G4/228
CPC分类号： H01G4/005 , H01G4/228
摘要： A symmetrical capacitor includes at least a first metal layer and a second metal layer. Each of the metal layers has a first electrode plate and a second electrode plate separated by a predetermined distance. The first electrode plates on the metal layers are symmetrical, and the second electrode plates on the metal layers are symmetrical. Given the symmetrical structure of the capacitor, the output ports of the capacitor have the same electrical features. Therefore, there will not be a direction problem when the capacitor is used, and the symmetrical electrical features are improved.
摘要翻译：对称电容器包括至少第一金属层和第二金属层。每个金属层具有分隔预定距离的第一电极板和第二电极板。金属层上的第一电极板是对称的，金属层上的第二电极板是对称的。给定电容器的对称结构，电容器的输出端口具有相同的电气特性。因此，当使用电容器时不会有方向问题，并且改善对称的电气特征。

9. 发明申请

US20070183131A1 Mirror image shielding structure 有权
标题翻译：镜像屏蔽结构
公开(公告)号：US20070183131A1
公开(公告)日：2007-08-09
申请号：US11451292
申请日：2006-06-12
申请人： Uei-Ming Jow , Chin-Sun Shyu , Chang-Sheng Chen , Min-Lin Lee , Shinn-Juh Lai
发明人： Uei-Ming Jow , Chin-Sun Shyu , Chang-Sheng Chen , Min-Lin Lee , Shinn-Juh Lai
IPC分类号： H04B3/28 , H05K9/00
CPC分类号： H05K1/0218 , H05K1/0224 , H05K1/0237 , H05K1/025 , H05K1/162 , H05K1/165 , H05K1/167 , H05K2201/0792 , H05K2201/09672
摘要： A mirror image shielding structure is provided, which includes an electronic element and a ground shielding plane below the electronic element. The shape of the ground shielding plane is identical to the projection shape of the electronic element, and the horizontal size of the ground shielding plane is greater than or equal to that of the electronic element. Thus, the parasitic effect between the electronic element and the ground shielding plane is effectively reduced, and the vertical coupling effect between electronic elements is also reduced. Furthermore, the vertical impact on the signal integrity of the embedded elements caused by the layout of the transmission lines is prevented.
摘要翻译：提供一种镜像屏蔽结构，其包括电子元件和电子元件下方的接地屏蔽平面。接地屏蔽面的形状与电子元件的突出形状相同，接地屏蔽面的水平尺寸大于或等于电子元件的尺寸。因此，有效地减小了电子元件与接地屏蔽层之间的寄生效应，并且电子元件之间的垂直耦合效应也降低。此外，防止了由传输线的布局引起的对嵌入元件的信号完整性的垂直影响。

10. 发明申请

US20070025052A1 Symmetrical capacitor 有权
标题翻译：对称电容器
公开(公告)号：US20070025052A1
公开(公告)日：2007-02-01
申请号：US11362115
申请日：2006-02-27
申请人： Uei-Ming Jow , Ying-Jiunn Lai , Chang-Sheng Chen , Ching-Liang Weng
发明人： Uei-Ming Jow , Ying-Jiunn Lai , Chang-Sheng Chen , Ching-Liang Weng
IPC分类号： H01G4/005
CPC分类号： H01G4/005 , H01G4/228
摘要： A symmetrical capacitor includes at least a first metal layer and a second metal layer. Each of the metal layers has a first electrode plate and a second electrode plate separated by a predetermined distance. The first electrode plates on the metal layers are symmetrical, and the second electrode plates on the metal layers are symmetrical. Given the symmetrical structure of the capacitor, the output ports of the capacitor have the same electrical features. Therefore, there will not be a direction problem when the capacitor is used, and the symmetrical electrical features are improved.
摘要翻译：对称电容器包括至少第一金属层和第二金属层。每个金属层具有分隔预定距离的第一电极板和第二电极板。金属层上的第一电极板是对称的，金属层上的第二电极板是对称的。给定电容器的对称结构，电容器的输出端口具有相同的电气特性。因此，当使用电容器时不会有方向问题，并且改善对称的电气特征。

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