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1. 发明授权

US06496443B2 Data buffer control circuits, integrated circuit memory devices and methods of operation thereof using read cycle initiated data buffer clock signals 失效
标题翻译：数据缓冲器控制电路，集成电路存储器件及其使用读周期启动的数据缓冲时钟信号的操作方法
公开(公告)号：US06496443B2
公开(公告)日：2002-12-17
申请号：US09726197
申请日：2000-11-29
申请人： Byung-Chul Kim , Seung Bum Ko
发明人： Byung-Chul Kim , Seung Bum Ko
IPC分类号： G11C800
CPC分类号： G11C7/225 , G11C7/1006 , G11C7/1012 , G11C7/1051 , G11C7/1057 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C2207/108
摘要： A data buffer control circuit provides a buffer clock signal to a data buffer of an integrated circuit memory device having a read cycle that is initiated by assertion of a read cycle control signal. A clock buffer circuit that receives an input clock signal and a clock buffer control signal, the clock buffer circuit operative to generate the buffer clock signal from the input clock signal when the clock buffer control signal is in a first state and to prevent generation of the buffer clock signal from the input clock signal when the clock buffer control signal is in a second state. A clock buffer control circuit is responsive to the read cycle control signal and to the clock signal and transitions the clock buffer control signal to the first state responsive to a first transition of the input clock signal following assertion of the read cycle control signal and that transitions the clock buffer control signal to the second state responsive to the end of the predetermined interval. A first half cycle of the input clock signal may commence with the first transition of the input clock signal, and the clock buffer control circuit may be operative to transition the clock buffer control signal to the first state following the first transition of the input clock signal and before the end of the first half cycle of the input clock signal.
摘要翻译：数据缓冲器控制电路将缓冲时钟信号提供给具有通过断言读周期控制信号启动的读周期的集成电路存储器件的数据缓冲器。时钟缓冲器电路，其接收输入时钟信号和时钟缓冲器控制信号，所述时钟缓冲器电路在时钟缓冲器控制信号处于第一状态时从输入时钟信号产生缓冲时钟信号，并且防止产生当时钟缓冲器控制信号处于第二状态时，来自输入时钟信号的缓冲时钟信号。时钟缓冲器控制电路响应于读周期控制信号和时钟信号，并且响应于在读周期控制信号的断言之后的输入时钟信号的第一转变而将时钟缓冲器控制信号转变到第一状态，时钟缓冲器控制信号响应于预定间隔的结束而处于第二状态。输入时钟信号的前半周期可以从输入时钟信号的第一次转变开始，并且时钟缓冲器控制电路可操作以在时钟缓冲器控制信号转换到第一状态之后，在输入时钟信号的第一次转换之后并在输入时钟信号的前半周期结束之前。

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