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1. 发明申请

US20120170373A1 SEMICONDUCTOR MEMORY DEVICE AND PROGRAM METHODS THEREOF 失效
标题翻译：半导体存储器件及其程序方法
公开(公告)号：US20120170373A1
公开(公告)日：2012-07-05
申请号：US13341382
申请日：2011-12-30
申请人： Byung Ryul KIM , Duck Ju KIM , You Sung KIM
发明人： Byung Ryul KIM , Duck Ju KIM , You Sung KIM
IPC分类号： G11C16/10 , G11C16/06
CPC分类号： G11C16/3454 , G11C11/5628 , G11C16/10
摘要： Programming a semiconductor memory device includes: performing a program loop using a blind program operation until the selected cell threshold voltages reach a first verification level; upon detecting a cell having the threshold voltage reaching the first verification level, verifying whether a cell having the threshold voltage reached a second verification level higher than the first verification level; upon verifying a cell having the threshold voltage reaching the second verification level, continuously performing program loops on cells having the first verification level as a target level and on cells having the second verification level as a target level; and upon verifying no cell having the threshold voltage reaching the second verification level, performing a program loop on memory cells having a target level higher than the first verification level, after programming the memory cells having the first verification level as the target level.
摘要翻译：编程半导体存储器件包括：使用盲目程序操作执行程序循环，直到所选择的单元阈值电压达到第一验证水平; 一旦检测到阈值电压达到第一验证电平的单元，则验证具有阈值电压的单元是否达到高于第一验证电平的第二验证电平; 在验证具有阈值电压达到第二验证电平的单元的情况下，对具有第一验证电平的单元作为目标电平，以及具有第二验证电平的单元作为目标电平连续执行程序循环; 并且在验证没有阈值电压达到第二验证电平的单元时，在将具有第一验证电平的存储单元编程为目标电平之后，对具有高于第一验证电平的目标电平的存储单元执行程序循环。

2. 发明申请

US20130163335A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US20130163335A1
公开(公告)日：2013-06-27
申请号：US13601882
申请日：2012-08-31
申请人： Byung Ryul KIM , Duck Ju KIM
发明人： Byung Ryul KIM , Duck Ju KIM
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/06 , G11C16/3436
摘要： A semiconductor memory device is operated by, inter alia, sequentially inputting program data to page buffers coupled to selected pages of at least four planes in order to program selected memory cells included in the selected pages; performing a program operation on each of the four planes; performing a program verify operation on each of the four planes; and inputting new program data for next pages to the page buffers coupled to the next pages, after determining the selected pages of at least two of the four planes have passed the program verify operation, while performing the program operations and the program verify operations on the two remaining planes.
摘要翻译：尤其是通过将程序数据顺序地输入到耦合到至少四个平面的选定页面的页缓冲器以便对包括在所选页中的所选择的存储单元进行编程来操作半导体存储器件; 在四个平面中的每一个上执行程序操作; 在四个平面中的每一个上执行程序验证操作; 并且在确定所述四个平面中的至少两个平面中的所选择的页面已经通过了程序验证操作之后，在对所述页面缓冲器执行所述程序操作和所述程序验证操作的同时，将用于下一页的新程序数据输入到耦合到所述下一页的页缓冲器剩下的两架飞机。

3. 发明申请

US20080175063A1 NAND FLASH MEMORY DEVICE AND METHOD OF IMPROVING CHARACTERISTIC OF A CELL IN THE SAME 失效
标题翻译： NAND闪速存储器件及改善其中的细胞特性的方法
公开(公告)号：US20080175063A1
公开(公告)日：2008-07-24
申请号：US11751014
申请日：2007-05-19
申请人： Ji Hye SON , Jun Seop JUNG , Duck Ju KIM
发明人： Ji Hye SON , Jun Seop JUNG , Duck Ju KIM
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5642
摘要： A non-volatile memory device includes a memory cell array, a page buffer, a cell characteristic detecting circuit, an X decoder and a Y decoder. The memory cell array has memory cells coupled to bit lines and word lines. The page buffer programs data to a selected memory cell or read data from the selected memory cell. The cell characteristic detecting circuit is coupled to a sensing node of the page buffer, and outputs a controlling signal in accordance with a distribution state of the memory cell using a read voltage and a program voltage about the selected memory cell. The X decoder selects a word line of the memory cell array in accordance with an inputted address. The Y decoder provides a path for inputting/outputting data in the selected memory cell. Here, the selected memory cell is programmed by using the program voltage corresponding to a program verifying voltage in accordance with the controlling signal outputted from the cell characteristic verifying circuit.
摘要翻译：非易失性存储器件包括存储单元阵列，页缓冲器，单元特性检测电路，X解码器和Y解码器。存储单元阵列具有耦合到位线和字线的存储单元。页面缓冲器将数据编程到选定的存储单元或从所选存储单元读取数据。单元特性检测电路耦合到页缓冲器的感测节点，并且使用关于所选存储单元的读取电压和编程电压，根据存储单元的分布状态输出控制信号。 X解码器根据输入的地址选择存储单元阵列的字线。 Y解码器提供用于在所选择的存储单元中输入/输出数据的路径。这里，根据从单元特性验证电路输出的控制信号，通过使用与程序验证电压相对应的编程电压对所选存储单元进行编程。

4. 发明申请

US20130070552A1 NON-VOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件
公开(公告)号：US20130070552A1
公开(公告)日：2013-03-21
申请号：US13488207
申请日：2012-06-04
申请人： Je Il RYU , Duck Ju KIM
发明人： Je Il RYU , Duck Ju KIM
IPC分类号： G11C8/10
CPC分类号： G11C8/14
摘要： A non-volatile memory device includes a plurality of memory blocks, first block switches configured to correspond to the respective odd-numbered memory blocks of the plurality of memory blocks and couple the word lines of the odd-numbered memory blocks and first local lines, second block switches configured to correspond to the respective even-numbered memory blocks of the plurality of memory blocks and couple the word lines of the even-numbered memory blocks and second local lines, a local line switch unit configured to selectively couple the first local lines or the second local lines and global word lines, and a high voltage generator configured to supply operating voltages to the global word lines.
摘要翻译：非易失性存储器件包括多个存储器块，第一块开关被配置为对应于多个存储器块中的各个奇数存储块并且耦合奇数存储块和第一局部线的字线，第二块开关，被配置为对应于所述多个存储器块中的相应的偶数存储块，并且耦合所述偶数存储块和第二本地线的字线;局部线路开关单元，被配置为选择性地耦合所述第一本地线或第二本地线路和全局字线，以及被配置为向全局字线提供工作电压的高压发生器。

5. 发明申请

US20100142282A1 METHOD OF PROGRAMMING FLASH MEMORY DEVICE 有权
标题翻译：编程闪存存储器件的方法
公开(公告)号：US20100142282A1
公开(公告)日：2010-06-10
申请号：US12702205
申请日：2010-02-08
申请人： You Sung KIM , Duck Ju KIM
发明人： You Sung KIM , Duck Ju KIM
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/5642
摘要： A method of programming data in a flash memory device is disclosed. The memory device includes a memory cell array which in turn includes at least one block, and the block in turn includes a plurality of pages. A program command to program a plurality of pages in the block is received. The plurality of pages is programmed in a predefined order. An address corresponding to a page that was programmed last amongst the plurality of pages is stored.
摘要翻译：公开了一种在闪速存储器件中编程数据的方法。存储器件包括存储单元阵列，该存储单元阵列又包括至少一个块，并且该块又包括多个页。接收用于对块中的多个页面进行编程的程序命令。多个页面以预定义的顺序被编程。存储与多个页面中最后编程的页面相对应的地址。

6. 发明申请

US20130083614A1 VOLTAGE SUPPLY CIRCUIT, SEMICONDUCTOR MEMORY DEVICE, AND OPERATING METHOD THEREOF 有权
标题翻译：电压电路，半导体存储器件及其工作方法
公开(公告)号：US20130083614A1
公开(公告)日：2013-04-04
申请号：US13614056
申请日：2012-09-13
申请人： Pil Seon YOO , Je Il RYU , Duck Ju KIM
发明人： Pil Seon YOO , Je Il RYU , Duck Ju KIM
IPC分类号： G11C7/00
CPC分类号： G11C8/14 , G11C8/08
摘要： A voltage supply circuit includes a high voltage generator configured to generate an operating voltage, a global word line switch configured to transfer the operating voltage to global word lines, a plurality of local line switches coupled to the global word lines and configured to transfer the operating voltage to corresponding local word lines, a precharge unit configured to supply a precharge voltage to an unselect local line switch adjacent to a select local line switch to which the operating voltage will be supplied, from among the plurality of local line switches, in a preparation section before an operation is started, and a coupling unit configured to couple the unselect local line switch and the global word line switch when the operation is started.
摘要翻译：电压供应电路包括被配置为产生工作电压的高电压发生器，配置成将工作电压传送到全局字线的全局字线开关，耦合到全局字线的多个局部线路开关，并被配置为传送操作电压到相应的本地字线;预充电单元，被配置为在多个本地线路开关中从多个本地线路开关中提供预充电电压到与所提供的工作电压的选择本地线路开关相邻的非选择本地线路开关，开始操作之前的部分，以及耦合单元，其被配置为当操作开始时耦合未选择的本地线路开关和全局字线开关。

7. 发明申请

US20120008397A1 MEMORY SYSTEM AND METHOD OF OPERATING THE SAME 有权
标题翻译：存储器系统及其操作方法
公开(公告)号：US20120008397A1
公开(公告)日：2012-01-12
申请号：US13178880
申请日：2011-07-08
申请人： Tai Sik SHIN , Duck Ju KIM , Dong Hyeon HAM
发明人： Tai Sik SHIN , Duck Ju KIM , Dong Hyeon HAM
IPC分类号： G11C16/10
CPC分类号： G11C11/5628 , G11C16/10
摘要： A memory system includes a flash memory device including a first memory block group on which a least significant bit (LSB) program operation has been performed and a program operation on another bit has not been performed and a second memory block group on which both the LSB program operation and a most significant bit (MSB) program operation have been performed and a memory controller configured to check which of the first and second memory block groups a memory block selected for an LSB data read operation belongs to and set a level of a read voltage for the LSB data read operation of the selected memory block.
摘要翻译：存储器系统包括闪速存储器件，其包括第一存储器块组，其上已经执行了最低有效位（LSB）编程操作，并且还没有执行对另一位的编程操作;以及第二存储块组，其中LSB 已经执行了程序操作和最高有效位（MSB）程序操作，并且存储器控制器被配置为检查选择用于LSB数据读取操作的存储器块属于哪个第一和第二存储块组，并设置读取的电平所选存储块的LSB数据读取操作的电压。

8. 发明申请

US20080205149A1 METHOD OF PROGRAMMING NON-VOLATILE MEMORY DEVICE 审中-公开
标题翻译：编程非易失性存储器件的方法
公开(公告)号：US20080205149A1
公开(公告)日：2008-08-28
申请号：US11771877
申请日：2007-06-29
申请人： Duck Ju KIM , Jong Hyun Wang
发明人： Duck Ju KIM , Jong Hyun Wang
IPC分类号： G11C7/00 , G11C11/34
CPC分类号： G11C16/30 , G11C16/10
摘要： A method of programming a non-volatile memory device enables a pump in response to a first program confirm command. The pump generates a voltage. An initial page of a memory block is programmed. Subsequent intermediate pages of the memory block are programmed in response to a second program confirm command while the pump remains enabled. A final page of the memory block is programmed in response to a third program confirm command. The pump is then disabled after the final page is programmed.
摘要翻译：一种编程非易失性存储器件的方法使泵响应于第一程序确认命令。泵产生电压。内存块的初始页被编程。当泵保持启用时，响应于第二程序确认命令来编程存储器块的随后中间页面。响应于第三程序确认命令编程存储块的最后一页。最后一页被编程后，泵被禁用。

9. 发明申请

US20120269007A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF READING OUT THE SAME 有权
标题翻译：半导体存储器件及其读出方法
公开(公告)号：US20120269007A1
公开(公告)日：2012-10-25
申请号：US13451110
申请日：2012-04-19
申请人： In Gon YANG , Duck Ju KIM , Jae Won CHA , Sung Hoon AHN , Tae Ho JEON
发明人： In Gon YANG , Duck Ju KIM , Jae Won CHA , Sung Hoon AHN , Tae Ho JEON
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C7/00 , G11C7/10 , G11C11/5642 , G11C16/0483
摘要： A semiconductor memory device includes a memory cell array configured to include memory cells, peripheral circuits configured to read out data stored in a selected memory cell in a read operation, and a controller configured to control the peripheral circuits so that the peripheral circuits sense a voltage level of the bit line when a first read voltage of the read voltages is supplied to the word line and the peripheral circuits sense voltage levels of the bit line when a second read voltage lower than the first read voltage by a specific level and a third read voltage higher than the first read voltage by the specific level are supplied to the word line in order to determine whether a threshold voltage of the selected memory cell falls within a set voltage distribution in the read operation.
摘要翻译：半导体存储器件包括：存储单元阵列，被配置为包括存储器单元，外围电路，被配置为在读取操作中读出存储在选择的存储单元中的数据;以及控制器，被配置为控制外围电路，使得外围电路感测电压当读取电压的第一读取电压被提供给字线时，位线的电平，并且当低于第一读取电压的第二读取电压达到特定电平和第三读取时，外围电路检测位线的电压电平将高于第一读取电压的特定电平的电压提供给字线，以便确定所选择的存储器单元的阈值电压是否落在读取操作中的设置电压分布内。

10. 发明申请

US20080158987A1 NON-VOLATILE MEMORY DEVICE AND DATA READ METHOD AND PROGRAM VERIFY METHOD OF NON-VOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件和非易失性存储器件的数据读取方法和程序验证方法
公开(公告)号：US20080158987A1
公开(公告)日：2008-07-03
申请号：US11751016
申请日：2007-05-19
申请人： Seong Hun PARK , Duck Ju KIM , Chang Won YANG
发明人： Seong Hun PARK , Duck Ju KIM , Chang Won YANG
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/24 , G11C16/3454
摘要： A non-volatile memory device includes an even bit line and an odd bit line, a first register, a second register, a first precharge unit, a second precharge unit and a bit line select unit. The even bit line and the odd bit line are connected to a memory cell array. The first register is connected to the even bit line and configured to store specific data. The second register is connected to the odd bit line and configured to store specific data. The first precharge unit precharges an even sense node, formed at a node of the even bit line and the first register, with a high level or supplies supplementary current to the even sense node. The second precharge unit precharges an odd sense node, formed at a node of the odd bit line and the second register, with a high level or supplies supplementary current to the odd sense node. The bit line select unit connects the even bit line and the even sense node and connects the odd bit line and the odd sense node.
摘要翻译：非易失性存储器件包括偶数位线和奇数位线，第一寄存器，第二寄存器，第一预充电单元，第二预充电单元和位线选择单元。偶数位线和奇数位线连接到存储单元阵列。第一个寄存器连接到偶数位线，并配置为存储特定数据。第二个寄存器连接到奇数位线，并配置为存储特定数据。第一预充电单元以偶数位线和第一寄存器的一个节点对偶数感测节点进行预充电，或者将高电平提供给偶校验节点。第二预充电单元以奇数位线和第二寄存器的节点处形成的奇数检测节点以高电平预充电，或者向奇检测节点提供辅助电流。位线选择单元连接偶数位线和偶数检测节点，并连接奇数位线和奇数检测节点。

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